Commit graph

4113 commits

Author SHA1 Message Date
Wasim Khan
e93a7caf86 armv8: Update LX2160A/LX2120A/LX2080A SVR value
LX2160A/LX2120A/LX2080A SVR value should be
0x873600/0x873620/0x873602
Previous values were valid only if CAN fuse is blown.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21 15:34:18 +05:30
Yuantian Tang
54d5c06cb9 armv8: ls1028a: disable multimedia for ls1027a, ls1017a
ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a.
Both ls1027a and ls1017a personalities are lower functionality version
which doesn't support the multimedia subsystems, like LCD, GPU.

To disable multimedia feature on non-multimedia version,
set the status property to disabled in dts nodes.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21 15:34:17 +05:30
Ran Wang
3d23b6c583 armv8: fsl-layerscape: Make USB masters snoopable
Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and
SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write
snoop signal on LS1043A and LS1046A.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21 15:34:17 +05:30
Kuldeep Singh
bb6f3c0f76 armv7: ls102xa: Update SCFG_QSPI_CLKSEL value
Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5
which means ClusterPLL/16

Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21 15:34:17 +05:30
Yuantian Tang
6ed6952383 armv8: ls1028a: Add more personalities support
Add LS1027A, LS1018A and LS1017A personalities support to
LS1028A SoC family.

LS1028A is the prime personality of LS1028A SoC family.
LS1027A is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.

The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72
core, low power versions of the QorIQ LS1028A and LS1027A
SoCs respectively.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21 15:34:17 +05:30
Tom Rini
6f1f28b8e1 u-boot-imx-20191014
-------------------
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
 
 	- logicpd pinmux
 	- i.MX7ULP: imx_ddr_size
 	- fixes Toradex i.MX6/i.MX7
 	- pico-imx7d
 	- tpc70 converted to DM
 	- New Board: meerkat96
 	- add HAB version command
 	- i.MX8 :
       		imx8: Jump from alias to OCRAM address at SPL init
       		imx8qm/qxp: Set SPL TEXT base to OCRAM base
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Merge tag 'u-boot-imx-20191014' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191014
-------------------

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628

	- logicpd pinmux
	- i.MX7ULP: imx_ddr_size
	- fixes Toradex i.MX6/i.MX7
	- pico-imx7d
	- tpc70 converted to DM
	- New Board: meerkat96
	- add HAB version command
	- i.MX8 :
      		imx8: Jump from alias to OCRAM address at SPL init
      		imx8qm/qxp: Set SPL TEXT base to OCRAM base
2019-10-14 13:00:51 -04:00
Tom Rini
fae7948011 Merge tag 'mmc-10-10-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- Add sdhci driver for Broadcom iProc platform
- Add a driver callback for power-cycle for mmc
- Implement host_power_cycle callback for stm32_sdmmc2
- spl: dm_mmc: Initialize only the required mmc device
2019-10-14 07:28:32 -04:00
Sjoerd Simons
b4eca2d787 imx :hab: Add hab version command
THe RVT data includes a major and minor version in its header
parameter. Add a new command to print this out.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2019-10-14 09:31:41 +02:00
Ye Li
9a2738581a imx8: Jump from alias to OCRAM address at SPL init
When running SPL on iMX8, the A core starts at address 0
which is a alias to OCRAM 0x100000.
The alias only map first 96KB of OCRAM, so this require the
SPL size can't beyond 96KB. But when using SPL DM, the size increase
significantly and may exceed 96KB.
So to fix the problem, we will change SPL linker address to OCRAM
address 0x100000. And then jump to the absolute address not the PC relative
address for entering OCRAM.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-10-13 22:49:12 +02:00
Rasmus Villemoes
26c1060951 ARM: asm/io.h: remove redundant #if !defined(readb) block
readb is unconditionally defined earlier in io.h, so there's no point
checking whether it's undefined.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-10-11 15:33:27 -04:00
Rasmus Villemoes
909d0399a5 ARM: asm/io.h: kill off confusing #ifdef __mem_pci block
No ARM board seems to define __mem_pci - and if it did, one would get tons of

  ./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined

warnings, because readl and friends are unconditionally defined
earlier in io.h. Moreover, the redefinitions lack the memory barriers
that the first definitions have. So I'm guessing this is practically
dead code.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-10-11 15:33:27 -04:00
Arun Parameswaran
36645f45a0 drivers: mmc: Add sdhci driver for Broadcom iProc platform
Add SDHCI driver for iProc family of Broadcom devices.

Signed-off-by: Corneliu Doban <corneliu.doban@broadcom.com>
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Pavithra Ravi <pavithra.ravi@broadcom.com>
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
2019-10-10 10:59:48 +08:00
Stefano Babic
d714a75fd4 imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross
architecture purposes. If Secure Boot is required for imx, this means to
enable and use the HAB processor in the soc.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-10-08 16:36:37 +02:00
Peng Fan
4d81755272 misc: imx8: add more scfw api
Add more scfw api for clk/partition/seco usage
The api will be used by ccf/partition/secure boot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
5f24d0cb9c imx8m: add clk support for i.MX8MM
Introduce clk implementation for i.MX8MM, including pll configuration,
ccm configuration. Mostly will be done clk dm driver,
but such as DRAM part, we still use non clk dm driver, because we
have limited sram.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
8838cdf10d imx8m: restructure clock.h
i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
1c7cba9fa7 imx: add i.MX8MM PE property
i.MX8MM does not have LVTTL, it has a PE property

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
e246b7ad74 imx8m: add pin header for i.MX8MM
Add pin header file for i.MX8MM

To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
selected.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
20ebb4fa75 imx8m: update imx-regs for i.MX8MM
i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and register layout change.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
4800df0cb0 imx8m: imx-regs: drop unused register definitions
Drop unused register definitions and structures for i.MX8MQ

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
65a6c50095 imx: add i.MX8MM cpu type
Add i.MX8MM cpu type and related helper functions

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Patrick Wildt
d08a194871 imx: add support for i.MX8MQ power domain controller
Add support for the power domain controller that's used on the
i.MX8MQ.  This will be needed to be able to power on the PCIe
controller.  Bindings taken from Linux, driver implementation
taken from the i.MX8 power domain controller and adjusted for
the i.MX8M SoC.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-10-08 16:36:36 +02:00
Peng Fan
8cacd788b4 imx: scu_api: add sc_pm_is_partition_started
Add sc_pm_is_partition_started to check whether a partition
has been started. This will be used to detect M4 partition booted up or
not, then we could choose which dtb to use. If M4 is up, we need
use dtb, such as imx8qm-mek-rpmsg.dtb.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:59 +02:00
Peng Fan
fefe051335 imx8: save args passed from ATF
We use information from ATF to know whether OP-TEE is running or not.
So save args passed from ATF.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:59 +02:00
Peng Fan
268644735b imx: scu_api: add sc_rm_set_master_sid
Add sc_rm_set_master_sid to set stream sid of masters to make
sure they could use smmu.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:59 +02:00
Peng Fan
b5fd5fd5a4 imx: sys_proto: add is_imx8qm helper
Add is_imx8qm helper which could be used by SoC and Driver code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:59 +02:00
Peng Fan
7b86cd4274 imx8: support parsing i.MX8 Container file
Add parsing i.MX8 Container file support, this is to let
SPL could load images in a container file to destination address.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:58 +02:00
Ye Li
df3572e930 i.MX7ULP: Set A7 core frequency to 500Mhz for B0 chip
The normal target frequency for ULP A7 core is 500Mhz, but now ROM
set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:16 +02:00
Ye Li
61bf6173cd i.MX7ULP: Fix wrong i2c configuration name
Wrong I2c driver configuration name is used in codes, so I2c driver is
not built. Correct it.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:16 +02:00
Ye Li
a0f4f7ee60 i.MX7ULP: Fix PCC register bits mask and offset issue
The offset for FRAC and the mask for PCD are not correct.
If we set FRAC, we can't get the right frequency. Fix them
to correct value.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:16 +02:00
Bai Ping
7777406a8a i.MX7ULP: Fix system reset after a7 rtc alarm expired.
The board will reboot if A7 core enter mem mode by rtc, then M4 core
enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
to fix this issue.
Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access
it. So check the CPU rev and not apply the settings for B0.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:35:16 +02:00
Peng Fan
e92fca66a3 imx: i.MX7ULP: add get_boot_device
Add get_boot_device for i.MX7ULP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
2019-10-08 16:35:16 +02:00
Peng Fan
81ae46c2e6 imx: add i.MX6ULZ cpu type
Add i.MX6ULZ cpu type and helper.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-10-08 16:33:45 +02:00
Yinbo Zhu
24cb6f2295 fsl-layerscape: Add fsl_esdhc peripheral clock support
Add esdhc peripheral clock support
for NXP layerscape platforms: LS1046ARDB, LS1043ARDB,
LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:00:35 +05:30
Eddie James
7764ee2e83 mmc: Add Aspeed SD controller driver
Add support for the Aspeed SD host controller engine.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2019-09-05 15:27:31 +08:00
Eddie James
38c9f08b41 clk: aspeed: Add support for SD clock
Add code to enable the SD clock on the ast2500 SoC.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-05 15:27:31 +08:00
Peng Fan
6dba0864ec i2c: mxc: add CONFIG_CLK support
When CONFIG_CLK enabled, use CLK UCLASS for clk related settings.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>

hs: removed hunk in mxc_i2c_probe() as not longer in code
2019-09-02 06:35:08 +02:00
Adam Ford
1bf330150c Convert CONFIG_ARCH_CPU_INIT to Kconfig
This converts the following to Kconfig:
   CONFIG_ARCH_CPU_INIT

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Tested-by: Felix Brack <fb@ltec.ch>
2019-08-25 19:32:55 -04:00
Rohan Garg
0482538499 rockchip: rk3399: derive ethaddr from cpuid
Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.

The MAC address is only generated and set if there is no ethaddr
present in the saved environment.

This is based off of Klaus Goger's work in 8adc9d

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23 18:15:31 +08:00
Laurentiu Tudor
b249fcba00 armv8: ls1028a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, edma, qdma, gpu, display and sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
5c6dc6c9a9 armv8: ls1088a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
aef654a2ed armv8: fsl-layerscape: make icid setup endianness aware
The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
08f9bc9f43 armv8: fsl-layerscape: add base addresses for several devices
Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
ef3f364a75 armv8: fsl-layerscape: add missing sec jr base address defines
Add defines for all the SEC job rings base addresses.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
bd9eab46c8 gpio: do not include <asm/arch/gpio.h> on ARCH_LS1088A
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls1088a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
b547dd9584 gpio: do not include <asm/arch/gpio.h> on ARCH_LS2080A
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls2080a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
dcfb8f516d gpio: do not include <asm/arch/gpio.h> on ARCH_LS1028A
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls1028a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
db717629ff gpio: do not include <asm/arch/gpio.h> on ARCH_LX2160A
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls2160a.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
068cabe8f6 drivers: i2c: mxc: Fix compiler error when using i2c dm mode
I2C dm mode enablemenet causes below compilation errors:

In file included from include/config.h:8:0,
                 from include/common.h:20:
include/config_fallbacks.h:51:4: error: #error "Cannot define
CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
 #  error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
    ^~~~~
In file included from include/config.h:8:0,
                 from include/common.h:20:
include/config_fallbacks.h:51:4: error: #error "Cannot define
CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
 #  error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
    ^~~~~

board/freescale/lx2160a/lx2160a.c: In function 'board_early_init_f':
board/freescale/lx2160a/lx2160a.c:108:2: warning: implicit declaration
of function 'i2c_early_init_f'; did you mean 'arch_early_init_r'?
[-Wimplicit-function-declaration]
  i2c_early_init_f();
  ^~~~~~~~~~~~~~~~
  arch_early_init_r

 drivers/i2c/mxc_i2c.c: In function 'mxc_i2c_probe':
  drivers/i2c/mxc_i2c.c:824:8: warning: implicit declaration of function
'enable_i2c_clk';
  did you mean 'enable_irq_wake'? [-Wimplicit-function-declaration]
  ret = enable_i2c_clk(1, bus->seq);
        ^~~~~~~~~~~~~~
        enable_irq_wake

So fix these compilation errors.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Tom Rini
60f38d82c4 - amlogic: add support for the SEI Robotic SEI510
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Merge tag 'u-boot-amlogic-20190812' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- amlogic: add support for the SEI Robotic SEI510
2019-08-12 23:03:35 -04:00
Tom Rini
9c6115822e Merge branch '2019-08-11-ti-imports'
- More DaVinci updates and fixes
- PCIe support on am65x
- Watchdog converted to DM
- Assorted other bugfixes
2019-08-12 18:47:53 -04:00
Suniel Mahesh
7659ea32a6 watchdog: omap_wdt: Convert watchdog driver to use DT and DM
This patch adds device tree and driver model watchdog support,
converts the legacy omap watchdog driver to driver model for
TI AM335x chipsets. The following compile warning is removed:

===================== WARNING ======================
This board does not use CONFIG_WDT (DM watchdog support).
Please update the board to use CONFIG_WDT before the
v2019.10 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

CONFIG_HW_WATCHDOG is no more a default option for AM33XX devices
after DT/DM conversion, adjusted kconfig accordingly.

DM watchdog support is enabled by default in SPL. The SPL image
doesn't fit into SRAM because of size constraints and build breaks
with an overflow. For this reason DM watchdog support should be
disabled in SPL, driver code should be adjusted accordingly to serve
this purpose.
Built and tested on AM335x device (BeagleboneBlack), compile tested
for all other AM33xx based boards.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-08-12 07:25:22 -04:00
Neil Armstrong
b1dd7debea arm: meson: add sm command to retrieve the reboot reason
The Secure Monitor offers multiple services, like returning the
SoC unique serial number, and can provide the "reboot reason" as
set by the previous booted system.

This extends the Amlogic specific "sm" cmd with a "reboot_reason" subcommand
to print or set a specified environment variable with the reboot reason in
human readable format.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:02:30 +02:00
Manivannan Sadhasivam
c62c7ef779 board: hisilicon: Add support for Hikey960 board
This commit adds board support for Hikey960 board from Hisilicon. This
board is one of the Consumer Edition boards of the 96Boards family
powered by Kirin960 SoC.

More information about this board can be found in 96Boards website:
https://www.96boards.org/product/hikey960/

The initial supported/tested devices include:
 - Debug serial
 - SD

With these support, it's good enough for loading Linux Kernel from SD.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Kever Yang
85a38742e0 rockchip: ram: add full feature rk3328 DRAM driver
This driver supports DDR3/LPDDR3/DDR4 SDRAM initialization.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit 9fb0777ec3 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:45 +08:00
Tom Rini
333755ef7b Merge branch '2019-07-29-ti-imports'
- More DaVinci DM migration, drop am18xx EVM platform
- Keystone bug fix
2019-07-29 17:59:15 -04:00
Bartosz Golaszewski
7bf9972643 nand: davinci: make davinci_nand_init() static
This function is only used within the driver itself. No need
to export it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-07-29 17:58:52 -04:00
Tom Rini
c957be9ba0 Merge tag 'u-boot-rockchip-20190729' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean up and migrate to use common rockchip spl board file
- Clean up and migrate to use common rockchip board file
- Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
2019-07-29 09:02:15 -04:00
Kever Yang
faa98c7c5a rockchip: rk3399: move chromebook bob specific flow to its board file
Add a board_early_init_f() in board_init_f() and move the board
specific init code into its own board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Tom Rini
df9a7a195b u-boot-imx-20190719
- CCF for i.MX6
 - nandbcb command to write SPL into NAND
 - Switch to DM (i.MX28)
 - Boards: Toradex, engicam, DH
 - Fixes for i.MX8
 - Fixes for i.MX7ULP
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
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Merge tag 'u-boot-imx-20190719' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20190719

- CCF for i.MX6
- nandbcb command to write SPL into NAND
- Switch to DM (i.MX28)
- Boards: Toradex, engicam, DH
- Fixes for i.MX8
- Fixes for i.MX7ULP

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
2019-07-27 09:35:05 -04:00
Kever Yang
bfcf15aad2 rockchip: declear boot_devices in bootrom.h
boot_devices may defined in soc file, and used in board file,
we need to delear it in header file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Kever Yang
cd59501f21 rockchip: intruduce common BROM_BOOTSOURCE_ID_ADDR
The boot source from BootRom is store at a fix offset of IRAM,
update to use the common macro instead of rk3399 specific one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Patrick Delaunay
e21e3ffdd1 psci: Fix warnings when compiling with W=1
This patch solves the following warnings:
arch/arm/mach-stm32mp/psci.c:

warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes]

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-24 14:15:38 -04:00
Kever Yang
0845a0ee66 rockchip: remove rk_timer
We have convert all SoC to use DM timer or ARM arch/generic
timer, we can remove this rk_timer now.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
25c6173099 rockchip: rk3288: move configure_l2ctlr back to rk3288
The configure_l2ctlr() is used only by rk3288, do not need to
locate in sys_proto.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
614d8ca438 arm: include: rockchip: Add rk3399 pmu file
Add pmu header file for rk3399 SoC, this will help
to configure pmu in sdram driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21 00:00:13 +08:00
Jagan Teki
a735550bb8 ram: rk3399: Add DdrMode
Add DdrMode structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
ed77ce728a ram: rk3399: Add ddrtimingC0
Add DdrTimingC0 structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
b713e0291b ram: rk3399: Add ddr version enc macro
Add dram config macro for handling ddr version number.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
01cc103915 ram: rk3399: Introduce sys_reg3 for more capacity info
cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
879f9fed6a ram: rk3399: Simply existing dram enc macro
Add simplified and meaningful macro for all setting.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash the similar patches into 1 patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Anatolij Gustschin
d87b2486e6 arm: imx8: don't duplicate build_info()
Move build_info() to common place.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Anatolij Gustschin
64b5f46975 arm: imx8: factor out uart init code
New imx8 boards started adding duplicated UART init code.
Factor out this to common function sc_pm_setup_uart().

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Peng Fan
7752a0fef7 misc: imx8: add sc_misc_get_temp
Add sc_misc_get_temp to support get temperature

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 15:16:54 +02:00
Shyam Saini
1d43e24b94 i.MX6: nand: add nandbcb command for imx
Writing/updating boot image in nand device is not
straight forward in i.MX6 platform and it requires
boot control block(BCB) to be configured.

It becomes difficult to use uboot 'nand' command to
write BCB since it requires platform specific attributes
need to be taken care of.

It is even difficult to use existing msx-nand.c driver by
incorporating BCB attributes like mxs_dma_desc does
because it requires change in mtd and nand command.

So, cmd_nandbcb implemented in arch/arm/mach-imx

BCB contains two data structures, Firmware Configuration Block(FCB)
and Discovered Bad Block Table(DBBT). FCB has nand timings,
DBBT search area, page address of firmware.

On summary, nandbcb update will
- erase the entire partition
- create BCB by creating 2 FCB/DBBT block followed by
  1 FW block based on partition size and erasesize.
- fill FCB/DBBT structures
- write FW/SPL on FW1
- write FCB/DBBT in first 2 blocks

for nand boot, up on reset bootrom look for FCB structure in
first block's if FCB found the nand timings are loaded for
further reads. once FCB read done, DTTB will load and finally
firmware will be loaded which is boot image.

Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
information.

Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
2019-07-19 14:51:25 +02:00
Jagan Teki
cb13534abe ram: rk3399: debug: Add sdram_print_stride
Add code to print the channel stride, this would help to
print the stride of associated channel.

Here is sample print on LPDDR4, 50MHz.
256B stride

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
07894f5aac ram: rockchip: debug: Add sdram_print_ddr_info
Add sdram ddr info print support, this would help to
observe the sdram base parameters.

Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
07112672a5 ram: rockchip: Add debug sdram driver
Add sdram driver to handle debug across rockchip SoCs.

This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
7757d1102f arm: include: rockchip: Add DDR4 enum
Add DDR4 enum number in common header.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
fafd2ad4df arm: include: rockchip: Move dramtypes to common header
dramtype enum numbers as common across all dram controllers
in rockchip, so move the eneum values in common header.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
e5e444aaa5 ram: rk3399: Move common sdram structures in common header
Move common sdram structures like sdram_cap_info, sdram_base_params
into sdram_common header, this would help to reuse the same
from another controllers like px30.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
1372a6ec47 ram: rk3399: s/rk3399_base_params/sdram_base_params
Most of the ddr parameters are common in rk3399_base_params
structure and which would reuse it in another controller like
px30 in future.

So, rename the structure from rk3399_base_params into
sdram_base_params.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
355490dc5c ram: rockchip: rk3399: Add cap_info structure
Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig

into a common cap_info structure for more code readability and extend
if possible based on the new features.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Tom Rini
0de8153564 Merge branch '2019-07-17-master-imports'
- Various FS/disk related fixes with security implications.
- Proper fix for the pci_ep test.
- Assorted bugfixes
- Some MediaTek updates.
- 'env erase' support.
2019-07-18 11:31:37 -04:00
Heinrich Schuchardt
0c1456d571 ARM: correct detection of thumb mode
When a crash occurs in thumb mode the crash dump is incorrect. This is due
to the usage of a non-existing configuration variable CONFIG_ARM_THUMB in
the definition of macro thumb_mode(regs).

Use CONFIG_IS_ENABLED(SYS_THUMB_BUILD) to detect that the code has been
compiled for thumb mode. Remove ARM_THUMB from config_whitelist.txt.

With the patch crash dumps indicate thumb mode correctly.

On a system with thumb mode:

=> exception unaligned
data abort
pc : [<8f7a2b52>]          lr : [<8f7ab1ef>]
reloc pc : [<1780cb52>]    lr : [<178151ef>]
sp : 8ed8c3f8  ip : 8f7a2b4d     fp : 00000002
r10: 8f7f8228  r9 : 8ed95ea8     r8 : 8ed99488
r7 : 8f7ab141  r6 : 00000000     r5 : 8ed8c3f9  r4 : 8f7f6390
r3 : 8ed9948c  r2 : 00000001     r1 : 00000000  r0 : 8f7f6390
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32 (T)
Code: 8f7e 466d f105 0501 (e9d5) 6700

The Flags line has '(T)' and in the Code line the output is in u16 groups.

On a system without thumb mode:

=> exception breakpoint
prefetch abort
pc : [<7ff5a5c8>]          lr : [<7ff675ec>]
reloc pc : [<0000e5c8>]    lr : [<0001b5ec>]
sp : 7ee0ad80  ip : 7ff5a5cc     fp : 7ff674cc
r10: 00000002  r9 : 7ef0bed8     r8 : 7ffd6214
r7 : 7ef0e080  r6 : 00000000     r5 : 7ffd4090  r4 : 00000000
r3 : 7ef0e084  r2 : 00000001     r1 : 00000000  r0 : 7ffd4090
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Code: e1a0500d e2855001 e1c560d0 e3a00001 (e12fff1e)

The Flags line does not show '(T)' and in the Code line the output is in
u32 groups.

Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-18 11:31:24 -04:00
Vignesh R
4fd4c898f0 arm: omap_i2c: Remove unwanted header file inclusion
There is no need for to include this header here, so drop it.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-17 11:12:54 -04:00
Andre Przywara
75a8a641f3 sunxi: H6: Add DDR3 support to DRAM controller driver
At the moment the H6 DRAM driver only supports LPDDR3 DRAM.

Extend the driver to cover DDR3 DRAM as well.

The changes are partly motivated by looking at the ZynqMP register
documentation, partly by looking at register dumps after boot0/libdram
has initialised the controller.

Many thanks to Jernej for contributing some fixes!

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:09:41 +05:30
Andre Przywara
770b85a418 sunxi: H6: move LPDDR3 timing definition into separate file
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM.
Split the timing parameters for this LPDDR3 configuration  into a
separate file, to allow selecting an alternative later at compile time
(as the sunxi-dw driver does).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:09:31 +05:30
Pascal Linder
fd9d70d738 km/spi: remove deprecated SPI flash driver code for KM Kirkwood boards
KM Kirkwood boards now implement the driver model for its SPI flash
interface. Therefore, the old board specific claim and release functions
can be deleted. The preprocessor definition CONFIG_SYS_KW_SPI_MPP is yet
unused as well. All its appearances and dependencies are removed in the
kirkwood_spi driver, header files and finally the configuration whitelist.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-07-11 10:58:03 +02:00
Tom Rini
0b7f1a95df - fix khadas-vim README
- add support for unique generated MAC adresses from SoC serial,
   limited to Amlogic GXL/GXM boards for now
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Merge tag 'u-boot-amlogic-20190704' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- fix khadas-vim README
- add support for unique generated MAC adresses from SoC serial,
  limited to Amlogic GXL/GXM boards for now
2019-07-08 16:02:19 -04:00
Neil Armstrong
dad258fadd ARM: meson: add unique MAC address generation
Add support for generating an unique MAC address using the SoC internal
serial number from the Secure Monitor interface.

The algorithm generates an unicast locally administered 6bytes minus 2bits
address using an crc16 of the serial for the top 16bits with the lower 2 bits
masked to setup the unicast locally administered property and a crc24 for
the lower 24bits.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-04 16:04:59 +02:00
Neil Armstrong
0ef8e4069e ARM: meson: sm: Add secure monitor calls to retrieve SoC serial number
The Secure Monitor interface permits retrieving the SoC Serial Number,
add a function to retrieve it.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-04 16:04:59 +02:00
Yangbo Lu
e37ac717d7 Convert to use fsl_esdhc_imx for i.MX platforms
Converted to use fsl_esdhc_imx for i.MX platforms.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
2019-06-23 14:18:34 +08:00
Alex Marginean
062d8148f8 arm: ls1028a: define the integrated PCI bus (ECAM)
LS1028A includes an integrated PCI bus with 11 PCI functions residing on
bus 0.  ECAM plus the device register space takes up 256MB of address
space.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Yangbo Lu
087bfe67ac armv8: fsl-lsch3: add clock support for the second eSDHC
Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Xiaowei Bao
36f50b7523 armv8: ls1028a: Add other serdes protocal support
Add other serdes protocal support.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Ran Wang
3458a4198c armv8: ls1028a: enable workaround for USB erratum A-008997
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL
registers has been moved to DSCR as compared to other Layerscape SoCs
where it was in SCFG.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Tom Rini
529faf80c3 u-boot-imx-20190612
--------------------
 
 - Board fixes:
 	- imx6logic
 	- wandboard
 	- mx6sabre boots again
 	- imx8qm_mek
 	- pico-* boards
 	- Toradex apalis / colibri
 	- engicam imx6 (environment)
 	- KP MX53
 	- opos6ul
 - Switch to DM:
 	- vining2000
 	- dh MX6
 	- Toradex colibri i.MX7
 	- Novena
 - Security : fix CSF size for HAB
 - Other:
       - imx: fix building for i.mx8 without spl
       - pcie and switch to DM
 
       mx6sabreauto: Enable SPL SDP support
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Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imx

u-boot-imx-20190612
--------------------

- Board fixes:
	- imx6logic
	- wandboard
	- mx6sabre boots again
	- imx8qm_mek
	- pico-* boards
	- Toradex apalis / colibri
	- engicam imx6 (environment)
	- KP MX53
	- opos6ul
- Switch to DM:
	- vining2000
	- dh MX6
	- Toradex colibri i.MX7
	- Novena
- Security : fix CSF size for HAB
- Other:
      - imx: fix building for i.mx8 without spl
      - pcie and switch to DM

      mx6sabreauto: Enable SPL SDP support
2019-06-11 13:41:24 -04:00
Peng Fan
16529ff255 imx: define ARCH_MXC for i.MX8/8M/7ULP
Without this definition, fsl_esdhc will access reserved registers
on i.MX chips, so define ARCH_MXC to fix it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-06-11 10:43:00 +02:00
Peng Fan
75eba18321 imx: drop imx-regs.h
imx-regs.h under arch-imx has no user, drop it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-06-11 10:43:00 +02:00
Jun Nie
79fcbde8eb pico-imx7d: Correct uart clock root
Correct uart clock root ID. Incorrect ID may result the
clock is gated because rate value 0 is returned in
imx_get_uartclk()

The ID can be ignored if CONFIG_SKIP_LOWLEVEL_INIT is not enabled
because init_clk_uart() will enable all uart clocks in that case.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
2019-06-11 10:42:48 +02:00
Ye Li
15bae9a86d mx7ulp: Add common plugin codes for mx7ulp
Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2
header.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-06-11 10:42:48 +02:00
Thierry Reding
34e12e03c7 ARM: tegra: Implement cboot_get_ethaddr()
This function will attempt to look up an Ethernet address in the DTB
that was passed in from cboot. It does so by first trying to locate the
default Ethernet device for the board (identified by the "ethernet"
alias) and if found, reads the "local-mac-address" property. If the
"ethernet" alias does not exist, or if it points to a device tree node
that doesn't exist, or if the device tree node that it points to does
not have a "local-mac-address" property or if the value is invalid, it
will fall back to the legacy mechanism of looking for the MAC address
stored in the "nvidia,ethernet-mac" or "nvidia,ether-mac" properties of
the "/chosen" node.

The MAC address is then written to the default Ethernet device for the
board (again identified by the "ethernet" alias) in U-Boot's control
DTB. This allows the device driver for that device to read the MAC
address from the standard location in device tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-06-05 09:16:34 -07:00
Thierry Reding
a0dbc1314c ARM: tegra: Unify Tegra186 builds
Tegra186 build are currently dealt with in very special ways, which is
because Tegra186 is fundamentally different in many respects. It is no
longer necessary to do many of the low-level programming because early
boot firmware will already have taken care of it.

Unfortunately, separating Tegra186 builds from the rest in this way
makes it difficult to share code with prior generations of Tegra. With
all of the low-level programming code behind Kconfig guards, the build
for Tegra186 can again be unified.

As a side-effect, and partial reason for this change, other Tegra SoC
generations can now make use of the code that deals with taking over a
boot from earlier bootloaders. This used to be nvtboot, but has been
replaced by cboot nowadays. Rename the files and functions related to
this to avoid confusion. The implemented protocols are unchanged.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-06-05 09:16:34 -07:00
Thierry Reding
f9ec2ec850 ARM: tegra: Support TZ-only access to PMC
Some devices may restrict access to the PMC to TrustZone software only.
Non-TZ software can detect this and use SMC calls to the firmware that
runs in the TrustZone to perform accesses to PMC registers.

Note that this also fixes reset_cpu() and the enterrcm command on
Tegra186 where they were previously trying to access the PMC at a wrong
physical address.

Based on work by Kalyani Chidambaram <kalyanic@nvidia.com> and Tom
Warren <twarren@nvidia.com>.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-06-05 09:16:34 -07:00
Thierry Reding
e9c58f2bb8 ARM: tegra: Use common header for PMU declarations
There's no need to replicate the pmu.h header file for every Tegra SoC
generation. Use a single header that is shared across generations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-06-05 09:16:33 -07:00
Christoph Muellner
dee5ad5ae7 rockchip: pinctrl: rk3399: Add support for UART3.
This patch adds the missing GRF bit definitions for UART3 on the RK3399.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30 18:22:35 +08:00
Tom Rini
e2822ccc2c Merge branch 'master' of git://git.denx.de/u-boot-tegra
- Audio support
2019-05-29 07:28:40 -04:00
Bartosz Golaszewski
d7cc0e4d79 mcx: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-28 13:58:06 -04:00
Bartosz Golaszewski
2aa20c43e4 twister: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2019-05-28 13:58:06 -04:00
Bartosz Golaszewski
899dd71e9f mt_ventoux: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2019-05-28 13:58:06 -04:00
Bartosz Golaszewski
8c2644ca69 cm_t3517: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-28 13:58:06 -04:00
Bartosz Golaszewski
7a2b51e36f ea20: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2019-05-28 13:58:06 -04:00
Bartosz Golaszewski
881ae794b9 calimain: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-28 13:58:06 -04:00
Simon Glass
c5a120b3f0 tegra: sound: Add an I2S driver
Add a driver which supports transmitting digital sound to an audio codec.
This uses fixed parameters as a device-tree binding is not currently
defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-05-24 10:14:03 -07:00
Simon Glass
112f2e1443 tegra: sound: Add an audio hub driver
Add a driver for the audio hub. This is modelled as a misc device which
supports writing audio data from I2S.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-05-24 10:13:52 -07:00
Yuantian Tang
d4ad111dc4 armv8: ls1028a: Add NXP LS1028A SoC support
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
 ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Hou Zhiqiang
059d942283 armv8: lx2160a: add MMU table entries for PCIe
The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Hou Zhiqiang
3fbe8f0f44 armv8: fsl-layerscpae: correct the PCIe controllers' region size
The LS2080A has 8GB region for each PCIe controller, while the
other platforms have 32GB.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Tom Rini
79764b5081 Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- H6 WDT reset fix (Clément)
- H6 SPL_TEXT_BASE fixes (Clément, Jonas)
- NPI-M1+ emac enablment (Emmanuel)
2019-05-20 13:53:51 -04:00
Clément Péron
26f8e0d7f2 arm: sunxi: h6: fix reset using r_wdog
Some H6 boards have a watchdog which didn't make the SoC
reboot properly.

Reason is still unknown but several people have test it.
Chen-Yu Tsai :
Pine H64 = H6 V200-AWIN H6448BA 7782 => OK
OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO

Martin Ayotte :
Pine H64 = H8069BA 6892 => OK
OrangePi 3 = HA047BA 69W2 => KO
OrangePi One Plus = H7310BA 6842 => KO
OrangePi Lite2 = H6448BA 6662 => KO

Clément Péron:
Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO

After the series of result, Icenowy try to reach Allwinner about this
issue but they seems not interested to investigate it.

As we don't have the ARIS coproc to do power management and watchdogis
the only solution to reset the board.

So, Change from watchdog to R_watchdog to allow a reboot on all H6
boards.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-20 22:24:47 +05:30
Trevor Woerner
1001502545 CONFIG_SPL_SYS_[DI]CACHE_OFF: add
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-18 08:15:35 -04:00
Tom Rini
f30f268a07 Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchip
Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
2019-05-09 12:36:17 -04:00
Neil Armstrong
92d911b2ee mach-meson: g12a: add DWC2 peripheral mode support
Adds support for Amlogic G12A USB Device mode.

The DWC2 Controller behind the Glue can be connected to an OTG
capable PHY. The Glue setups the PHY mode.

This patch implements Device mode support by adding a board_usb_init/cleanup
setting up the DWC2 controller and switch the OTG capable port to Device
before starting the DWC2 controller in Device mode.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-05-09 10:38:32 +02:00
Kever Yang
6b780e441b rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add
condition to limit it not affect TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
93557bd260 rockchip: add common header boot0.h and gpio.h for soc
boot0.h and gpio.h will be used by system and include by
'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-05-08 17:34:12 +08:00
Dinh Nguyen
2bac27ce94 ARM: pl310: Add macro's for handling tag and data latency mask
Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05 08:48:50 -04:00
Tom Rini
3570ea1f98 Improvements and new features:
- improved SPI driver for better read throughput
 - refactors initialisation of debug UART init
 - restructures header file paths
 - adds pinctrl improvements
 
 Adds Kever as a co-custodian.
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Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchip

Improvements and new features:
- improved SPI driver for better read throughput
- refactors initialisation of debug UART init
- restructures header file paths
- adds pinctrl improvements

Adds Kever as a co-custodian.
2019-05-01 11:52:04 -04:00
Tom Rini
b4ee6daad7 Porting to DM and i.MX8
------------------------
 
 - warp7 to DM
 - kp_imx53 to DM
 - Warnings in DT
 - MX8QM support
 - colibri-imx6ull to DM
 - imx7d-pico to DM
 - ocotp for MX8
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Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx

Porting to DM and i.MX8
------------------------

- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
2019-05-01 07:25:51 -04:00
Kever Yang
15f09a1a83 rockchip: use 'arch-rockchip' as header file path
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
6916dad511 rockchip: arm: use 'arch-rockchip' for common header
rockchip platform header file is in 'arch-rockchip'
instead of arch-$(SOC) for all SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
9f09b9d3cc rockchip: arm: remove no use macro
TIMER7_BASE is no used by source code now, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Marcel Ziswiler
edcd4d1b88 misc: imx8: remove duplicates from scfw api
Remove duplicate function declarations from the SCFW API header file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:16:24 +02:00
Peng Fan
4ba1b34dfe imx8: imx8-pins: add i.MX8QM
Add i.MX8QM entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
7f50af6090 imx8: add cpu support
Add cpu type and Kconfig entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
a87eb0405f imx: sip: add call_imx_sip_ret2
This function will be used by i.MX8 fuse driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 09:03:15 +02:00
Tom Rini
ceb6ddbc73 - Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
 - Add support for the Libretech-AC AML-S805X-AC board
 - Add Amlogic AXG reset compatible
 - Add I2C support for Amlogic AXG
 - Fix AXG PIN and BANK pinctrl definitions
 - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
 - Add initial support for Amlogic G12A SoC and U200 board
 - Enable PHY_REALTEK for selected boards
 - Fix Khadas VIM2 README
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Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogic

- Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
- Add support for the Libretech-AC AML-S805X-AC board
- Add Amlogic AXG reset compatible
- Add I2C support for Amlogic AXG
- Fix AXG PIN and BANK pinctrl definitions
- Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
- Add initial support for Amlogic G12A SoC and U200 board
- Enable PHY_REALTEK for selected boards
- Fix Khadas VIM2 README
2019-04-24 12:26:25 -04:00
Jerome Brunet
17b7efe25b ARM: meson: add G12a support
Add support for the Amlogic G12A SoC, which is a mix between the
new physical memory mapping of AXG and the functionnalities of
the previous Amlogic GXL/GXM SoCs.

To handle the internal ethernet PHY, the Amlogic G12A SoCs now
embeds a dedicated PLL to feed the internal PHY.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Jerome Brunet
912af8423f clk: meson: add g12a support
Add basic support for the Amlogic G12A clock controller based on
the AXG driver.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Chee Hong Ang
f6b0115a96 ARMv8: Allow SiP service extensions on top of PSCI code
Allow PSCI layer to handle any SiP service functions added by
platform vendors. PSCI layer will look for SiP service function
in the SiP function table located in '._secure_svc_tbl_entries'
section if the SMC function identifier is not found in the PSCI
standard functions table. Use DECLARE_SECURE_SVC macro to declare
and add platform specific SiP service function.
This new section '._secure_svc_tbl_entries' is located next to
'._secure.text' section. Refer to arch/arm/cpu/armv8/u-boot.lds.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2019-04-22 18:13:21 -04:00
Philippe Reynes
6478848d16 arm: asm: io.h: define readX_relaxed and writeX_relaxed
This patch port the function readX_relaxed and
writeX_relaxed from kernel 4.18.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 11:55:58 -04:00
Tom Rini
75ce8c938d Move to DM
-----------
 
 - DM support in sata
 - Toradex Board to DM
 - wandboard to DM
 - tbs2910 to DM
 - GE boards to DM
 - VHybrid boards to DM
 - DM_VIDEO for i.MX
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Merge tag 'u-boot-imx-20190415' of git://git.denx.de/u-boot-imx

Move to DM
-----------

- DM support in sata
- Toradex Board to DM
- wandboard to DM
- tbs2910 to DM
- GE boards to DM
- VHybrid boards to DM
- DM_VIDEO for i.MX
2019-04-15 07:31:14 -04:00
Stefan Agner
2588bf1edc arm: vf610: add uart2 clock/pinmux support
Add support for Vybrid's UART2 (Colibri UART_B).

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:09 +02:00
Marcel Ziswiler
872fc0d8ac vf610: ddrmc: add missing include
The DDR memory controller include file for the Vybrid uses
iomux_v3_cfg_t without actually including iomux-vf610.h.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-13 20:30:09 +02:00
Anatolij Gustschin
57f065fee2 video: ipuv3: add DM_VIDEO support
Extend the driver to build with DM_VIDEO enabled. DTS files
must additionally include 'u-boot,dm-pre-reloc' property in
soc and ipu nodes to enable driver binding to ipu device.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-04-13 20:30:09 +02:00
Lukasz Majewski
e5b345f30c pcm052: bk4: sdcard: Add support for SD card booting/recovery
This code allows reusing the default u-boot as in the late board init, the
default envs are restored and proper recovery scripts executed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-13 20:30:08 +02:00
Lukasz Majewski
7db8b854d3 vybrid: clock: Provide enable_i2c_clk() function for Vybrid
Provide function to enable I2C clocks for vf610 - in the generic code.
This function overrides the default weak function implementation (which
only returns 1).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:08 +02:00
Tom Rini
0a5228be86 - mt76xx: add USB support, small fixes
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
 - mscc: small fixes, add network support for JR2 and ServalT SoCs
 - bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
 - MIPS: fix redundant relocation of initrd images
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Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mips

- mt76xx: add USB support, small fixes
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
2019-04-13 08:27:26 -04:00
Tom Rini
dd758c6720 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2019-04-12 15:43:08 -04:00
Philippe Reynes
2629128572 gpio: do not include <asm/arch/gpio.h> on ARCH_BCM63158
As no gpio.h is defined for this architecture, to avoid
a compilation failure, do not include <asm/arch/gpio.h>
for arch bcm63158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Philippe Reynes
d96e7ed802 gpio: do not include <asm/arch/gpio.h> on ARCH_BCM6858
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch bcm6858.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Sjoerd Simons
f50939647c Add support for the MT41K128M16JT125K memory modules
Add configuration for the MT41K128M16JT125K memory modules as used on the
Bosch Guardian device.

Based on a patch by:
    Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com>

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
[checkpatch.pl cleanup by Martyn Welch]
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-04-12 08:05:48 -04:00
Andre Przywara
067e0b9684 sunxi: Allow booting from 128KB SD/eMMC offset
On modern Allwinner SoCs (tested: H2+, A64, H5, H6) the BootROM can
actually load the SPL also from sector 256 (128KB) of an SD card or eMMC
chip. For more details, see [1].
In this case the boot source indicator (written at offset 0x28 of SRAM A1)
has bit 4 set, so it's 0x10 for SD card and 0x12 for eMMC.

Add those new values to the existing boot source check to allow booting
the SPL from those "high" disk offsets as well. For this to work, the
value of CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to be adjusted,
for instance to 0x140 (right after the high SPL). Doing this dynamically
sounds desirable, but looks nasty to implement.

[1] https://groups.google.com/forum/#!topic/linux-sunxi/MaiijyaAFjk

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-10 15:34:32 +05:30
Alison Wang
158097052a armv7: ls102xa: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:01 +05:30
Laurentiu Tudor
7122f79141 armv8: fsl-layerscape: avoid DT fixup warning
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:

WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.

Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:14 +05:30
Laurentiu Tudor
e82d9ee73a armv8: fsl-layerscape: fix SEC QI ICID setup
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:09 +05:30
Rajesh Bhagat
bbf5b25282 armv8: layerscape: move TZASC and TZPC configs to Kconfig
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig
for LS1088A and LS2088A platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Pankaj Bansal
1eba723c72 lx2160aqds : Add support for LX2160AQDS platform
LX2160AQDS is a development board that supports LX2160A
family SoCs. This patch add base support for this board.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[PK: Sqaush patch for "secure boot defconfig" & add maintainer]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Priyanka Jain
fc615be4a6 armv8: lx2160a: Update CONFIG_SYS_FSL_PEBUF_BASE
As per hardware documentation,
CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Abel Vesa
79536013a3 usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE
Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL,
makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE.
Everything that is not part of the usb storage support in SPL is now
build under SPL_USB_HOST_SUPPORT.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Lukasz Majewski
c5b22a5360 ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)
This commit provides extra defines needed for DDR memory controller
calibration (read leveling performing).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-02-15 12:16:50 +01:00
Simon Glass
9e92116bc8 rockchip: Add support for chromebook_bob
Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C
ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports
for both power and external display. It includes a Chrome OS EC
(Cortex-M3) to provide access to the keyboard and battery functions.

Support so far includes only:
- UART
- SDRAM
- MMC, SD card
- Cros EC (but not keyboard)

Not included:
- Keyboard
- Display
- Sound
- USB
- TPM

Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support
for this is not provided in this series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
aa48c94ca8 rockchip: Implement spl_gpio in the GPIO driver
Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
3ec6f11c7d rockchip: Move pull-up/down enum into a common file
At present this enum is only available to rk3288. Move it so that other
rockchip SoCs can access it. It is needed for the SPL GPIO driver for
rk3999 in a later patch.

Also adjust the enum name to lower case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
3dbfe5ae61 rockchip: rk3288: Add i2s pinctrl and clock support
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Neil Armstrong
3bed422094 video: Add Meson Video Processing Unit Driver
This adds video output support for Amlogic GXBB/GXL/GXM chips.
The supported ports are CVBS and HDMI (based on DW_HDMI).

When using HDMI, only DMT modes are supported.

There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB)

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[narmstrong: fixed defines alignment in meson_canvas.c]
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Tom Rini
748ad078ee For 2019.04
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Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imx

For 2019.04
2019-01-30 07:22:12 -05:00
Ye Li
d8bbf362f3 imx: Check the PL310 version for applying errata
Apply errata based on PL310 version instead of compile
time. Also set Prefetch offset to 15, since it improves
memcpy performance by 35%. Don't enable Incr double
Linefill enable since it adversely affects memcpy
performance by about 32MB/s and reads by 90MB/s. Tested
with 4K to 16MB sized src and dst aligned buffer.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
2019-01-28 20:55:46 +01:00
Lukasz Majewski
56ac8104e3 ARM: imx: fix: Provide correct enum values for ONENAND/NOR boot recognition
According to "Table 5-1. Boot Device Select" (page 335,
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017)
the BOOT_CFG1[3] have following values (regarding EIM booting):
0 - NOR flash and 1 - ONENAND

This commit provides correct identification of the boot medium for IMX6Q
boards booting from NOR memory (MCCMON6 is one of them).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-28 20:55:46 +01:00
Shawn Guo
7fa6d33684 poplar: clean up board level mmc initialization code
We have converted mmc to driver model on Poplar.  So let's clean up
board level mmc initialization code.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-25 12:12:57 -05:00
Tom Rini
d01806a8fc Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2019-01-24 15:30:48 -05:00
Michal Simek
274ccb5b11 arm64: zynqmp: Move SoC sources to mach-zynqmp
Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.

Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.

Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Tom Rini
77c07e7ed3 Add TFA boot flow for more boards
Add TFA boot defconfig for ls1088a and ls2088a.
 Add dts fixup for PCIe endpoint and root complex.
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Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for more boards

Add TFA boot defconfig for ls1088a and ls2088a.
Add dts fixup for PCIe endpoint and root complex.
2019-01-18 23:11:51 -05:00
Jagan Teki
99ba430870 reset: Add Allwinner RESET driver
Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
0d47bc7056 clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Stefan Mavrodiev
da1ae5905e sunxi: board: Add i2c initialization for sun50i
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE.
However even the controller is enabled, the mux for the pins
are not set.

This patch follows the existing mux method. Since the pads are
different, separate check is added for each i2c.

Tested with A64-SOM204 board.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-18 22:19:08 +05:30
Laurentiu Tudor
a954f6fe70 armv8: fsl-layerscape: properly configure qdma ICID
The ICIDs for the qdma device are not configured through SCFG but
through some registers found in the actual device register block.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:15 -08:00
Hou Zhiqiang
ec88ff80ff armv8: ls1043a: add SVR definitions for 23x23 package silicon
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:40 -08:00
Weijie Gao
3e066bcaef reset: MedaiTek: add reset controller driver for MediaTek SoCs
This patch adds reset controller driver for MediaTek SoCs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-01-14 17:43:18 -05:00
Shawn Guo
e7ab6dfc65 poplar: add DWC2 OTG gadget support
It enables DWC2 OTG gadget driver support for Poplar board.  As
usb2_phy_init() is being always called from board_init(), we can save
the call from board_usb_init().

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-01-14 17:42:44 -05:00
Tom Rini
e5aa3f4d97 Fixes for 2019.01
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Merge tag 'u-boot-imx-20190110' of git://git.denx.de/u-boot-imx

Fixes for 2019.01
2019-01-10 09:28:16 -05:00
Stefan Agner
52c2c97e7c ARM: vf610: ddrmc: fix initialization completion detection
The CR80 register has multiple interrupt bits, the code is supposed
to check bit 8 but instead uses a logical and. In most cases this
probably did not affect real operations since at that stage typically
none of the other bits are set.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-01-09 16:27:23 +01:00
Stefan Agner
b77e368fa2 ARM: vf610: ddrmc: fix CR138 preprocessor define
According to the data sheet bits 10-8 are PHYDRAM_CK_EN. Fix mask
to allow setting PHYDRAM_CK_EN correctly.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-09 16:27:08 +01:00
Stefan Agner
a95d444055 ARM: vf610: ddrmc: program Dummy DDRBYTE1/2
The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter
5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed
for correct operation of DDR. Assume the default DDR pin configuration
which seems to work well on a Colibri VF50.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-09 16:19:36 +01:00
Ye Li
9d47d1316d arm: Round the dma_alloc_coherent memory size to cache line aligned
When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot.
The root cause is a cache coherence issue. When it happens, the ctrl_req in
gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev)
is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB
controller, any accessing to usb_composite_dev variable will cause the cache line refill, then
when setup transfer is completed, reading the setup data in ctrl_req will gets old value from
cache not from memory.

The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory.
so it still needs cache maintain operations before/after HW accessing. Since the cache flush or
invalidate bases on cache line, so when the allocated memory size is not cache line aligned,
potentially it may meet such issue.

This patch modifies the dma_alloc_coherent API to round the size to cache line aligned.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-09 07:13:31 -05:00
Tom Rini
522e035441 imx for 2019.01
- introduce support for i.MX8M
 - fix size limit for Vhybrid / pico boards
 - several board fixes
 - w1 driver for MX2x / MX5x
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Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x
2019-01-01 10:01:00 -05:00
Peng Fan
416f63194b imx8m: ddr: removed unused macros
Remove unused DDRC register macros.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01 14:12:18 +01:00
Peng Fan
e3963c0943 drivers: ddr: introduce DDR driver for i.MX8M
Introduce DDR driver for i.MX8M. The driver will be used by SPL to
initialze DDR PHY and DDR Controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01 14:12:18 +01:00
Peng Fan
389023ced0 imx: imx8m: add lpddr4 header file
Introduce lpddr4 header file

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01 14:12:18 +01:00
Peng Fan
b3e5cb8d35 imx: imx8m: clock refactor dram pll part
Refactor dram_pll_init to accept args to configure different pll freq.
Introduce dram_enable_bypass and dram_disable_bypass

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01 14:12:18 +01:00
Peng Fan
cd357ad112 imx: rename mx8m,MX8M to imx8m,IMX8M
Rename mx8m,MX8M to imx8m,IMX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
2019-01-01 14:12:18 +01:00
Peng Fan
14d4a3d2aa imx: introduce is_imx8mq helper
Introduce is_imx8mq header macro

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01 14:12:18 +01:00
Peng Fan
5041d1e3b2 imx: cpu: add CHIP_REV_2_1 macro
Introduce CHIP_REV_2_1 macro.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01 14:12:18 +01:00
Jean-Jacques Hiblot
7d98dbcc3d usb: musb-new: Add support for DM_USB
Enable DM for USB peripheral in the musb-new driver.
Also make sure that the driver can be used in the SPL.
This implies that:
* the driver must work with and without the OF_CONTROL option. That
in turn, implies that the platform data can be passed in a struct
ti_musb_platdata or be read from the dtb
* usb.o is linked in the SPL if host support is enabled

Another change is that the driver does not fail to bind (and stop the boot
process) if one of the child driver does not bind. Reporting the error is
enough. This kind of error would appear if the port is configured in the
DTS but the driver is not activated in the config.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-14 17:59:10 +01:00
Tom Rini
d94604d558 Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC
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Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-10 17:19:59 -05:00
Jean-Jacques Hiblot
5f97ae6814 i2c: omap24xx_i2c: Use platdata to probe the device
This allows the driver to be used without OF_CONTROL.
AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in
SPL thus requires that the omap I2C can be passed platdata.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 06:11:18 +01:00
Vignesh R
bca09ce4b0 i2c: omap24xx_i2c: Move away from SoC specific headers for reg offset
Move away from SoC specific headers to handle different register layout.
Instead use driver data to get appropriate register layouts like in the
kernel. While at it, perform some mostly cosmetic alignment/cleanup in
the functions being updated.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 06:09:34 +01:00
Patrice Chotard
b2f84e37e2 gpio: stm32f7: Move STM32_GPIOS_PER_BANK into gpio.h
To allow access to this define by other driver, move
it into gpio.h

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Patrice Chotard
dbf928dd26 gpio: stm32f7: Add gpio bank holes management
In some STM32 SoC packages, GPIO bank has not always 16 gpios.
Several cases can occur, gpio hole can be located at the beginning,
middle or end of the gpio bank or a combination of these 3
configurations.

For that, gpio bindings offer the gpio-ranges DT property which
described the gpio bank mapping.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Álvaro Fernández Rojas
47b1cbaf02 arm: implement {in, out}_{16, 32} and {clr, set, clrset}bits_{16, 32}
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-07 08:13:46 -05:00
Priyanka Jain
4909b89ec7 armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Priyanka Jain
d6fdec211f armv8:fsl-layerscape: Add support for Chassis 3.2
NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.

Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Priyanka Jain
6252faa0da armv8: lsch3: Add support of serdes3 module
Some lsch3 based SoCs like lx2160a contains three
serdes modules.
Add support for third serdes protocol in lsch3

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
York Sun
56db948b85 armv8: fsl-layerscape: Update parsing boot source
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
681d489e62 armv8: layerscape: add SMC calls for DDR size and bank info
Adds SMC calls for getting DDR size and bank info for TFABOOT.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
4c41738462 armv8: fsl-layerscape: identify boot source from PORSR register
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.

Further, it can be used to select the environment location.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix multiple checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:26 -08:00
York Sun
d171c70716 move data structure out of cpu.h
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-04 08:30:23 -08:00
Christoph Muellner
af765a49ba rockchip: rk3399: Initialize CPU B clock.
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz.
This decreases the boot time of Linux 4.19 by about 8%.

The 600 MHz are inspired by the 600 MHz used for LPLL initialization
(came in with commit 9f636a249c).

Tested on RK3399-Q7 on Haikou base board.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:45 +01:00
Otavio Salvador
5d2cb15c77 ARM: rockchip: rv1108: Sync clock with vendor tree
Make adjustments to the rv1108 clock driver in order to align it
with the internal Rockchip version.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Heiko Stuebner
5b5ca4c0d4 rockchip: rk3188: add support for usb-uart functionality
Rockchip socs can route the debug uart pins through the d+ and d- pins
of one specific usbphy per soc. Add a config option and implement the
setting on the rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up to mark grf as maybe unused:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Tom Rini
93e72ac472 Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
 - net: designware: add meson meson compatibles
 - Amlogic Meson cleanup for AXG SoC support
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Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
2018-11-29 15:16:58 -05:00
Ryder Lee
01aa9d1d54 pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Ryder Lee
cbd2fba1ec arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:50 -05:00
Neil Armstrong
d96a782d09 ARM: meson: Add boot device discovery
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol.

When no other boot medium are available (or by forcing the USB mode), the
ROM sets the primary USB port as device mode and waits for a Host to
enumerate.

When enumerated, a custom protocol described at [1] permits writing to
memory and execute some specific FIP init code to run the loaded
Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage.

In this mode, we can load different binaries that can be used by U-boot
like a script image file.

This adds support for a custom USB boot stage only available when the
boot mode is USB and the script file at a pre-defined address is valid.
This support was heavily copied from the Sunxi Allwinner FEL U-Boot support.

The tool pyamlboot described at [2], permits using this boot mode on boards
exposing the first USB port, either as OTG or Host port.

[1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md
[2] https://github.com/superna9999/pyamlboot/blob/master/README.md

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
f6eb68b978 clk: Add clock driver for AXG
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
485bba395e ARM: meson: Add support for AXG family
This patch adds support for the Amlogic AXG SoC, which is very close from
the Amlogic GXL SoCs with :
- Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max
- DDR Interface limited to DDR4 16bit
- The whole physical register address space has been moved to 0xfxxxxxxx
- The pinctrl setup has changed
- The clock tree is different enough to use a different driver

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
33e3378091 ARM: meson: rework soc arch file to prepare for new SoC
We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are different
in this SoC. Rework the meson arch directory to prepare for this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Baruch Siach
5c8fd32b22 Use _AC and UL macros from linux/const.h
Drop the _AC and UL macros from common.h. Linux headers is the original
source of this macro, so keep its definition in the same header.

Update existing users of these macros to include const.h directly.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Chee Hong Ang
a7aab5bcb5 ARMv8: Enable all asynchronous abort exceptions taken to EL3
Allow EL3 to handle all the External Abort and SError interrupt
exception occur in all exception levels.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:33 -05:00
Tom Rini
6f44333018 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-11-14 18:25:34 -05:00
Vasily Khoruzhick
31a4ac4d79 sun50i: A64: add support for R_I2C controller
Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has
two groups of pinmuxes on PL bank, so it's called R_I2C.

Add support for this I2C controller and the pinmux which doesn't conflict
with RSB.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:09:10 +05:30
Vasily Khoruzhick
20940ef2a3 mmc: sunxi: add support for automatic delay calibration
A64 and H6 support automatic delay calibration and Linux driver uses it
instead of hardcoded delays. Add support for it to u-boot driver.

Fixes eMMC instability on Pinebook

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:07:39 +05:30
Grygorii Strashko
79d8127168 driver: net: ti: keystone_net: switch to use common mdio lib
Update TI Keystone 2 driver to re-use common mdio lib.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:01 -06:00
Grygorii Strashko
af0cf2178b drivers: net: keystone_net: drop non dm code
Networking support for all TI K2 boards converted to use DM model and
CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop
unused non DM K2 networking code.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:00 -06:00
Tom Rini
2f07a9a6d1 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-10-29 11:21:00 -04:00
Andre Przywara
5776610e9e sunxi: store DRAM size in SPL header
At the moment we rely on the infamous get_ram_size() function to learn
the actual DRAM size in U-Boot proper. This function has two issues:
1) It only works if the DRAM size is a power of two. We start to see
boards which have 3GB of (usable) DRAM, so this does not fit anymore.
2) As U-Boot has no notion of reserved memory so far, it will happily
ride through the DRAM, possibly stepping on secure-only memory. This
could be a region of DRAM reserved for OP-TEE or some other secure
payload, for instance. It will most likely crash in that case.

As the SPL DRAM init routine has very accurate knowledge of the actual
DRAM size, lets propagate this wisdom to U-Boot proper.
We re-purpose a currently reserved word in our SPL header for that.
The SPL itself stores the detected DRAM size there, and bumps the SPL
header version number in that case. U-Boot proper checks for a valid
SPL header and a high enough version number, then uses the DRAM size
from there. If the SPL header field is not sufficient, we fall back to
the old DRAM scanning routine.

Part of the DRAM might be present and probed by SPL, but not accessible
by the CPU. They're restricted in the main U-Boot binary, when accessing
the DRAM size from SPL header.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Andre Przywara
55d481d201 sunxi: Extend SPL header versioning
On Allwinner SoCs we use some free bytes at the beginning of the SPL image
to store various information. We have a version byte to allow updates,
but changing this always requires all tools to be updated as well.

Introduce the concept of semantic versioning [1] to the SPL header:
The major part of the version number only changes on incompatible
updates, a minor number bump indicates backward compatibility.
This patch just documents the major/minor split, adds some comments
to the header file and uses the versioning information for the existing
users.

[1] https://semver.org

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Tom Rini
cf033e04da Merged imx8 architecture, fix build for imx8 + warnings
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Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx

Merged imx8 architecture, fix build for imx8 + warnings
2018-10-25 10:16:21 -04:00
Cédric Le Goater
e1a8dfde5a watchdog: aspeed: restore default value of reset_mask
This is required for the current Linux kernel to reboot. It should also
probably be fixed in Linux.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-22 09:18:49 -04:00
Peng Fan
d526f340f7 power: Add power domain driver for i.MX8
Add the power domain DM driver for i.MX8, that it depends on the DTB
power domain trees to generate the power domain provider devices. Users
need to add power domain trees with property "compatible = "nxp,imx8-pd";"

When power on a PD device, the driver will power on its ancestor PD
devices in power domain tree.

When power off a PD device, the driver will check its child PD devices
first. Only if all child PD devices are off, then power off the current PD
device. Then the driver checks sibling PD devices. If sibling PD devices
are off, then it will power off parent PD device.

There is no counter maintained in this driver, but a state to hold current
on/off state. So the request and free functions are empty.

The power domain implementation in i.MX8 DTB set the "#power-domain-cells"
to 0, so there is no ID binding with each PD device. We don't use "id"
variable in struct power_domain. At the same time, we have to set of_xlate
to empty to bypass standard of_xlate in uclass driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
8b2a31f133 gpio: mxc_gpio: add support for i.MX8
Add i.MX8 support, there are 8 GPIO banks.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
2d58296f3e imx8: add dummy clock
This driver is mostly used to avoid build errors.
We use uclass clk driver for clk related operations.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
abeebc19db imx8: add iomux configuration api
Add iomux configuration api.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Anatolij Gustschin
2fdb1a1df9 imx8: cpu: add uclass based CPU driver
print_cpuinfo() in board init code requires uclass CPU driver,
add it to be able to display CPU info when CONFIG_DISPLAY_CPUINFO
option is enabled. CPU node in DT will have to include 'clocks'
and 'u-boot,dm-pre-reloc' properties for generic print_cpuinfo()
to work as expected. The driver outputs info for i.MX8QXP Rev A
and Rev B CPUs.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-10-22 12:59:01 +02:00
Peng Fan
1ef20a3d81 imx8: add arch_cpu_init arch_cpu_init_dm
Add arch_cpu_init(_dm) mainly to open the channel between ACore and SCU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
8aa1505b59 imx8: add boot device detection
Add get_boot_device to detect boot device.
Add print_bootinfo to print the boot device info.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
fa64d8429b armv8: add cpu core helper functions
Add helper functions to identify different armv8 variants.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
5710a48afc imx: add i.MX8 cpu type
Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
0468be6e7c imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined
Include i.MX8QXP pin header when CONFIG_IMX8QXP defined,
if no SoC macro defined, report error.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
8c51872248 imx8: add imx-regs header file
Add imx-regs header file to include the register base definition

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
707effeafd imx: boot_mode: Add FLEXSPI boot entry
i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
ad9d40acb4 misc: imx8: add scfw api impementation
Add clk/misc/pad/pm/rm scfw api implementaion for different
drivers to invoke. The low level code is using misc_call
to invoke imx8_scu driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
60b9de4f70 arm: global_data: add scu_dev for i.MX8
Add scu_dev for i.MX8, this will be used as a handle
to communite with SCU from A35.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
bf494d7e9b imx8: add scfw macro definition
Add SCFW macro definition.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Adam Ford
2fe88d4522 Convert CONFIG_FLASH_CFI_DRIVER et al to Kconfig
This converts the following to Kconfig:
   CONFIG_FLASH_CFI_DRIVER
   CONFIG_SYS_FLASH_USE_BUFFER_WRITE
   CONFIG_FLASH_CFI_MTD
   CONFIG_SYS_FLASH_PROTECTION
   CONFIG_SYS_FLASH_CFI

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Re-migrate]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-19 19:19:50 -04:00
Siva Durga Prasad Paladugu
5860bc16b9 arm64: zynqmp: Add new command for TCM initialization
This patch adds new zynqmp command "zynqmp tcminit mode" to
initialize TCM. TCM needs to be initialized before accessing
to avoid ECC errors. This new command helps to perform
the same. It also makes tcm_init() as global and uses it for
doing the TCM initialization.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Marek Vasut
ed85f77190 arm: mx5: Add LDB clock config code
Add code to configure PLL4, from which the LDB clock are directly
derived.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-16 10:34:02 +02:00
Patrick Delaunay
606f3a74e6 arm: remove duplicated prototypes in u-boot.arm.h
Remove the function prototypes duplicated between u-boot.arm.h
and init.h/common.h

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:10 -04:00
Patrick Delaunay
6180ea7e66 arm: remove prototype for get_timer_masked
The interruption support had be removed for ARM architecture and
the function get_timer_masked() is no more used except in some
the timer.c files.

This patch clean each timer.c which implement this function and
remove the associated prototype in u-boot-arm.h

For timer.c, I don't verify if the weak version of get_timer
(in lib/time.c) can be used

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00
Patrick Delaunay
aa33fe8695 arm: remove prototype for udelay_masked
The interruption support had be removed for ARM architecture and
the function udelay_masked() is no more used except in some timer.c
files  and have the same content than udelay() or __udelay().

This patch update each timer.c implementing this function and
remove the associated prototype in u-boot-arm.h.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00