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armv8: ls1028a: add icid setup for platform devices

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Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, edma, qdma, gpu, display and sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Laurentiu Tudor 2019-07-30 17:29:59 +03:00 • committed by Prabhakar Kushwaha
parent 5c6dc6c9a9
commit b249fcba00
8 changed files with 76 additions and 16 deletions
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1
arch/arm/cpu/armv8/fsl-layerscape/Makefile
View file

@ -52,4 +52,5 @@ endif
ifneq ($(CONFIG_ARCH_LS1028A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
obj-y += icid.o ls1028_ids.o
endif

33
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c Normal file
View file

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <common.h>
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <asm/arch-fsl-layerscape/fsl_portals.h>
struct icid_id_table icid_tbl[] = {
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);

2
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
View file

@ -9,7 +9,7 @@
#include <asm/arch-fsl-layerscape/fsl_portals.h>
struct icid_id_table icid_tbl[] = {
SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),

2
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file

@ -341,7 +341,7 @@ void fsl_lsch3_early_init_f(void)
bypass_smmu();
#endif
#ifdef CONFIG_ARCH_LS1088A
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
set_icids();
#endif
}

38
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View file

@ -54,6 +54,8 @@ void fdt_fixup_icid(void *blob);
#define SCFG_IS_LE false
#endif
#define QDMA_IS_LE false
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
@ -71,14 +73,6 @@ void fdt_fixup_icid(void *blob);
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
CONFIG_SYS_FSL_ESDHC_ADDR)
#define SET_QDMA_ICID(compat, streamid) \
SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
QDMA_BASE_ADDR, false), \
SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
QDMA_BASE_ADDR, false)
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
EDMA_BASE_ADDR)
@ -127,6 +121,8 @@ extern int fman_icid_tbl_sz;
#define GUR_IS_LE false
#endif
#define QDMA_IS_LE true
#define SET_GUR_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, streamid, \
offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
@ -140,14 +136,34 @@ extern int fman_icid_tbl_sz;
SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
AHCI_BASE_ADDR##sata_num)
#define SET_SDHC_ICID(streamid) \
SET_GUR_ICID("fsl,esdhc", streamid, sdmm1_amqr,\
CONFIG_SYS_FSL_ESDHC_ADDR)
#define SET_SDHC_ICID(sdhc_num, streamid) \
SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
FSL_ESDHC##sdhc_num##_BASE_ADDR)
#define SET_EDMA_ICID(streamid) \
SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
EDMA_BASE_ADDR)
#define SET_GPU_ICID(compat, streamid) \
SET_GUR_ICID(compat, streamid, misc1_amqr,\
GPU_BASE_ADDR)
#define SET_DISPLAY_ICID(streamid) \
SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
DISPLAY_BASE_ADDR)
#define SEC_ICID_REG_VAL(streamid) (streamid)
#endif /* CONFIG_FSL_LSCH2 */
#define SET_QDMA_ICID(compat, streamid) \
SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
QDMA_BASE_ADDR, QDMA_IS_LE), \
SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
QDMA_BASE_ADDR, QDMA_IS_LE)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
SET_ICID_ENTRY( \
(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \

6
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View file

@ -440,7 +440,8 @@ struct ccsr_gur {
u32 usb2_amqr;
u8 res_528[0x530-0x528]; /* add more registers when needed */
u32 sdmm1_amqr;
u8 res_534[0x550-0x534]; /* add more registers when needed */
u32 sdmm2_amqr;
u8 res_538[0x550 - 0x538]; /* add more registers when needed */
u32 sata1_amqr;
u32 sata2_amqr;
u8 res_558[0x570-0x558]; /* add more registers when needed */
@ -448,7 +449,8 @@ struct ccsr_gur {
u8 res_574[0x590-0x574]; /* add more registers when needed */
u32 spare1_amqr;
u32 spare2_amqr;
u8 res_598[0x620-0x598]; /* add more registers when needed */
u32 spare3_amqr;
u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */
u32 gencr[7]; /* General Control Registers */
u8 res_63c[0x640-0x63c]; /* add more registers when needed */
u32 cgensr1; /* Core General Status Register */

7
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
View file

@ -76,7 +76,7 @@
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
#define FSL_DMA_STREAM_ID 6
#elif defined(CONFIG_ARCH_LS1088A)
#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
#define FSL_DMA_STREAM_ID 5
#endif
@ -104,4 +104,9 @@
#define FSL_SEC_JR3_STREAM_ID 67
#define FSL_SEC_JR4_STREAM_ID 68
#define FSL_SDMMC2_STREAM_ID 69
#define FSL_EDMA_STREAM_ID 70
#define FSL_GPU_STREAM_ID 71
#define FSL_DISPLAY_STREAM_ID 72
#endif

3
board/freescale/ls1028a/ls1028a.c
View file

@ -13,6 +13,7 @@
#include <linux/libfdt.h>
#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <i2c.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_FSL_LS_PPA
@ -143,6 +144,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory_banks(blob, base, size, 2);
fdt_fixup_icid(blob);
return 0;
}
#endif