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ARM: vf610: ddrmc: fix initialization completion detection
The CR80 register has multiple interrupt bits, the code is supposed to check bit 8 but instead uses a logical and. In most cases this probably did not affect real operations since at that stage typically none of the other bits are set. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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2 changed files with 4 additions and 2 deletions
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@ -200,7 +200,8 @@
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#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24)
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#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
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#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
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#define DDRMC_CR82_INT_MASK 0x10000000
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#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8)
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#define DDRMC_CR82_INT_MASK (1 << 28)
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#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
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#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
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#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
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@ -233,6 +233,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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/* all inits done, start the DDR controller */
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writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
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while (!(readl(&ddrmr->cr[80]) && 0x100))
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while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
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udelay(10);
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writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
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}
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