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ARM: vf610: ddrmc: fix initialization completion detection

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The CR80 register has multiple interrupt bits, the code is supposed
to check bit 8 but instead uses a logical and. In most cases this
probably did not affect real operations since at that stage typically
none of the other bits are set.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Stefan Agner 2018-12-04 11:10:20 +01:00 • committed by Stefano Babic
parent b77e368fa2
commit 52c2c97e7c
2 changed files with 4 additions and 2 deletions
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3
arch/arm/include/asm/arch-vf610/imx-regs.h
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@ -200,7 +200,8 @@
#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24)
#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
#define DDRMC_CR82_INT_MASK 0x10000000
#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8)
#define DDRMC_CR82_INT_MASK (1 << 28)
#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)

3
arch/arm/mach-imx/ddrmc-vf610.c
View file

@ -233,6 +233,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
/* all inits done, start the DDR controller */
writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
while (!(readl(&ddrmr->cr[80]) && 0x100))
while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
udelay(10);
writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
}