s6e8ax0 panel has many panel of types. This patch support another panel
on TIZEN lunchbox board(HWREVISION 2). This panel has reversed panel
display type. So, I had added necessary command.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 'master' of git://git.denx.de/u-boot-usb:
USB: S5P: Add ehci support
usb:udc:samsung Add functions for storing private gadget data in UDC driver
usb:gadget:composite: Support for composite at gadget.h
usb:gadget:composite USB composite gadget support
usb:udc:samsung:cleanup Replace DEBUG_* macros with debug_cond() calls
usb:udc: Remove duplicated USB definitions from include/linux/usb/ch9.h file
USB: Document the QH and qTD antics in EHCI-HCD
USB: Drop cache flush bloat in EHCI-HCD
USB: Drop ehci_alloc/ehci_free in ehci-hcd
USB: Align buffers at cacheline
usb: use noinline define
* 'master' of git://git.denx.de/u-boot-arm: (167 commits)
OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT
ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
omap4: do not enable auxiliary cores
omap4: do not enable fs-usb module
omap4: panda: disable uart2 pads during boot
igep00x0: change mpurate from 500 to auto
igep00x0: enable the use of a plain text file
tegra2: trivially enable 13 mhz crystal frequency
tegra: Enable keyboard for Seaboard
tegra: Switch on console mux and use environment for console
tegra: Add tegra keyboard driver
tegra: fdt: Add keyboard definitions for Seaboard
tegra: fdt: Add keyboard controller definition
tegra: Add keyboard support to funcmux
input: Add support for keyboard matrix decoding from an fdt
input: Add generic keyboard input handler
input: Add linux/input.h for key code support
fdt: Add fdtdec functions to read byte array
tegra: Enable LP0 on Seaboard
tegra: fdt: Add EMC data for Tegra2 Seaboard
tegra: i2c: Add function to find DVC bus
fdt: tegra: Add EMC node to device tree
tegra: Add EMC settings for Seaboard
tegra: Turn off power detect in board init
tegra: Set up warmboot code on Nvidia boards
tegra: Setup PMC scratch info from ap20 setup
tegra: Add warmboot implementation
tegra: Set up PMU for Nvidia boards
tegra: Add PMU to manage power supplies
tegra: Add EMC support for optimal memory timings
tegra: Add header file for APB_MISC register
tegra: Add tegra_get_chip_type() to detect SKU
tegra: Add flow, gp_padctl, fuse, sdram headers
tegra: Add crypto library for warmboot code
tegra: Add functions to access low-level Osc/PLL details
tegra: Move ap20.h header into arch location
Add AES crypto library
i2c: Add TPS6586X driver
Add abs() macro to return absolute value
fdt: Add function to return next compatible subnode
fdt: Add function to locate an array in the device tree
i.MX28: Avoid redefining serial_put[cs]()
i.MX28: Check if WP detection is implemented at all
i.MX28: Add battery boot components to SPL
i.MX28: Reorder battery status functions in SPL
i.MX28: Add LRADC init to i.MX28 SPL
i.MX28: Add LRADC register definitions
i.MX28: Shut down the LCD controller before reset
i.MX28: Add LCDIF register definitions
i.MX28: Implement boot pads sampling and reporting
i.MX28: Improve passing of data from SPL to U-Boot
M28EVK: Add SD update command
M28EVK: Implement support for new board V2.0
FEC: Abstract out register setup
MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
i.MX28: Add delay after CPU bypass is cleared
spi: mxs: Allow other chip selects to work
spi: mxs: Introduce spi_cs_is_valid()
mx53loco: Remove unneeded gpio_set_value()
mx53loco: Add CONFIG_REVISION_TAG
mx53loco: Turn on VUSB regulator
mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
pmic: dialog: Avoid name conflicts
imx: Add u-boot.imx as target for ARM9 i.MX SOCs
i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
imx: usb: There is no such register
i.MX25: usb: Set PORTSCx register
imx: nand: Support flash based BBT
i.MX25: This architecture has a GPIO4 too
i.MX25: esdhc: Add mxc_get_clock infrastructure
i.MX6: mx6q_sabrelite: add SATA bindings
i.MX6: add enable_sata_clock()
i.MX6: Add ANATOP regulator init
mx28evk: add NAND support
USB: ehci-mx6: Fix broken IO access
M28: Scan only first 512 MB of DRAM to avoid memory wraparound
Revert "i.MX28: Enable additional DRAM address bits"
M28: Enable FDT support
mx53loco: Add support for 1GHz operation for DA9053-based boards
mx53loco: Allow to print CPU information at a later stage
mx5: Add clock config interface
imx-common: Factor out get_ahb_clk()
i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
mx31pdk: Allow booting a zImage kernel
mx6qarm2: Allow booting a zImage kernel
mx6qsabrelite: Allow booting a zImage kernel
mx28evk: Allow booting a zImage kernel
m28evk: Allow to booting a dt kernel
mx28evk: Allow to booting a dt kernel
mx6qsabrelite: No need to set the direction for GPIO3_23 again
pmic: Add support for the Dialog DA9053 PMIC
MX53: mx53loco: Add SATA support
MX53: Add support to ESG ima3 board
SATA: add driver for MX5 / MX6 SOCs
MX53: add function to set SATA clock to internal
SATA: check for return value from sata functions
MX5: Add definitions for SATA controller
NET: fec_mxc.c: Add a way to disable auto negotiation
Define UART4 and UART5 base addresses
EXYNOS: Change bits per pixel value proper for u-boot.
EXYNOS: support TRATS board display function
LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI
EXYNOS: support EXYNOS MIPI DSI interface driver.
EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
LCD: add data structure for EXYNOS display driver
EXYNOS: add LCD and MIPI DSI clock interface.
EXYNOS: definitions of system resgister and power management registers.
SMDK5250: fix compiler warning
misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998
misc:pmic:max8997 MAX8997 support for PMIC driver
TRATS: modify the trats's configuration
ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement
EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
cm-t35: add I2C multi-bus support
include/configs: Remove CONFIG_SYS_64BIT_STRTOUL
include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF
omap3: Introduce weak misc_init_r
omap730p2: Remove empty misc_init_r
omap5912osk: Remove empty misc_init_r
omap4+: Remove CONFIG_ARCH_CPU_INIT
omap4: Remove CONFIG_SYS_MMC_SET_DEV
OMAP3: pandora: drop console kernel argument
OMAP3: pandora: revise GPIO configuration
...
This field gets read in one place (by "bdinfo"), and we can replace
that with getenv("ipaddr"). After all, the bi_ip_addr field is kept
up-to-date implicitly with the value of the ipaddr env var.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus.
This allows us to talk to the PMU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.
- Split PMU code into separate TPS6586X driver
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a basic header file for this register, to be filled in as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These headers provide access to additional Tegra features.
flow - start/stop CPUs
sdram - parameters for SDRAM
fuse - access to on-chip fuses / security settings
gp_padctl - pad control and general purpose registers
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warmboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to include this from board code, so move the header into
an easily-accessible location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Pass memory size from SPL via structure located in SRAM instead of SCRATCH
registers. This allows passing more data about boot from SPL to U-Boot, like the
boot mode pads configuration.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
After an update to the MX51 reference manual (Rev. 5), the
values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH
are now clearly wrong:
"Bit 13:
High / Low Output Voltage Range. This bit selects the output voltage mode for
SD2_CMD. 0 High output voltage mode
1 Low output voltage mode"
The values are currently negated in code - fixed.
Reported-by: David Jander <david.jander@protonic.nl>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: David Jander <david.jander@protonic.nl>
Acked-by: David Jander <david.jander@protonic.nl>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.
The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.
Suggested-by: Yu Li <yk@magniel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
types.h must be included in imx-regs.h if one wants to include
imx-regs.h in a board configuration file. That for one's part is
necessary, if one wants to use addresses defined in imx-regs.h.
For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and
a proper thing is to define it with IMX_MMC_SDHCx_BASE in board
configuration file. This patch fixes the build in that case.
Signed-off-by: Timo Ketola <timo@exertus.fi>
Acked-by: Stefano Babic <sbabic@denx.de>
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's
implement get_clocks function. This is how it seems to be implemented
elsewhere.
Signed-off-by: Timo Ketola <timo@exertus.fi>
Acked-by: Stefano Babic <sbabic@denx.de>
Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
Print CPU information within board_late_init().
This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
mx5: Add clock config interface
Add clock config interface support, so that we
can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Eric Miao <eric.miao@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
get_ahb_clk() is a common function between mx5 and mx6.
Place it into imx-common directory.
Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The MX53 SATA interface can use an internal clock (USB PHY1)
instead of an external clock. This is an undocumented feature, but used
on most Freescale's evaluation boards, such as MX53-loco.
As stated by Freescale's support:
Fuses (but not pins) may be used to configure SATA clocks.
Particularly the i.MX53 Fuse_Map contains the next information
about configuring SATA clocks :
SATA_ALT_REF_CLK[1:0] (offset 0x180C)
'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
EXYNOS SoC platform has MIPI-DSI controller and MIPI-DSI
based LCD Panel could be used with it. This patch supports MIPI-DSI driver
based Samsung SoC chip.
LCD panel driver based MIPI-DSI should be registered to MIPI-DSI driver at
board file and LCD panel driver specific function registered to mipi_dsim_ddi
structure at lcd panel init function called system init.
In the MIPI-DSI driver, find lcd panel driver by using registered
lcd panel name, and then initialize lcd panel driver.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
This patch support EXYNOS FB and FIMD display drivers.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
To sets up lcd and mipi clock in EXYNOS display driver, added clock interface.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This is definitions of system registers and power mananagement registers for EXYNOS SoC.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
TZPC IP is common across Exynos based SoC'c. Renaming exynos5_tzpc
in arch/arm/include/asm/arch-exynos/tzpc.h to exynos_tzpc will allow generic
usase of tzpc.
Also modify board/samsung/smdk5250/tzpc_init.c to use exynos_tzpc.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Avoid using __attribute__ ((__packed__)) unless it's
absolutely necessary. "packed" will remove alignment
requirements for the respective objects and may cause
alignment issues unless alignment is also enforced
using a pragma.
Here, these packed attributes were causing alignment
faults in Thumb build.
Signed-off-by: Aneesh V <aneesh@ti.com>
This will add ARM specific over-rides for the defines
from linux/linkage.h
Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Mike Frysinger <vapier@gentoo.org>
The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
PD_TIM bit field which specifies the power down timing is defined
to occupy bits 8-11, where as it is actually from 12-15 bits.
So correcting this.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The full internal SRAM of size 128kb is public in the case of OMAP5 soc.
So change the base address accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.
Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
http://lists.denx.de/pipermail/u-boot/2012-March/119151.html
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recommended for
OMAP5430 ES1.0 silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
|---------------| (SET1 default 1.4V)
| --------(programmed voltage)
| <- (This switch happens on mux7,pullup)
vdd_mpu(TPS) -----/ (OPP boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -----------------------/ (OPP boot voltage)
Problem 1) |<----- Tx ------>|
timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.
By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
-------- (programmed voltage)
vdd_mpu(TPS) ------------/ (Opp boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -------------/ (OPP boot voltage)
NOTE: This does not attempt to address OMAP5 - Aneesh please confirm
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.
With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.
NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency. While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.
Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
This change adds an implementation of high-speed UART found on NXP
LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
This change adds initial support for NXP LPC32x0 SoC series.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
In driver mmc, generic s5p_sdhci code is implemented.
s5p_mmc file is dupulicated.
we are good that use the generic sdhci.
This patch supported the sdhci for Samsung-SoC.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Lei Wen<leiwen@marvell.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Earlier, a driver exists in the u-boot source for designware i2c interface. That
driver was specific to spear platforms. This patch implements the i2c controller
as a generic driver which can be used by multiple platforms
The driver files are now renamed to designware_i2c.c and designware_i2c.h and
these are moved into drivers/i2c folder for reusability by other
platforms
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
This fixes the issue where mxs_dma_init() was called either twice or never,
without introducing any new init hooks.
The idea is to allow each and every device using the APBH DMA block to
configure and request only the channels it uses, instead of making it call init
for all the channels as is now.
The common DMA block init part, which only configures the block, is then called
from CPUs arch_cpu_init() call.
NOTE: This patch depends on:
http://patchwork.ozlabs.org/patch/150957/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Add basic i2c driver for Tegra2 with 8- and 16-bit address support.
The driver requires CONFIG_OF_CONTROL to obtain its configuration
from the device tree.
(Simon Glass: sjg@chromium.org modified for upstream)
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
I2C ports have a 16-bit clock divisor. Add code to handle this special
case so that I2C speeds below 150KHz are supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change this name to fit with the current convention in the Tegra
header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.
Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:
aliases {
/* This defines the order of our USB ports */
usb0 = "/usb@0xc5008000";
usb1 = "/usb@0xc5000000";
};
drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC).
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Adds prep subcommand to bootm implementation of ARM. When bootm is called
with the subcommand prep the function stops right after ATAGS creation and
before announce_and_cleanup.
This is used in command "cmd_spl export"
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
This adds Linux booting to the SPL
This depends on CONFIG_MACH_TYPE patch by Igor Grinberg
(http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809)
Related CONFIGs:
CONFIG_SPL_OS_BOOT
Activates/Deactivates the OS booting feature
CONFIG_SPL_OS_BOOT_KEY
defines the IO-pin number u-boot switch - if pressed u-boot is
booted
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
Address where the kernel boot arguments are expected - this is
normaly RAM-begin + 0x100
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
Linux crashes if the GPMC isn't configured for the dm9000.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
Instead of hardcoding the mx6 silicon revision, read it in run-time.
Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.
Tested on a mx6qsabrelite, where it shows:
CPU: Freescale i.MX6Q rev1.0 at 792 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
The GPIO_INT_ACT_LOW_SET was incorrectly handling interrupt lines higher than 7.
This is due to the fact that there are two registers for total of 16 lines.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Adds support for loading U-Boot from UART using YMODEM protocol.
If YMODEM support is enabled in SPL and the romcode indicates
that SPL loaded via UART then SPL will wait for start of a
YMODEM transfer via the console port.
Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This patch fixes erroneous 32-bit access to registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This patch introduces an 8-bit register, mx28_register_8, in order to
prepare for fixing erroneous 32-bit wide access of registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This patch renames mx28_register to mx28_register_32 in order to
prepare for the introduction of an 8-bit register, mx28_register_8.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
The video setup for the Epson display is provided. Addtionally
some extra info is displayed next to the Linux logo.
Make get_cpu_rev() publicly available (added to sys_proto.h).
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
* For cold silicon the DDR timings need to be relaxed in order for
the device to boot with DDR at 266MHz
* Fix proposed by James Doublesin
Signed-off-by: Chase Maupin <Chase.Maupin@ti.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU
Introduce two new macros to control conditional setup
MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
The interface to the mxc_gpio driver uses integer (ordinal) values to
refer to all GPIOs on the i.MX processors. The registers themselves
and much of the i.MX documentation are banked in groups of 32, and these
macros allow the use of the port:index numbering for clarity.
GPIO_NUMBER() converts to ordinal value from port:index
GPIO_PORT() returns the port of an ordinal value
GPIO_INDEX() returns the index or offset of the ordinal.
Discussion on the mailing list at
http://lists.denx.de/pipermail/u-boot/2012-January/116927.html
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Before we can send a command we need both the DATI (command inhibit on
mmc_dat line) bit and CMDI (command inhibit on mmc_cmd line) are clear.
The previous behavior of only checking on DATI was insufficient on some
cards and incorrect behavior in any case. This makes the code check
for both bits being clear and makes the error print more clear as
to what happened. DATI_CMDDIS is removed as it was unused elsewhere
in the code and stood for 'DATI is set, cmds are disabled still'.
Fix originally spotted by Peter Bigot.
Tested-by: Peter A. Bigot <bigotp@acm.org>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Andreas Müller <schnitzeltony@googlemail.com>
This patch moves hawkboard to the new spl infrastructure from the
older nand_spl one.
Removed the hawkboard_nand_config build option -- The spl code now
gets compiled with hawkboard_config, after building the main u-boot
image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard
to reflect the same.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
ACTIM_CTRLA macro errently passes "b" parameter to ACTIM_CTRLA_TRAS()
instead of "c". To make usage more clear, replace all single-letter
macro parameters with more descriptive parameter names.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
add support for printing various clock frequency info found
in SOC such as ARM core frequency, DSP core frequency and DDR
frequency as part of bdinfo command.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
AM3517: Changed default clock rate for AM3517
Changed #define MPU_M_13_ES2 from 0x1F4 to 0x258, this allows
the AM3517 to boot up at 600MHz instead of 500 MHz
Signed-off-by: Schuyler Patton <spatton@ti.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
Adding ehci clock enabling mechanism part of clock framework.
When essential clocks are enabled during init phase usb host
clocks can also be enabled from clock framework.
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Clean up added ehci-omap.c and make it generic for re-use across
omap-soc having same ehci ip block. Also pass the modes to be configured
from board file and configure the ports accordingly. All usb layers
are not cache aligned, till then keep cache off for usb ops as ehci will use
internally dma for all usb ops.
* Add a generic common header ehci-omap.h having common ip block
data and reg shifts.
* Rename and modify ehci-omap3 to ehci.h retain only conflicting
sysc reg shifts remove others and move to common header file.
* pass the board data for beagle/panda accordinly to use
ehci ports.
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support the generic watchdog timer for s5pc1xx and exynos4
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: HeungJun, Kim <riverful.kim@samsung.com>
This patch adds power.h and SAMSUNG_BASE() macro for using Exynos4 power.
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch add watchdog.h for Exynos4
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add TCMPB3 field in pwm structure, earliar this was res1.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch modifies mxcmmc.c to be used
not only by i.MX27 but also by i.MX31 boards.
Both use the same SD controller, but have different
clock set-ups.
The i.MX27 imx_get_XXXclock functions are made static to
generic.c and a public mxc_get_clock() function
is provided. Pins, base address and prototypes for
an i.MX31 specific board_init_mmc() are provided.
Some of the i.MX27 clock getters are unused and marked
as such to avoid warnings (./MAKEALL -s mx27), but
the code was left in for future use.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
The uart txd pad can also provide the rxd function. But it does not stop its
tx role. This could be used for a half duplex serial port.
Change names to reduce confusion.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
The Buffer Logic of VPSS is Not Reset by System Reset Pin, see
http://www.ti.com/lit/er/sprz316b/sprz316b.pdf chapter Advisory 1.2.1
on page 9. Add workaroundcode proposed in the errata.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
The OMAP-L138 has a pre-divider available on PLL0.
Add support to da850_lowlevel.c for configuring PLL0's pre-divider. This is
to achieve certain OPP's -- e.g. the 372MHz OPP used also by Linux.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Christian Riesch <christian.riesch@omicron.at>
CC: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
This adds support for SDMMC ports to the funcmux. Only one
option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit
wide SDIO interface where available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support to funcmux for selecting I2C functions and programming
the pinmux appropriately.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to give a name to each available funcmux config. For now we just
use the pin group names (even through it is verbose) since there seems
to be nothing better.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to support config options other than zero, so move the test to the
end to allow intermediate code to OK such a config.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
* implementation based on ti beagleboard/omap3evm
* timing data and i2c workaround for revision 0 boards taken from x-loader
* run-tested with overo revision 0 and 1 / boot from NAND and SDcard
* run-tested with x-loader
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This patch is added to update incorrect ddr and timer
register offset.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This patch is added to replace CONFIG_AM335X symbol
with CONFIG_AM333XX for AM33XX platforms.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Thomas Weber <weber@corscience.de>
Fix boot issue on ES2.0 Panda by tuning some
IO settings. The CONTROL_EFUSE_2 register has
to be over-ridden in software for 4430 boards.
Commit 23e9f0723e
wrongly did this for CONTROL_EFUSE_1. Reverting
this and doing it for CONTROL_EFUSE_2.
Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Raúl Porcel <armin76@gentoo.org>
Now the values in the defines agree with those in the manuals.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
For the i.mx6q, the burned-in MAC address will be the following odering,
fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5]
fuse: 0x620[15:8] MAC_ADDR[15:8] ---> mac[4]
fuse: 0x620[23:16] MAC_ADDR[23:16] ---> mac[3]
fuse: 0x620[31:24] MAC_ADDR[31:24] ---> mac[2]
fuse: 0x630[7:0] MAC_ADDR[39:32] ---> mac[1]
fuse: 0x630[15:8] MAC_ADDR[47:40] ---> mac[0]
This patch also fix the error caculation for the fuse bank[0] address
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Let dram_init function be a common function, so that other mx28 boards
can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.
This feature is important on mx28 SoC for example that has two FEC ports.
Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
ARM boards should use the generic GPIO API
This means changing gpio to unsigned type
Remove the unused gpio_toggle() function which is not part of the API
Comment that free should not modify pin state
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
fixed merge conflict in da8xx_gpio.c, tegra2_gpio.c, and
extended to the new mxs_gpio.c.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
We add a way of initialising the selected of UARTs prior to relocation.
Boards can use the board_init_uart_f() instead of repeating this code
themselves.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
funcmux permits selection of config options for particular peripherals,
such as the pins that are used for that peripheral, if there are several
options.
Add UART selection to start with.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Most boards will want to enable a UART early. This function provides
that feature in Tegra architecture code so the code does not need to be
copied on every board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra2_mmc_init() is implemented by the Tegra2 MMC driver. Since most of
the Tegra2-based boards will need to call it, this commit exports it in
the new public asm/arch/mmc.h header file to prevent each board from
providing its own prototype.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra2 Seaboard has the unfortunate feature that SPI and the console
UART are multiplexed on the same pins. We need to switch between one
and the other during SPI and console activity.
This new file implements a switch and keeps track of which peripheral
owns the pins. It also flips over the controlling GPIO as needed
Since we are adding a second file to board/nvidia/common, we create
a proper Makefile there and remove the direct board.o include from
board/nvidia/seaboard/Makefile
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
During misc_init_r, make sure to setup the clocks
properly for the USB hub on the pandaboard. With
this in place, the USB hub and the ethernet works
on the pandaboard.
Signed-off-by: Chris Lalancette <clalancette@gmail.com>
Acked-by: Aneesh V <aneesh@ti.com>
Fix trailing white space, indentation by spaces instead of TABs,
excessive blank lines, trailing blank lines.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit enables support for USB Gadgets on the Exynos4210 (C210 Universal)
reference target.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
CC: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>
V2: Fix spacing in crm_regs.h
This commit enables support for USB Gadgets on the GONI
reference target.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Remy Bohmer <linux@bohmer.net>
This moves SPL to common location so it can be reused by multiple boards. Also,
this commit adjusts M28 SoM to avoid breakage due to the move.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.
In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Some SOCs have do not start up with their 'main' CPU. The first U-Boot
code may then be executed with a CPU which does not have a CP15, or not a
useful one.
Here we split the initialization of CP15 into a separate call, which can
be performed later if required.
Once the main CPU is running, you should call cpu_init_cp15() to perform
this init as early as possible.
Existing ARMv7 boards which define CONFIG_SKIP_LOWLEVEL_INIT should not
need to change, this CP15 init is still skipped in that case. The only
impact for these boards is that the cpu_init_cp15() will be available
even if it is never used on these boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Fix:
clocks.c: In function 'setup_post_dividers':
clocks.c:175: warning: comparison is always true due to limited range of
data type
clocks.c:177: warning: comparison is always true due to limited range of
data type
clocks.c:179: warning: comparison is always true due to limited range of
data type
clocks.c:181: warning: comparison is always true due to limited range of
data type
clocks.c:183: warning: comparison is always true due to limited range of
data type
clocks.c:185: warning: comparison is always true due to limited range of
data type
clocks.c:187: warning: comparison is always true due to limited range of
data type
clocks.c:189: warning: comparison is always true due to limited range of
data type
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
The serial driver for iMX SOCs is continuosly changed if a
new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port>
defines were used only to find the base address for the selected UART.
Instead of that, move the base address to the board configuration
file and drop all #ifdef from driver.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Helmut Raiger <helmut.raiger@hale.at>
CC: John Rigby <jcrigby@gmail.com>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
Some functions were internal to the apbh dma driver, so annotate them static.
Some of the functions weren't used at all so drop them. This makes the U-Boot
binary smaller by about 1500 bytes.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Add an SPL_BOARD_INIT hook and for OMAP3 have it turn on i2c. OMAP4
doesn't need i2c enabled in SPL. Enable SPL_BOARD_INIT on devkit8000.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>.
This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.
Signed-off-by: Tom Rini <trini@ti.com>
This introduces 200MHz Micron parts timing information based on x-loader
to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init
logic is also based on what x-loader does in these cases. Note that
while previously u-boot would be flashed in with SW ECC in this case it
now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to
0x80100000.
Cc: Dirk Behme <dirk.behme@gmail.com>
Beagleboard rev C5, xM rev A:
Tested-by: Tom Rini <trini@ti.com>
Beagleboard xM rev C:
Tested-by: Matt Ranostay <mranostay@gmail.com>
Beagleboard rev B7, C2, xM rev B:
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
A number of boards are populated with a PoP chip for both DDR and NAND
memory. Other boards may simply use this as an easy way to identify
board revs. So we provide a function that can be called early to reset
the NAND chip and return the result of NAND_CMD_READID. All of this
code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by: Tom Rini <trini@ti.com>
This changes to making the board be responsible for providing the
memory initialization timings in SPL and converts the devkit8000
to this framework. In SPL we try and initialize both CS0 and CS1.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
This adds the optimal SDRC autorefresh control register values for
100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this
to provide the default 165MHz value.
Signed-off-by: Tom Rini <trini@ti.com>
This adds an MCFG macro to calculate the correct value, similar to
the ACTIMA/ACTIMB macros and adds a comment that all of the potential
values here are documented in the TRM. Then we convert the Micron
value to use this macro.
Signed-off-by: Tom Rini <trini@ti.com>
Expand the "enable the config" comment to explain what the bit shifts
are and define out two of the magic numbers.
Signed-off-by: Tom Rini <trini@ti.com>
move struct davinci_rtc to arch/arm/include/asm/arch-davinci/hardware.h
and add RTC_KICK0R_WE, RTC_KICK1R_WE defines,
so they are global useable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Up to now nearly every davinci board has separate code for the
definition of pinmux configurations. This patch adds pinmux
configurations for the DA850 SoCs to the arch tree which may later
be used for all DA850 based boards.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Heiko Schocher <hs@denx.de>
DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs
also. This patch moves common defines from arch-davinci/emac_defs.h to
drivers/net/davinci_emac.h
DaVinci specific PHY drivers hacked to include the new header. We might
want to switch to phylib in future.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
This patch replaces the HAWKBOARD_KICK{0,1}_UNLOCK defines by
DV_SYSCFG_KICK{0,1}_UNLOCK.
The kick register values are not hawkboard specific but may be used
for all davinci boards. In commit f3c149d6c6
new defines for these values wer introduced.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Change my old email address which is no longer valid.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
- Cleanup a lot of fix values, and use defines instead.
- Also make some values configurable through the board config
file.
- delete the NAND_SPL code for da850, as it is not used actually
- remove the asm code
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.
Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Add the emif configurations required for omap5 soc.Add the
correct ddr part configurations required for omap5 evm board.
EDB8164B3PH from ELPIDA is the part used on the board.
Also changes are done to retain some part of the code
common for OMAP4/5 and keep only the remaining in the Soc
specific directories.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Adding the correct configurations required for
dplls, clocks, for omap5 Soc.
Also changes are done to retain some part of the code common
for OMAP4/5 and move only the remaining to the Soc specific
directories.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Fixing them here so that when the files are reused in
subsequent patches for omap5, avoids new checkpatch
warnings.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Cleanup register definitions by introducing new regs-uart.h, compliant with
rest of U-Boot.
* Remove old register definitions from pxa-regs.h
* Convert serial_pxa to new regs-uart.h
* Cleanup serial_pxa
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Taken from Linux kernel with minor modifications:
commit bf985969e27b507f734435a99df8bf745a3dbb2b
Author: Shawn Guo <shawn.guo@freescale.com>
Date: Mon Dec 20 22:57:43 2010 +0800
ARM: mxs: Add iomux support
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Acked-by: Andy Fleming <afleming@gmail.com>
Rename arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c and
arch/arm/include/asm/arch-davinci/am1808_lowlevel.h to da850_lowlevel.c
and da850_lowlevel.h since they apply not only to the AM1808 SoC
but to all DA850 chips. The function names and #defines are changed
likewise.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch fixes following compile error for da8xx evm
da830evm.c: In function 'board_init':
da830evm.c:222: error: 'DAVINCI_SYSCFG_SUSPSRC_UART2' undeclared (first use in this function)
da830evm.c:222: error: (Each undeclared identifier is reported only once
da830evm.c:222: error: for each function it appears in.)
make[2]: *** [da830evm.o] Error 1
similarly for da850evm.
introduced through commit:
f9fc237f1f
Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Calculations for ACTIM_CTRLA amd ACTIM_CTRLB values
are defined in 'header' style comments.
Moved them along with definitions. Should help maintain
consistency between comments and code if any of these
are tweaked in future.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Define common macros to arrive at the values of registers
SDRC_ACTIM_CTRLA and SDRC_ACTIM_CTRLB for different memory
types.
This doesn't make any real change in the execution but
helps readability.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The patch is a port from the framebuffer driver
of the Linux driver drivers/video/da8xx-fb.c, used
on davinci da8xx and OMAP-L138 boards.
As base for the port, the following commit (last changes
for this driver at the moment in the Linux kernel tree)
was taken:
commit 1db41e032d563eb47deab40dc5595be306b143ba
Author: axel lin <axel.lin@gmail.com>
Date: Tue Feb 22 01:52:42 2011 +0000
video: da8xx-fb: fix section mismatch warning
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The hardware base address for ther LCD configuration
registers is missing, as well as some syscfg registers.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
used for booting (for example) from NAND using spl code.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
By default, on Kirkwood SoC DCache Lnd ICache line
lengths are 32 bytes long
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
This allows to initialize DDR memory in C code.
Currently all mx31 boards use assembler code (lowlevel_init.S)
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
Introduce mx31_set_gpr function for setting the GPR (General Purpose Register) on MX31.
This function can be useful for setting a group of pins into tied to some specific peripherals.
Reuse this function from the linux kernel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This patch adds AM33xx emif/ddr support along with board specific
defines.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds basic support for AM33xx which is based on ARMV7
Cortex A8 CPU.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
remove macro CONFIG_EMAC_MDIO_PHY_NUM and depending macro EMAC_MDIO_PHY_NUM
as they are no longer needed with the support for more than 1 PHYs in davinci
emac driver.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
We add an weak version of omap_rev_string in omap-common/spl.c
and while at it drop the omap3 version. Move the prototype over
to <asm/omap_common.h> with the other SPL functions.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Adding the register definitions for omap3 DMA controller to cpu.h
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Adding the base register address of OMAP3 DMA controller.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
MDSTAT.STATE occupies bits 0..5 according to all available documentation, so fix
the mask which previously was leaving out the intermediate state indicator bit.
While at it, introduce two #define's for that mask -- unfortunately, we can't
use a single #define as the assembly code can't include <asm/arch/hardware.h>
due to C-specfic constructs in it.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
OMAP4460 has a different set of values for the ID code, so moving the
old ones to be related just with 4430.
Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to
the definition in the platform definition files.
Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.
Signed-off-by: Lei Wen <leiwen@marvell.com>
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the
definition in the platform definition files.
Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.
Signed-off-by: Lei Wen <leiwen@marvell.com>
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the
definition in the platform definition files.
Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.
Updated cpu.h to remove build errors for gplugd board (by prafulla)
Signed-off-by: Lei Wen <leiwen@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
For files like the drivers/serial/serial.c, it must include the platform
file, as the CONFIG_SYS_NS16550_COM1 must reference to the definition in
the platform definition files.
Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Fix checkpatch warning and errors in several i.MX related files.
While at it also address a checkpatch warning at arch/arm/cpu/armv7/mx5/soc.c
regarding the usage of extern in a C file.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
setup_weimcs() and some macros are added to support the setup
for i.MX31 WEIM chip selects. As a compromise between verbosity
and readability an ASCII-art'ish bit comment is used instead of
bitfields.
All i.MX31 boards have been patched to use this approach using a
helper program to verify the changes.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
This commit updates the mach-types based on the latest in Linus's head
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
This adds support for changing pinmux functions of pin groups. This is done
by defining a PMUX_FUNC_... enum which can be used to select the function for
each group using pinmux_set_func(). It is also possible to enable
pullup/pulldown, and the existing tristate functionality is retained.
Also provided is a means of configuring a list of pingroups by providing a
configuration table to pinmux_config_table().
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
The pin groupings are better named PINGRP, since on Tegra2 they refer to
multiple pins.
Sorry about this, but better to get it right now when there is only a small
amount of code affected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This adds most of the clock functions required by board and driver code:
-query and adjust peripheral clocks
-query and adjust PLLs
-reset and enable control
These functions are plumbed in as required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the
code now deals with both PLL clocks and source clocks.
This also tidied up the assert() to match the one sent upstream, and fixes
an error in the PWM id.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This adds a device tree pointer to the global data. It can be set by
board code. A later commit will add support for making a device
tree binary blob available to U-Boot for run-time configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
This additionally updates mx31/generic.c by
- replacing __REG() macro accesses with readl() and writel()
- providing macros for PDR0 and PLL bit accesses
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Now that none of the core checks CONFIG_NET_MULTI, there's not much point
in boards defining it. So scrub all references to it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This pushes the ugly duplicated arch ifdef lists we maintain in various
image related files out to the arch headers themselves.
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current post_log_word in global data is currently split into 2x
16 bits: half for the test start, half for the test success.
Since we alredy have more than 16 POST tests defined and more could
be defined, this may result in an overflow and the post_output_backlog
would not work for the tests defined further of these 16 positions.
An additional field is added to global data so that we can now support up
to 32 (depending of architecture) tests. The post_log_word is only used
to record the start of the test and the new field post_log_res for the
test success (or failure). The post_output_backlog is for this change
also adapted.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
For post to run on ARM, 3 things are needed:
- post_log_word to be defined in gd
- a post.h include in arch/arm/lib/board.c
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Allow redirection of console output prior to console initialisation to a
temporary buffer.
To enable this functionality, the board (or arch) must define:
- CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer
- CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer
- CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes)
The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes
Any earlier characters are silently dropped.
The PLL decoding algorithm didn't take into account many configuration bits.
Adjust it according to Linux kernel. Also, add PLL4 for MX53.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Hui <jason.hui@linaro.org>
Tested-by: Jason Liu <Jason.hui@linaro.org>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Turn on the watchdog WDZST bit so that watchdog timer does not count during low power modes.
Prior to applying this patch mx31pdk board got watchdog resets because when it booted in the Linux prompt
and there was no activity, the system entered into idle mode while watchdog timer was still active.
Fix this by disabling watchdog timer during idle mode.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Config VMMC voltage to 3V for MMC/SD card slot
and PBIAS settings needed for OMAP4
Fixes MMC/SD detection on boot from eMMC.
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Support for the new spl structure. Using the interface defined by Aneesh V for
OMAP4
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
OMAP3 relied on the memory config done by X-loader or Configuration Header. This
has to be reworked for the implementation of a SPL. This patch configures RAM
bank 0 if CONFIG_SPL_BUILD is set. Settings for Micron-RAM used by devkit8000
are added to mem.h
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The existing timing does not quite meet the minimum requirements
in the LAN9221 datasheet. The timing in this patch solves problems
noticed on some parts. The patch also combines the CS configuration
for the overo and igep0020 boards per request.
Signed-off-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
This patch adds support for Fast Ethernet Controller driver for
Armada100 series.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Tuning some IO settings for better performance and power.
And consolidate all such IO settings at one place.
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
SDRAM init was not working on ES1.0 due to a programming
error. A pointer that was passed by value to a function
was set in function emif_get_device_details(), but the effect
wouldn't be seen in the calling function. The issue came
out while testing for ES1.0 because ES1.0 doesn't have any
SDRAM chips connected to CS1
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Convert all OMAP specific functions to use the common API
definitions in include/asm/gpio.h. In the process, made
few additional changes:
- Use -EINVAL consistently. -1 was used in many places.
- Removed one-liner static functions that were used only
once. Replaced the content as necessary.
- Combines implementation of functions omap_get_gpio_dataout()
and omap_get_gpio_datain(). To do so, new static function
_get_gpio_direction() was added.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
OMAP3: Add 37xx ESx revision numbers.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Signed-off-by: Howard D. Gray <howard.gray@matrix-vision.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Read directly from OMAP_GPIO_DATAOUT to get the output state of the GPIO pin
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
commit 0edf8b5b2f breaks
building on a different directory with the O= parameter.
The patch wil fix this issue, generating always asm-offsets.h before
the other targets.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Wolfgang Denk <wd@denx.de>
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
add support for DSP wake-up by default on DA850/OMAP-L138
during board initialization. Enable hwconfig environment and added
extra env setting through CONFIG_EXTRA_ENV_SETTINGS.
To prevent DSP from being woken up,set the environment variable as,
set hwconfig "dsp:wake=no"
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Modify clk_get() function in cpu file to work for
multiple PLL controllers.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
AM/DM37x is another OMAP3 variant, where the GFX clock has been
boosted to 192MHz/200MHz. So fix the GFX_DIV value for this change.
HW Errata: Due to dependency of TV out clock of 54MHz, it is not
possible to configure GFX to 192MHz. So as per HW errats, the
recommended GFX clock is 200MHz (=CORE_CLK/2).
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for software I2C for GONI and Universal C210 reference targets.
It adds support for access to GPIOs by number, not as it is present,
by bank and offset.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
These functions provide access to the high resolution microsecond timer
and tidy up a global variable in the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is a port of the official PLL errata workaround from Freescale to
mainline u-boot.
The PLL's in the i.MX51 processor can go out of lock due to a metastable
condition in an analog flip-flop when used at high frequencies.
This workaround implements an undocumented feature in the PLL (dither
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.
Signed-off-by: David Jander <david@protonic.nl>
This change is driven by need of general gpio_* functions,
which as their parameter are accepting the GPIO pin number, NOT
block and pin.
This makes the code alike to omap, and allows for using more
generic frameworks (e.g. software I2C).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
