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https://github.com/AsahiLinux/u-boot
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Tegra2: Add additional pin multiplexing features
This adds an enum for each pin and some functions for changing the pin muxing setup. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Albert ARIBAUD
parent
b4ba2be8dc
commit
858bd095e1
4 changed files with 210 additions and 35 deletions
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@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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SOBJS := lowlevel_init.o
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COBJS := ap20.o board.o clock.o sys_info.o timer.o
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COBJS := ap20.o board.o clock.o pinmux.o sys_info.o timer.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
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52
arch/arm/cpu/armv7/tegra2/pinmux.c
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52
arch/arm/cpu/armv7/tegra2/pinmux.c
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@ -0,0 +1,52 @@
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* Tegra2 pin multiplexing functions */
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#include <asm/io.h>
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#include <asm/arch/tegra2.h>
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#include <asm/arch/pinmux.h>
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#include <common.h>
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void pinmux_set_tristate(enum pmux_pin pin, int enable)
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
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u32 reg;
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reg = readl(tri);
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if (enable)
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reg |= TRISTATE_MASK(pin);
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else
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reg &= ~TRISTATE_MASK(pin);
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writel(reg, tri);
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}
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void pinmux_tristate_enable(enum pmux_pin pin)
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{
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pinmux_set_tristate(pin, 1);
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}
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void pinmux_tristate_disable(enum pmux_pin pin)
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{
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pinmux_set_tristate(pin, 0);
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}
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@ -24,6 +24,142 @@
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#ifndef _PINMUX_H_
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#define _PINMUX_H_
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/* Pins which we can set to tristate or normal */
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enum pmux_pin {
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/* APB_MISC_PP_TRISTATE_REG_A_0 */
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PIN_ATA,
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PIN_ATB,
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PIN_ATC,
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PIN_ATD,
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PIN_CDEV1,
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PIN_CDEV2,
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PIN_CSUS,
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PIN_DAP1,
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PIN_DAP2,
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PIN_DAP3,
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PIN_DAP4,
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PIN_DTA,
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PIN_DTB,
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PIN_DTC,
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PIN_DTD,
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PIN_DTE,
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PIN_GPU,
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PIN_GPV,
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PIN_I2CP,
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PIN_IRTX,
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PIN_IRRX,
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PIN_KBCB,
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PIN_KBCA,
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PIN_PMC,
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PIN_PTA,
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PIN_RM,
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PIN_KBCE,
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PIN_KBCF,
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PIN_GMA,
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PIN_GMC,
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PIN_SDMMC1,
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PIN_OWC,
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/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
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PIN_GME,
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PIN_SDC,
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PIN_SDD,
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PIN_RESERVED0,
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PIN_SLXA,
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PIN_SLXC,
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PIN_SLXD,
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PIN_SLXK,
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PIN_SPDI,
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PIN_SPDO,
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PIN_SPIA,
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PIN_SPIB,
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PIN_SPIC,
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PIN_SPID,
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PIN_SPIE,
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PIN_SPIF,
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PIN_SPIG,
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PIN_SPIH,
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PIN_UAA,
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PIN_UAB,
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PIN_UAC,
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PIN_UAD,
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PIN_UCA,
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PIN_UCB,
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PIN_RESERVED1,
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PIN_ATE,
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PIN_KBCC,
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PIN_RESERVED2,
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PIN_RESERVED3,
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PIN_GMB,
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PIN_GMD,
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PIN_DDC,
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/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
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PIN_LD0,
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PIN_LD1,
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PIN_LD2,
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PIN_LD3,
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PIN_LD4,
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PIN_LD5,
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PIN_LD6,
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PIN_LD7,
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PIN_LD8,
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PIN_LD9,
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PIN_LD10,
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PIN_LD11,
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PIN_LD12,
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PIN_LD13,
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PIN_LD14,
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PIN_LD15,
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PIN_LD16,
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PIN_LD17,
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PIN_LHP0,
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PIN_LHP1,
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PIN_LHP2,
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PIN_LVP0,
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PIN_LVP1,
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PIN_HDINT,
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PIN_LM0,
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PIN_LM1,
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PIN_LVS,
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PIN_LSC0,
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PIN_LSC1,
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PIN_LSCK,
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PIN_LDC,
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PIN_LCSN,
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/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
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PIN_LSPI,
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PIN_LSDA,
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PIN_LSDI,
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PIN_LPW0,
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PIN_LPW1,
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PIN_LPW2,
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PIN_LDI,
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PIN_LHS,
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PIN_LPP,
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PIN_RESERVED4,
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PIN_KBCD,
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PIN_GPU7,
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PIN_DTF,
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PIN_UDA,
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PIN_CRTP,
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PIN_SDB,
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};
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#define TEGRA_TRISTATE_REGS 4
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/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
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struct pmux_tri_ctlr {
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uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
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@ -31,10 +167,7 @@ struct pmux_tri_ctlr {
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uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
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uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
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uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
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uint pmt_tri_a; /* _TRI_STATE_REG_A_0, offset 14 */
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uint pmt_tri_b; /* _TRI_STATE_REG_B_0, offset 18 */
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uint pmt_tri_c; /* _TRI_STATE_REG_C_0, offset 1C */
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uint pmt_tri_d; /* _TRI_STATE_REG_D_0, offset 20 */
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uint pmt_tri[TEGRA_TRISTATE_REGS]; /* _TRI_STATE_REG_A/B/C/D_0 14-20 */
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uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
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uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
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@ -48,14 +181,16 @@ struct pmux_tri_ctlr {
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uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */
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};
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#define Z_GMC (1 << 29)
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#define Z_IRRX (1 << 20)
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#define Z_IRTX (1 << 19)
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#define Z_GMA (1 << 28)
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#define Z_GME (1 << 0)
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#define Z_ATB (1 << 1)
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#define Z_SDB (1 << 15)
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#define Z_SDC (1 << 1)
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#define Z_SDD (1 << 2)
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/* Converts a pin number to a tristate register: 0=A, 1=B, 2=C, 3=D */
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#define TRISTATE_REG(id) ((id) >> 5)
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/* Mask value for a tristate (within TRISTATE_REG(id)) */
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#define TRISTATE_MASK(id) (1 << ((id) & 0x1f))
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/* Set a pin to tristate */
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void pinmux_tristate_enable(enum pmux_pin pin);
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/* Set a pin to normal (non tristate) */
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void pinmux_tristate_disable(enum pmux_pin pin);
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#endif /* PINMUX_H */
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@ -143,19 +143,15 @@ static void pin_mux_uart(void)
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reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
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writel(reg, &pmt->pmt_ctl_c);
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reg = readl(&pmt->pmt_tri_a);
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reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */
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reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */
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writel(reg, &pmt->pmt_tri_a);
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pinmux_tristate_disable(PIN_IRRX);
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pinmux_tristate_disable(PIN_IRTX);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
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#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
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reg = readl(&pmt->pmt_ctl_b);
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reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
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writel(reg, &pmt->pmt_ctl_b);
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reg = readl(&pmt->pmt_tri_a);
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reg &= ~Z_GMC; /* Z_GMC = normal (0) */
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writel(reg, &pmt->pmt_tri_a);
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pinmux_tristate_disable(PIN_GMC);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
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}
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@ -222,13 +218,9 @@ static void pin_mux_mmc(void)
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reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
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writel(reg, &pmt->pmt_ctl_d);
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reg = readl(&pmt->pmt_tri_a);
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reg &= ~Z_ATB; /* Z_ATB = normal (0) */
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reg &= ~Z_GMA; /* Z_GMA = normal (0) */
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writel(reg, &pmt->pmt_tri_a);
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reg = readl(&pmt->pmt_tri_b);
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reg &= ~Z_GME; /* Z_GME = normal (0) */
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writel(reg, &pmt->pmt_tri_b);
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pinmux_tristate_disable(PIN_ATB);
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pinmux_tristate_disable(PIN_GMA);
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pinmux_tristate_disable(PIN_GME);
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/* SDMMC3 */
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/* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
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@ -239,13 +231,9 @@ static void pin_mux_mmc(void)
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reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
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writel(reg, &pmt->pmt_ctl_d);
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reg = readl(&pmt->pmt_tri_b);
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reg &= ~Z_SDC; /* Z_SDC = normal (0) */
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reg &= ~Z_SDD; /* Z_SDD = normal (0) */
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writel(reg, &pmt->pmt_tri_b);
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reg = readl(&pmt->pmt_tri_d);
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reg &= ~Z_SDB; /* Z_SDB = normal (0) */
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writel(reg, &pmt->pmt_tri_d);
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pinmux_tristate_disable(PIN_SDC);
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pinmux_tristate_disable(PIN_SDD);
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pinmux_tristate_disable(PIN_SDB);
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}
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/*
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