Commit graph

3833 commits

Author SHA1 Message Date
Joonyoung Shim
483e49bfd7 EXYNOS5: Add function to enable exynos5420 usbdev phy ctrl
Exynos5420 has different registers with other exynos5 SoCs to control
usb device phy, so need separated function to enable exynos5420 usb
device phy.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:19:55 +09:00
Joonyoung Shim
de3b251870 Odroid-XU3: Add eMMC-reset node on DT
This needs for special handling of nRESET_OUT line(GPD1-0 gpio) for eMMC
memory to perform complete reboot on Odroid XU3 board.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:17:10 +09:00
Joonyoung Shim
44237f7a89 Odroid: Add eMMC-reset node on DT
This needs for special handling of nRESET_OUT line(GPK1-2 gpio) for eMMC
memory to perform complete reboot on Odroid X2/U3 boards.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:17:10 +09:00
Jaehoon Chung
a276172cf3 arm: exynos: fix the div value for set_mmc_clk
The most exynos used the  "Ratio + 1" as div value.
And value at register is "Ratio".
So if want to set exact value, it needs to subtract one.

Value at register ("Ratio") = div - 1

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:15:14 +09:00
Nobuhiro Iwamatsu
3eda55a32d arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control Register
r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we
need to enable SMP bit of Auxiliary Control Register.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2015-02-13 13:14:56 +09:00
Vladimir Barinov
3b7f0e109c arm: rmobile: Add SILK board support
SILK is an entry level development board based on R-Car E2 SoC (R8A7794)

This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, MMC, USB Host

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2015-02-13 13:14:56 +09:00
Simon Glass
b724bd7d63 dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig
Move this option to Kconfig and update all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 15:17:28 -07:00
Simon Glass
757fe635df dm: at91: Drop use of ATMEL_PIO_PORTS in the header file
With driver model the number of PIO ports is defined by platform data, so
remove it from the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-12 15:17:27 -07:00
Simon Glass
001646c478 dm: omap3: Move driver model CONFIGs to Kconfig
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 10:35:35 -07:00
Simon Glass
d7a4b2e42e dm: tegra: Move driver model CONFIGs to Kconfig
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 10:35:34 -07:00
Simon Glass
aab7e80d5f dm: exynos: Move driver model CONFIGs to Kconfig
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 10:35:34 -07:00
Simon Glass
34e609ca82 dm: Move Raspberry Pi driver model CONFIGs to Kconfig
Remove driver model CONFIGs from the board config header and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 10:35:34 -07:00
Tom Rini
c956662cc3 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-02-10 10:42:22 -05:00
Tom Rini
307367eaff Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-02-10 10:40:43 -05:00
Graeme Russ
2d6286ab79 arm: mxs: Add 'Wait for JTAG user' if booted in JTAG mode
When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)

Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a pseudo break-point when booting in JTAG mode

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
2015-02-10 12:48:50 +01:00
Graeme Russ
7a08603707 arm: mxs: Enable booting of mx28 without battery
Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery.

This patch changes the behaviour of the dropout control of the DC-DC
converter (refer to section 11.12.9 of the mx28 Application Processor
Reference Manual - Document Number: MCIMX28RM, Rev 2, 08/2013) to the
following:
 - Always use 4P2 Linear Regulator if CONFIG_SYS_MXS_VDD5V_ONLY is defined
 - Switch between 4P2 Linear Regulator and Battery, using whichever has
   the highest voltage if CONFIG_SYS_MXS_VDD5V_ONLY isnot set (this is
   the same as the pre-patch behaviour)

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Signed-off-by: Damien Gotfroi <dgotfroi@greenwatch.be>
2015-02-10 12:48:50 +01:00
Graeme Russ
950eaf6230 arm: mxs: Add debug outputs and comments to mxs SPL source files
It is difficult to track down fail to boot issues in the mxs SPL.
Implement the following to make it easier:
 - Add debug outputs to allow tracing of SPL progress in order to track
where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must
be defined to enable debug output in SPL
 - Add TODO comments where it is not clear if the code is doing what it
is meant to be doing, even tough the board boots properly (these comments
refer to existing code, not to any code added by this patch)

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
2015-02-10 12:48:49 +01:00
Ye.Li
e8cdeefc22 imx: mx6: Fixed AIPS3 base address issue
Should use AIPS3 configuration address 0x0227C000 to set AIPS3,
not the AIPS3 base address.
Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with
AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem.

Signed-off-by: Ye.Li <B37916@freescale.com>
2015-02-10 12:48:49 +01:00
Peng Fan
1730af1bbd imx:mx6 update fuse_bank0_regs
Update fuse_bank0_regs structure according reference mannual.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-02-10 12:48:48 +01:00
Tom Rini
a4fb5df214 Merge branch 'microblaze' of git://git.denx.de/u-boot-microblaze 2015-02-09 11:44:46 -05:00
Michal Simek
0267ba5d86 common: Move dram_init() declaration to common location
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-02-09 15:08:48 +01:00
Heiko Schocher
f4e1886df5 arm, at91: add reset controller status register
add reset controller status register

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:43:22 +01:00
Heiko Schocher
49b461f34a arm, at91, wdt: do not disable WDT in SPL
if CONFIG_AT91SAM9_WATCHDOG is set, do not disable WDT in
SPL

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-02-07 23:43:07 +01:00
Bo Shen
c6941e1203 ARM: atmel: cleanup: remove at91cap9 related code
As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07 23:42:56 +01:00
Bo Shen
0b2a982420 ARM: atmel: sama5d4_xplained: enable spl support
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:55 +01:00
Bo Shen
5a4c9c2287 ARM: atmel: sama5d4ek: enable SPL support
The sama5d4ek support boot up from NAND flash, SD/MMC card and
also the SPI flash.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:53 +01:00
Bo Shen
01c073c013 ARM: atmel: sama5d4: build related file when enable SPL
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:52 +01:00
Bo Shen
b54dd1b3ad ARM: atmel: sama5d4: can access DDR in interleave mode
The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:51 +01:00
Bo Shen
569bbd3ceb ARM: atmel: sama5d4: add interrupt redirect function
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07 23:42:50 +01:00
Bo Shen
09f5c9745b ARM: atmel: sama5d4: add bus matrix init function
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:49 +01:00
Bo Shen
5c756bbc9d ARM: atmel: sama5d4: add matrix1 base addr definition
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:48 +01:00
Bo Shen
0246b7c3b7 ARM: atmel: spl: can not disable osc for sama5d4
The SAMA5D4 SoC on chip rc oscillator can not be disabled.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:47 +01:00
Bo Shen
4514b5f46a ARM: atmel: spl: add saic to aic redirect function
Some SoC need to redirect the saic to aic to make the interrupt to
work, here add a weak function to be replaced by real function.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:46 +01:00
Bo Shen
433be902f3 ARM: atmel: spl: add weak bus matrix init function
Some SoC need to configure the bus matrix, add an weak function
to be replace by real function.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:45 +01:00
Bo Shen
abb44081a5 ARM: atmel: sama5: add sfr register header file
The SFR (special function registers) can be shared bwteen
sama5d3 and sama5d4 soc.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adoptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07 23:42:45 +01:00
Bo Shen
406202dffd ARM: atmel: sama5: add bus matrix header file
This matrix header file can be shared between sama5d3 and sama5d4 soc.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adaptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07 23:42:43 +01:00
Bo Shen
05084443f0 ARM: atmel: clock: make it possible to configure HMX32
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:40 +01:00
Tom Rini
5c123f5fbf Merge git://git.denx.de/u-boot-marvell 2015-02-06 12:02:59 -05:00
Stefan Roese
2e19cc316f arm: mvebu: Add Serdes PHY config code
This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06 17:24:59 +01:00
Stefan Roese
b0f80b913f arm: armada-xp: Add SPL support used to include the DDR training code
This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06 17:24:56 +01:00
Stefan Roese
2554167cc1 arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot
This patch adds SPL support to the db-mv784mp-gp eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06 17:24:46 +01:00
Stefan Roese
e7778ec153 arm: maxbcm: Enable SPL to include DDR training code into U-Boot
This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06 17:24:43 +01:00
Stefan Roese
1e0b5984f4 arm: armada-xp: Change built target to include the SPL binary as bin_hdr
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06 17:24:36 +01:00
Masahiro Yamada
4e79908044 ARM: UniPhier: leave the last element of boot_device_table empty
Checking if the pointer is NULL would be easier to know the tail
of the boot_device_table[] array.
For clarification, add the /* sentinel */ comment.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:03 +09:00
Masahiro Yamada
4431684910 ARM: UniPhier: refactor pinmon command
The return value of get_boot_mode_sel() is used as the index of
the boot_device_table[] array.  Its type should be "int" rather
than "u32".

Use only the iterator "i" for the loop in do_pinmon().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:03 +09:00
Masahiro Yamada
ee470645d1 ARM: UniPhier: enable I2C input pins for PH1-sLD8
To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0)
and bit 11 (SCL1/SDA1) of IECTRL register must be set.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:03 +09:00
Masahiro Yamada
6c45ef4b94 ARM: UniPhier: do not compile unnecessary objects
It is true that unused functions are removed from the ELF image
by the compiler's garbage collection but relying on it too much
does not look nice.
Currently, the build is taking more than it should.

Refactor the makefiles to compile only files that are really needed.
CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the
optimization.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:03 +09:00
Masahiro Yamada
dc4057eb81 ARM: UniPhier: remove unused checkboard() functions
Since commit 0365ffcc0b (generic-board: show model name in
board_init_f() too), checkboard() is invoked only when
show_board_info() fails to get the model name from Device Tree.
It never happens because UniPhier SoCs now only work with
CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees
have the "model" property.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:03 +09:00
Masahiro Yamada
08fda258ee ARM: UniPhier: revive support card info
Since commit 0365ffcc0b (generic-board: show model name in
board_init_f() too), the support card information has not been
displayed because check_support_card() is invoked only when
show_board_info() fails to get the model name from Device Tree.

This commit adds misc_init_f() function to call check_support_card()
from there.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:03 +09:00
Masahiro Yamada
35adfc4d25 ARM: UniPhier: move SPL init functions to spl_board_init()
Now init functions called from board_postclk_init() and dram_init()
are only necessary for SPL.
Move them to spl_board_init() for clean-up.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:03 +09:00
Masahiro Yamada
84ccd791af ARM: UniPhier: move pin_init() to board_early_init_f()
Currently, I/O pin settings are not necessary for SPL.
The board_early_init_f() seems a suitable place to call pin_init().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:02 +09:00
Masahiro Yamada
aa1cd2cf09 ARM: UniPhier: set I2C offset length of on-board EEPROM in DTS
The EEPROM chips on UniPhier reference daughter boards expect 2-byte
offset address.

Since 7132b9fd68 (dm: i2c: dts: Support an offset-len device tree
property), I2C sub-nodes can have "u-boot,i2c-offset-len" property.

It is convenient to set the default I2C offset address length in
Device Tree, so that we do not have to set it on the command line.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:02 +09:00
Masahiro Yamada
a7f2ecf5dc ARM: UniPhier: move EEPROM device node into a separate DTS
This EEPROM chip is installed on the expansion board commonly used
on UniPhier platform.  To avoid duplicated description, move the
EEPROM node to a separate file and include it from other device tree
sources.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:15:02 +09:00
Masahiro Yamada
5848899a1f ARM: UniPhier: remove dummy gpio.h
This dummy header was introduced by commit 630bf80ebb (ARM:
UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL).

Thanks to commit a08d643dbd (dm: Drop gpio.h header from
fdtdec.c), such an ugly workaround is no longer needed.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07 00:10:34 +09:00
Simon Glass
23d184d2fb arm: Show relocated PC/LR in the register dump
If we don't know the relocation address, the raw values are not very useful.
Show the pre-relocation values as well as these can be looked up in
System.map, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-02-03 18:42:01 +01:00
Tom Rini
37ffffb98d Merge branch 'master' of git://git.denx.de/u-boot-ti 2015-02-02 12:37:34 -05:00
Tom Rini
be8ddad9c8 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2015-02-02 10:11:44 -05:00
Hans de Goede
37d46dd3c4 sunxi: rsb: Move rsb_set_device_mode() call to rsb_init()
It turns out that the device_mode_data is rsb specific, rather then slave
specific, so integrate the rsb_set_device_mode() call into rsb_init().

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-02-02 13:55:14 +01:00
Hans de Goede
d35488c735 sunxi: rsb: Add sun9i (A80 support)
Add support for the A80 to the rsb code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-02-02 13:55:14 +01:00
Hans de Goede
c13f60d92a sunxi: Add a GMAC Transmit Clock Delay Chain Kconfig option
And use this to set the GMAC Transmit Clock Delay Chain value on Banana
boards, rather then keying of CONFIG_TARGET_FOO.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-02-02 13:55:14 +01:00
Bhupesh Sharma
37118fb27b Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas
This patch adds basic constructs in the ARMv8 u-boot code
to handle and apply Cortex-A57 specific erratas.

As and example, the framework showcases how erratas 833069, 826974
and 828024 can be handled and applied.

Later on this framework can be extended to include other
erratas.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2015-01-31 23:43:06 +01:00
Tom Rini
8e3da9dd11 Merge branch 'master' of git://git.denx.de/u-boot-dm 2015-01-30 09:24:42 -05:00
Peng Fan
0f274f5376 ARM: armv7 fix spelling of SCTRL
SCTLR is the abbreviation of System Control Register, so we should
use SCTLR but not SCTRL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-01-30 09:19:17 -05:00
Linus Walleij
ffc103732c vexpress64: support the Juno Development Platform
The Juno Development Platform is a physical Versatile Express
device with some differences from the emulated semihosting
models. The main difference is that the system is split in
a SoC and an FPGA where the SoC hosts the serial ports at
totally different adresses.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30 09:19:17 -05:00
Linus Walleij
f91afc4d00 vexpress64: get rid of CONFIG_SYS_EXTRA_OPTIONS
The Versatile Express ARMv8 semihosted FVP platform is still
using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure
some compile-time flags. Get rid of this and create a Kconfig
entry for the FVP model, and a selectable bool for the
semihosting library.

The FVP subboard is now modeled as a target choice so we can
eventually choose between different ARMv8 versatile express
boards (FVP, base model, Juno...) this way. All dependent
symbols are updated to reflect this.

The 64bit Versatile Express board symbols are renamed
VEXPRESS64 so we have some chance to see what is actually
going on. Tested on the FVP fast model.

Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30 09:19:17 -05:00
Simon Glass
bd768264fb dm: exynos: dts: Set the offset length for cros_ec
The EC has no concept of offset, so use a value of 0.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:10:01 -07:00
Przemyslaw Marczak
55df43c941 odroid u3: dts: add missing i2c aliases
This change fixes i2c bus numbering for Odroid U3.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2015-01-29 17:10:00 -07:00
Przemyslaw Marczak
fda0e27bfd exynos5: pinmux: check flag for i2c config
Some versions of Exynos5 supports High-Speed I2C,
on few interfaces, this change allows support this.
The new flag is: PINMUX_FLAG_HS_MODE

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:10:00 -07:00
Przemyslaw Marczak
232a02cf01 arndale: dts: add missing i2c aliases
Without this alias setting, the seq numbers
of the i2c devices are wrong.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2015-01-29 17:10:00 -07:00
Przemyslaw Marczak
8fd10a8dbf exynos4: dts: add missing i2c properties
This patch modify i2c nodes in exynos4.dtsi with:
- adding proper interrupts arrays for each i2c node,
  which allows to decode periph id
- add reg address for each i2c node for i2c driver internal use

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-01-29 17:10:00 -07:00
Simon Glass
25ab4b0303 dm: i2c: Provide an offset length parameter where needed
Rather than assuming that the chip offset length is 1, allow it to be
provided. This allows chips that don't use the default offset length to
be used (at present they are only supported by the command line 'i2c'
command which sets the offset length explicitly).

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
2015-01-29 17:09:53 -07:00
Simon Glass
6f755eb66b dm: exynos: dts: Use GPIO bank phandles for GPIOs
U-Boot now supports using GPIOs using bank phandles instead of global
numbers. Update the exynos device tree files to use this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2015-01-29 17:09:53 -07:00
Simon Glass
2b2b50bc87 dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOs
This new method is much easier and matches the kernel.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:52 -07:00
Simon Glass
0347960b87 dm: mmc: Remove use of fdtdec GPIO support
These functions are going away, so use the new uclass support instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:52 -07:00
Simon Glass
9762a415c8 dm: zynq: Remove inline gpio functions
These functions serve no useful purpose, and conflict with the generic API.
Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:52 -07:00
Simon Glass
04072cba19 dm: tegra: video: Remove use of fdtdec GPIO support
These functions are going away, so use the new uclass support instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:51 -07:00
Tom Rini
212324a9d4 davinci: Do not duplicate setting of gd
In f0c3a6c we stopped setting gd in board_init_f, but later had to
revert to due problems on certain platforms.  As davinci does not look
to have these problems, we can drop the setting here and rely upon
crt0.S to do it.

Cc: Peter Howard <pjh@northern-ridge.com.au>
Signed-off-by: Tom Rini <trini@ti.com>
2015-01-29 12:00:50 -05:00
Albert ARIBAUD \(3ADEV\)
7bc53efcd6 omap3: add some MUX definitions for upcoming cairo
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29 12:00:50 -05:00
Albert ARIBAUD \(3ADEV\)
5bfdd1fc97 omap3: mmc: add 1.8v bias setting for MMC1
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29 12:00:50 -05:00
Albert ARIBAUD \(3ADEV\)
d215b3e5e3 omap3: add SDRC settings for Samsung K4X51163PG
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29 12:00:50 -05:00
Albert ARIBAUD \(3ADEV\)
03843da5d5 omap3: make SDRC SHARING setting configurable
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29 12:00:50 -05:00
Albert ARIBAUD \(3ADEV\)
168f594765 omap3: enable GP9 timer and UART2
These are needed for the upcoming Cairo board support.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29 12:00:50 -05:00
Lubomir Popov
b558af8128 ARM: OMAP5: DRA7xx: Add support for power rail grouping
On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by a number of
corresponding PMIC OTP versions.

This patch implements correct operation of the core voltages
scaling routine by ensuring that each SMPS that is supplying
more than one domain shall be written only once, and with the
highest voltage of those fused in the SoC (or of those defined
in the corresponding header if fuse read is disabled or fails)
for the power rails belonging to the group.

The patch also replaces some PMIC-related magic numbers with
the appropriate definitions. The default OPP_NOM voltages for
the DRA7xx SoCs are updated as well, per the latest DMs.

Signed-off-by: Lubomir Popov <l-popov@ti.com>
2015-01-29 12:00:49 -05:00
Tom Rini
aed03faa06 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-01-26 06:42:40 -05:00
Tom Rini
306df2c824 Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2015-01-26 06:42:15 -05:00
Michal Simek
c8eac66bae ARM: zynq: List qspi, smc and nand baseaddresses
Add missing addresses to the list.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
63e3cea515 ARM: zynq: List nand, qspi and jtag boot modes
Use full boot mode list in SPL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Siva Durga Prasad Paladugu
f60c6fbbc6 ARM: zynq: slcr: Dont modify the reserved bits
Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
3ad87ca182 ARM: zynq: ddrc: Setup half of memory only for ECC case
Setup half of memory from ram_size for ECC case.
All the time the same board can be configured
with or without ECC. Based on ECC case detection
use half of memory with the same configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
555c7c066f ARM: zynq: Remove empty line
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
c08cfc2d2c ARM: zynq: Enable the Neon instructions
Added the lowlevel_init to enable the Neon instructions.

Initially the u-boot was causing undefined instruction
exception if loaded through tcl, and working fine if loaded
through FSBL. The exception was causing in convertion formula
of given time to ticks. It was because, the Neon instructions
were disabled and hence causing the undefined exception. In
FSBL case, the FSBL was enabling the Neon instructions. Hence,
added the lowlevel_init to enable the Neon instructions.

Also enable neon instructions for non-xilinx toolchain.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:31 +01:00
Tom Rini
03cae7261e Merge branch 'master' of git://git.denx.de/u-boot-marvell 2015-01-25 19:05:40 -05:00
Luka Perkov
62d1e990d9 ARM: kirkwood: fix cpu info for 6282 device id
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Stefan Roese <sr@denx.de>
2015-01-25 23:56:15 +01:00
tang yuantian
41ba57d0c7 fsl/ls1021qds: Add deep sleep support
Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24 09:12:32 -06:00
Alison Wang
33d2e46591 ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Alison Wang
7df50fd323 arm: ls102xa: Update snoop settings for CCI-400
CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
S0 will cause CAAM self test failure. This patch is to enable snooping
for S0 slave interface. These CCI-400 operations are moved to
board_early_init_f() to be initialized earlier. For S4 slave interface,
issuing of snoop requests and DVM message requests are enabled.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
tang yuantian
5699274373 ARM: HYP/non-sec: Make variable gic_dist_addr as a local one
Defining variable gic_dist_addr as a globe one prevents some
functions, which use it, from being used before relocation
which is the case in the deep sleep resume process on Freescale
SoC platforms.
Besides, we can always get the GIC base address by calling
get_gicd_base_address() without referring gic_dist_addr.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Ruchika Gupta
0181937fa3 crypto/fsl: Add fixup for crypto node
Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Ruchika Gupta
d8f527578e arm: ls102xa: Add dummy gpio.h to enable CONFIG_OF_CONTROL
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>.  As a result, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they
do not support GPIO.

The right fix would be to split the lib/fdtdec.c to remove
dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h>
to support OF_CONTROL for LS102x platform. This dummy header
will be removed after FDT-GPIO stuff is fixed correctly.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Alison Wang
0f5e5579f2 ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as default
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
York Sun
dda3b610ee arm/ls1021a: Add workaround for DDR erratum A008378
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:13 -06:00
Tom Rini
3b95288a2a Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-01-23 10:22:29 -05:00
Tom Rini
032c6867a2 Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2015-01-22 20:04:06 -05:00
Masahiro Yamada
0ba924a4ec ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2
PH1-sLD3, PH1-LD6b have DDR channel 2.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:52:16 +09:00
Masahiro Yamada
367a0d51db ARM: UniPhier: rename SG_MEMCONF_* macros for readability
Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined
by <linux/sizes.h> for readability.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:52:14 +09:00
Masahiro Yamada
4a35d60718 ARM: UniPhier: use <linux/sizes.h> for readability
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:52:06 +09:00
Masahiro Yamada
ee94ee3464 ARM: UniPhier: remove non-sense inline directives
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:51:44 +09:00
Masahiro Yamada
ec79c79824 ARM: UniPhier: add static to local functions
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:51:21 +09:00
Masahiro Yamada
448437496b ARM: UniPhier: fix IECTRL set code for PH1-Pro4
For PH1-Pro4, the bit 6 of the IECTRL must be set.  It is the only
available bit in this register.  There is no effect of the write
access to the other bits.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:50:57 +09:00
Masahiro Yamada
061ae4c0bb ARM: UniPhier: describe init_page_table shorter
The assembly directive ".rept ... .endr" allows us to write the
init_page_table much shorter.  To make things further simpler,
set the text and stack area as Normal Memory, and the other sections
as Device attribute.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:50:21 +09:00
Masahiro Yamada
89a7c773ea ARM: UniPhier: fix comments in SoC Glue init function
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:49:57 +09:00
Masahiro Yamada
d6bc30af52 ARM: UniPhier: remove __packed that causes a problem on GCC 4.9
The DDR PHY training function, ddrphy_prepare_training() would not
work if compiled with GCC 4.9.

The struct ddrphy (arch/arm/include/asm/arch-uniphier/ddrphy-regs.h)
is specified with __packed because it represents a hardware register
mapping, but it turned out to cause a problem on GCC 4.9.

If -mno-unaligned-access is specified (yes, it is in
arch/arm/cpu/armv7/config.mk), GCC 4.9 is aware of the
__attribute__((packed)) and generates extra instructions to perform
the memory access in a way that does not cause unaligned access.
(Actually it is not need here because the register base, the first
argument of the ddrphy_prepare_training(), is always given with a
4-byte aligned address.)

Anyway, as a result, readl() / writel() is divided into byte-wise
accesses.  The problem is that this hardware only accepts 4-byte
register access.  Byte-wise accesses lead to unexpected behavior.

There are some options to avoid this problem.

[1] Remove -mno-unaligned-access
[2] Add __aligned(4) along with __packed to struct ddrphy
[3] Remove __packed from struct ddrphy

[1] solves the problem for ARMv7, but it does not for pre-ARMv6 and
ARMv6-M architectures where -mno-unaligned-access is default.
So, [1] does not seem reasonable in terms of code portability.

Both [2] and [3] work well, but [2] seems too much.  All the members
of struct ddrphy have the u32 type.  No padding would be inserted
even if __packed is dropped.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
2015-01-23 00:44:17 +09:00
Tom Rini
65afbbde6b Merge branch 'phys_t' of git://www.denx.de/git/u-boot-microblaze 2015-01-22 09:51:18 -05:00
Hans de Goede
1a800f7af3 sunxi: Hookup OTG USB controller support
Hookup OTG USB controller support and enable the otg controller + USB-keyb
on various tablets.

This allows tablet owners to interact with u-boot without needing to solder
a serial console onto their tablet PCB.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:56 +01:00
Hans de Goede
7cd6f92d41 sunxi: video: Use frontend for dma on sun4i to fix memory bandwidth problems
Testing has shown that on sun4i the display backend engine does not have
deep enough fifo-s causing flickering / tearing in full-hd mode due to
fifo underruns. On sun4i use the display frontend engine to do the dma from
memory, as the frontend does have deep enough fifo-s.

As added advantage of this is that it results in much better memory bandwidth
as it reduces the amount of dram bank switches, for more details see:

http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html

Note that this changes the pipeline searched for in the simplefb node, we can
get away with doing this now, since no kernel has yet shipped with simplefb
dtb nodes, and I will make sure to get a simplefb node with the new pipeline
into 3.19 before it ships.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:56 +01:00
Hans de Goede
8ffc487c75 sunxi: Stop differentiating between 512M and 1G variants of the same board
While working on adding more boards I noticed that we lack a config for
the 512M cubieboard, and that some of the new boards which I want to add also
have 512M and 1G variants, rather then adding 2 defconfig's for all of these,
lets switch the exising boards which have both a 512M and 1024M variant over
to the sun4i dram autoconfig code.

This also drops the foo_RAMSIZE_defconfig variants of boards where we currently
have 2 separate configs already.

Note:
1) The newly introduced CONFIG_DRAM_EMR1 kconfig value is not used with
a value other then its default for now, but we need this to be configurable
to support some new boards with auto dram config.

2) We always set all CONFIG_DRAM_foo values in defconfigs, even if they match
the defaults, this is done to make it more clear what values are used for a
certain board.

This has been tested on a Mele A1000, Mini-X and a Cubieboard, all 1G
variants, the dram autoconfig code has also been tested on a 512M mk802
(a defconfig for the mk802 is added in a later patch).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:56 +01:00
Hans de Goede
daf22636c2 sunxi: mmc: Add support for sun9i (A80)
The clocks on the A80 are hooked up slightly different, add support for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
dacc0881ac sun9i: Add sun9i (A80) clock setup support
Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
going.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
e35377d726 sun9i: Add clock_sun9i.h with ccu register layout for sun9i
Add a headerfile with the sun9i ccu register layout.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
ee74fec845 sun9i: Add cpu_sun9i.h with iomem defines
Add a headerfile with all the base addresses from the sun9i blocks.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
9803e4e1db sunxi: Rename cpu.h to cpu_sun4i.h
sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite
different, so add a wrapper cpu.h which includes the right mach specific
cpu_sun#i.h based on mach, like we already do with clock.h and dram.h .

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
cc67a0b6e5 sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headers
Which pll-s are available depends on the machine type, move the
clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files
so that we only declare what is actually available. e.g. clock_get_pll5p()
is not available on sun6i / sun8i, and with sun9i we get a completely
different set of plls.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
22b618346a sunxi: Drop pll6 setting from clock_init_uart
As the comment says now that we have SPL support this is no longer necessary,
as PLL6 is already setup with the exact same parameters by the SPL.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
6515032e3b sunxi: display: Make lcd display clk phase configurable
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.

This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.

This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.

The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Christian Gmeiner
8551b3661c ot1200: select SUPPORT_SPL
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-01-22 11:03:18 +01:00
Peng Fan
d9efd47c03 imx:mx6sx add dram io configure for mx6sx
Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs.
Add a new function mx6sx_dram_iocfg to configure dram io.

Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1
to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1
effects as "mmdc1->entry=value".

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-01-22 09:55:47 +01:00
Peng Fan
3dae50d0a7 imx:mx6sxsabresd select SUPPORT_SPL
select SUPPORT_SPL for mx6sxsabresd.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-01-22 09:55:47 +01:00
Hans de Goede
b56f6e2b4e sunxi: Restore lowlevel_init usage
2 recent sunxi changes have removed the usage of lowlevel_init by moving some
code around and then setting CONFIG_SKIP_LOWLEVEL_INIT.
This is problematic for 2 reasons:

1) It does not just stop s_init from being called, it also stops
cpu_init_cp15 from getting called, which is undesirable.

2) We want u-boot.bin to be usable standalone, without SPL, some people e.g.
use an upstream u-boot.bin together with Allwinner's boot0 loader. So
u-boot.bin must (re)initialize the gpios, timer, etc.

This commit restores the lowlevel_init / s_init usage, while keeping the
changes to no longer use the global-data (gd) struct in the SPL.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-21 10:46:28 -05:00
Michal Simek
38cd2d9c9b mmc: zynq: Use phys_addr_t for addresses
phys_addr_t is designed for physical addresses that's why
use it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-21 10:30:43 +01:00
Tom Rini
1cd2000698 Merge branch 'master' of git://git.denx.de/u-boot-mmc 2015-01-20 10:21:36 -05:00
Simon Glass
80caacf9de zynq: Remove reference to gdata
The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-20 10:15:15 -05:00
Nobuhiro Iwamatsu
72d42bad58 mmc: rmobile: Add SDHC support for Renesas rmobile ARM SoC
This adds Renesas rmobile ARM SoC's SD/MMC host support.
This drivers tested with Gose board and Koelsch board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2015-01-19 16:24:25 +02:00
Bo Shen
765ece8b13 ARM: atmel: sama5d4: add usb device initial code
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-01-19 15:02:44 +01:00
Bo Shen
e05e46ed3c ARM: atmel: sama5d4: add usb platform data
The SAMA5D4 has the same usb platform data with SAMA5D3 SoC.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-01-19 15:02:43 +01:00
Heiko Schocher
99197a9e31 arm, arm926ejs: make thumb mode compileable
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:

{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'

so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-01-19 12:49:26 +01:00
Stefan Roese
5d6050fdb8 arm: mx6: Add Barco platinum-picon and platinum-titanium
This patch adds the new Barco platinum platform. It currently
includes those two boards:

platinum-titanium
-----------------
This is the same board as the titanium that is already supported in
mainline U-Boot. But its now moved to this new platform to support
multiple "flavors" of imx6 boards in one directory. Its also moved
to support SPL booting. And with this we use the run-time DDR
configuration of this SPL support. The board is equipped with the
Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR
related registers tuples from the imximage.cfg file. As all this
is done in the SPL at run-time.

platinum-picon
--------------
This board is new and based on the MX6DL with 1GiB DDR using the
Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND
chips (each 512MiB).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pieter Ronsijn <pieter.ronsijn@barco.com>
2015-01-19 09:07:31 +01:00
Simon Glass
2b7c0f3081 sunxi: Drop use of lowlevel_init()
This does nothing now, so drop it. We have SPL anyway to do our low-level
init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-16 14:52:53 -05:00
Simon Glass
f630974ccb sunxi: Move SPL s_init() code to board_init_f()
The current sunxi implementation uses gdata, which is going away. It also
sets up DRAM before board_init_f() in SPL.

There is really no reason to do much in s_init() since board_init_f() is
called immediately afterwards. The only change is that we need our own
implementation of board_init_f() which sets up DRAM before the BSS (which
is in DRAM) is cleared.

The s_init() code runs once for SPL and again for U-Boot proper. We
shouldn't need to init the clock/timer/gpio/i2c init twice, so just have it
in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-16 14:52:52 -05:00
Simon Glass
480ca13e74 arm: Add warnings about using gdata
We need to get rid of this SPL-specific setting of the global_data pointer.
It is already set up in start.S immediately before board_init_f() is called,
and there may be information there that is needed (e.g. pre-reloc malloc
info).

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-16 14:52:52 -05:00
Tom Rini
a6b541b090 TI ARMv7: Don't use GD before crt0.S has set it
Prior to this change we set the gd pointer early so that we can store
data in it.  This becomes problematic for DM changes as well as being
odd in general.  Re-work the code paths so that we don't need to set the
gd pointer so early and instead can rely upon the normal setting of it.

In order to do this we do need to move certain calls from s_init into
spl_board_init(), mainly preloader_console_init and
save_omap_boot_params.

Tested on: Beaglebone Black, AM43xx GP EVM, Beagleboard, Beagleboard xM,
OMAP5 uEVM, DRA7xx EVM
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-16 14:52:52 -05:00
Tom Rini
ab77f24119 Merge branch 'master' of git://git.denx.de/u-boot-ti 2015-01-16 10:25:01 -05:00
Michal Simek
f1075aedd2 ARM: armv8: Fix typo in commentary
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-14 11:37:39 -05:00
Evgeni Dobrev
9637c4b2dd Add support for Seagate BlackArmor NAS220
Add support for Seagate BlackArmor NAS220

Signed-off-by: Evgeni Dobrev <evgeni@studio-punkt.com>
2015-01-14 11:37:39 -05:00
Hans de Goede
a90e77dbeb sunxi: usbc: Add support for usb-vbus0 controller by axp drivebus pin
The axp221 / axp223's N_VBUSEN pin can be configured as an output rather
then an input, and this is used on some boards to control usb-vbus0, add
support for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Hans de Goede
4458b7a6e1 sunxi: usbc: Add support for usb0 to the common usbc code
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Hans de Goede
0eccec4ef1 sunxi: Move usb-controller init code out of ehci-sunxi.c for reuse for otg
Most of the usb-controller init code found in ehci-sunxi.c also is necessary
to init the otg usb controller, so move it to a common place.

While at it also update various #ifdefs / defines for sun8i support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Jan Kiszka
05c4bd3ec3 sun7i: Move psci_arch_init close to text_end
"adr rX, text_end" only works if the label is close. Adding further code
to the other functions will prevent this. So move the containing
function close to label. No functional change.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Jan Kiszka
602fa46c2c sun7i: Add support for taking CPUs offline via PSCI
Based on the original version by Marc Zyngier. It adds a psci_cpu_off
implementation for the A20 SoC. The mechanism works by first preparing
the calling CPU to go offline (disable and flush cache, disable SMP),
then requesting CPU 0 to pull the plug. The request is sent as FIQ on
SGI15.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Hans de Goede
213480e12d sunxi: video: Add lvds support
Add support for lvds lcd panels

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:40 +01:00
Hans de Goede
d9786d2380 sunxi: video: Add VGA output support
Add support for VGA directly from the sunxi SoC / display engine.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:39 +01:00
Hans de Goede
2dae800f1e sunxi: video: Add lcd output support
Add lcd output support, see the new Kconfig entries and doc/README.video for
how to enable / configure this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:39 +01:00
Hans de Goede
5489ebc7af sunxi: video: Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1
Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1, this is a
preparation patch for adding lcd support.

While at it also swap the divider search order, searching from low to
high, as the comment above the code says we should do. In cases where there
are multiple solutions this will result in picking a lower pll clock and
divider, which is more stable and saves power.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:39 +01:00
Hans de Goede
6c727e09a0 sunxi: gpio: Add support for gpio pins on the AXP209 pmic
Some boards use GPIO-s on the pmic, one example of this is the A13-OLinuXino
board, which uses gpio0 of the axp209 for the lcd-power signal.

This commit adds support for gpio pins on the AXP209 pmic, the sunxi_gpio.c
changes are universal, adding gpio support for the other AXP pmics (when
necessary) should be a matter of adding the necessary axp_gpio_foo functions
to their resp. drivers, and add "#define AXP_GPIO" to their header file.

Note this commit only adds support for the non device-model version of the
gpio code, patches for adding support to the device-model version are very
welcome.

The string representation for these gpio-s is AXP0-#, the 0 in the AXP0 prefix
is there in case we need to support gpio-s on more then 1 pmic in the future.
At least A80 boards have 2 pmics, and we may end up needing to support gpio-s
on both.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:38 +01:00
Hans de Goede
d27f7d14ea sunxi: gpio: Properly sort mux defines by port number
Move a few mux defines around so that all the mux defines are properly sorted
by port number.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:38 +01:00
Hans de Goede
876aaafdbd sunxi: video: Set input sync enable
Add a write to the "unknown" (*) register to enable auto input sync, when
initially adding sunxi hdmi output support this magic write from the android
kernel code was missed, causing lcdc -> hdmi encoder sync problems.

With this write added, we can drop the modesetting retries and the extra
delays added to work around these sync problems.

With the retries dropped there also is no need to 0 all the enable flags at
the beginning of the modeset, as they are initialized to 0 already by
engines_init.

*) "unknown" is the actual name of this register in the android kernel sources

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
5ee0bea49a sunxi: video: Add hdmi support
So far we've been programming the hdmi-encoder to send out dvi data over the
hdmi connector. This works well for most devices, including hdmi devices, but
not all devices accept dvi data on a hdmi input.

Add support for sending proper hdmi data over the hdmi output found on most
sunxi boards. This can be turned on by adding monitor=hdmi as option to the
video-mode env. variable.

A follow up patch will determine whether to send dvi or hdmi automatically when
EDID is used.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
75481607c7 sunxi: video: Add DDC & EDID support
Add DDC & EDID support and use it to automatically select the native mode of
the attached monitor. This can be disabled by adding edid=0 as option
to the video-mode env. variable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
25508ab26c sunxi: Fix PLL1 running at half speed on sun8i
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Siarhei Siamashka
c3d2b963c6 sunxi: Fix buggy sun6i/sun8i DRAM size detection logic
After reboot, reset or even short power off, DRAM typically retains
the old stale data for some period of time (for this type of memory,
the bits of data are stored in slowly discharging capacitors).

The current sun6i/sun8i DRAM size detection logic, which is
inherited from the Allwinner code, relies on using a large magic
signature with the hope that it is unique enough and unlikely to
ever accidentally match this leftover garbage data in RAM. But
this approach is inherently unsafe, as can be demonstrated using
the following test program:

/***** A testcase for reproducing the problem ******/

void main(int argc, char *argv[])
{
    size_t size, i;
    uint32_t *buf;
    /* Allocate the buffer */
    if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) ||
                    !(buf = malloc(size))) {
        printf("Need buffer size in MiB as a cmdline argument\n");
        exit(1);
    }
    /* Fill it with the Allwinner DRAM "magic" values */
    for (i = 0; i < size / 4; i++)
        buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64;
    /* Try to reboot */
    system("reboot");
    /* And wait */
    for (;;) {}
}
/***************************************************/

If this test program is run on the device (giving it a large
chunk of memory), then the DRAM size detection logic in u-boot
gets confused after reboot and fails to initialize DRAM properly.

A better approach is not to rely on luck and abstain from making
any assumptions about the properties of the leftover garbage
data in RAM. Instead just use a more reliable code for testing
whether two different addresses refer to the same memory location.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-14 14:56:37 +01:00
Hans de Goede
08fd1479c7 sun8i: Add dram initialization support
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
2367b44d0f sunxi: Use memcmp for mctl_mem_matches
Use memcmp for mctl_mem_matches instead of DIY.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
5665f50e81 sunxi: Fill memory before comparing it when doing dram init on sun6i
The sun8i boot0 code fills the DRAM with a "random" pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not do it, instead relying on the memory contents being random enough
to begin with for the memcmp to properly detect the wrap-around address, iow
it is working purely by chance. Since our sun6i dram code was modelled after
the boot0 code it contained the same issue.

This commit fixes this by filling the memory with a unique, distinct pattern.

The new mctl_mem_fill function this introduces is added as an inline helper
in dram.h, so that it can be shared with the sun8i dram code.

While at it move mctl_mem_matches to dram.h for re-use in sun8i too.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
07f4fe7d7d sunxi: Move await_completion dram helper to dram.h
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h, rather then adding yet another copy.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
1aac47bd1b sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them
Our old hardcoded k and m values are based on PLL5 being configured in steps
of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the
DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i)
the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps.

This commit adjusts clock_set_pll5 to automatically select the best k and m
depending on the requested clk rate.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
5af741f1e9 sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()
The sun8i dram code sometimes wants to enable sigma delta mode,
add a parameter to allow this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
bdcdf84631 sunxi: axp221: Add axp223 support
The axp223 appears to be the same as the axp221, except that it uses the
rsb to communicate rather then the p2wi. At least all the registers we use
are 100% the same.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
66ebea06f7 sunxi: Add support for the rsb (Reduced Serial Bus)
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.

This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
ce881076fc sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/
The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Jan Kiszka
3f6242eb30 sunxi: Align PSCI stack calculation to comment
0x400 is true 1K.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
cac5b1cc0d sunxi: Add sunxi_get_sid helper function
On sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a helper function to abstract this away.

This makes our MAC address generation code also work on sun6i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
fc3a832576 sunxi: mmc: Properly setup mod-clk and clock sampling phases
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.

The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).

For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.

This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
7582e39eb0 sun6i: dram: Do not try to initialize a second dram chan on A31s
The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
10191ed098 sun6i: Add sunxi_get_ss_bonding_id() function
Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between
the A31s and the A31.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
37781a1a7e sun6i: Make dram clk and zq value Kconfig options
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.

Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
James Doublesin
fc46bae2ae arm: am437x: Enable hardware leveling for EMIF
Switch to using hardware leveling for certain parameters on the EMIF
rather than using precalculated values.  Doing this also means we have a
common place now between am437x and am335x for setting
emif_sdram_ref_ctrl with a value for the correct delay length.

Tested-by: Felipe Balbi <balbi@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13 11:53:39 -05:00
Stefan Agner
75d7a0d7f1 arm: build arch memset/memcpy in Thumb2 mode
Resynchronize memcpy/memset with kernel 3.17 and build them in
Thumb2 mode (unified syntax). Those assembler files can be built
and linked in ARM mode too, however when calling them from Thumb2
built code, the stack got corrupted and the copy did not succeed
(the exact details have not been traced back). However, the Linux
kernel builds those files in Thumb2 mode. Hence U-Boot should
build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set.

To build the files without warning, some assembler instructions
had to be replaced with their UAL compliant variant (thanks
Jeroen for this input).

To build the file in Thumb2 mode the implicit-it=always option need
to be set to generate Thumb2 compliant IT instructions where needed.
We add this option to the general AFLAGS when building for Thumb2.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-01-09 10:20:22 -05:00
Tom Rini
f10d86d3ff Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-08 13:50:38 -05:00
Fabio Estevam
906d6fe303 mx25: Fix boot hang by avoiding vector relocation
Since commit 3ff46cc42b ("arm: relocate the exception vectors") mx25pdk
hangs like this:

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
(hangs)

Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX25 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.

This allows mx25 to boot again.

Acked-By: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-01-08 13:50:17 -05:00
Fabio Estevam
8ed5e4ce0b mx25: Remove empty line after printing the reset cause
Currently there is an unneeded empty line after printing the reset cause:

U-Boot 2015.01-rc4-00080-g0551a93 (Jan 06 2015 - 13:04:19)

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: POR

Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
MMC:   FSL_SDHC: 0

Remove the extra "\n" when printing the reset cause.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-01-08 11:00:45 -05:00
Masahiro Yamada
b4ad44baab ARM: UniPhier: add UART initialization routine for low-level debug
The low-level debugging functions are useful to debug the early boot
stage where the full UART driver is not available.

UniPhier SoCs need to initialize the UART port 0 to use this feature.
The initialization routine is called at the very entry of the
lowlevel_init().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-08 23:01:56 +09:00
Masahiro Yamada
2661dfd004 ARM: UniPhier: enable output of system bus
For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,
the output of the system bus is disabled by default.
It must be enabled by software to have access to the system bus.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-08 23:01:45 +09:00
Masahiro Yamada
5e165b258f ARM: UniPhier: fix SRAM size on support card
The max size of available memories on slot0 and slot1 is 32MB because
 - EA[25] signal is not output on the save-pin mode which is
   used PH1-LD4 or later SoCs.
 - EA[25] signal is not connected by the limitation (or bug?) of
   the PLD logic of DCC support card.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-08 23:01:21 +09:00
Marek Vasut
653cda8f66 dt: socfpga: Replace num-chipselect with num-cs
This optional DT property is called 'num-cs', so repair the misnomers.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-07 12:13:30 +05:30
Marek Vasut
7411486253 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 16:02:58 +05:30
Tom Rini
fc078895d8 Merge branch 'misc' of git://git.denx.de/u-boot-x86 2015-01-05 20:00:25 -05:00
Sjoerd Simons
9332274989 cros-ec-keyboard: Synchronize DT binding from linux
The ChromeOS EC keyboard is used by various different chromebooks. Peach
pi being the third board in the u-boot tree to use it (snow and peach
pit the other two). Rather then embedding the same big DT node in the
peach-pi DT again, copy the dtsi snippit & bindings documentation from
linux and include it in all 3 boards.

This slightly changes the dt bindings in u-boot:
  * google,key-rows becomes keypad,num-rows
  * google,key-colums becomes keypad,num-colums
  * google,repeat-delay-ms and google,repeat-rate-ms are no longer used
    and replaced by hardcoded values (similar to tegra kbc)

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-01-05 17:45:16 -07:00
Karicheri, Muralidharan
58927a964e keystone: set default pci mode to root complex
pci ports are used as root complex in Linux. So set this as default
in u-boot for keystone devices

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
2015-01-05 15:13:47 -05:00
Dmitry Lifshitz
87791adc22 arm: omap: reset sata on boot
On OMAP platforms (like OMAP5) Linux kernel fails to detect a SATA
device if it is used by U-Boot.

It happens because U-Boot does not reset SATA controller before boot.

Reset the controller on OS boot so that Linux will have a clean state
to work with.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2015-01-05 15:13:47 -05:00
Dmitry Lifshitz
8decf5d4a5 OMAP5+: sata/scsi: implement scsi_bus_reset()
Implement missing scsi_bus_reset() for SCSI subsystem commands
on OMAP platforms.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2015-01-05 15:13:46 -05:00
Nishanth Menon
25098144ac Revert "ARM: omap4: Update sdram setting for panda rev A6"
This reverts commit 47a4bea6af.

Signed-off-by: Nishanth Menon <nm@ti.com>
2015-01-05 15:13:45 -05:00
Nishanth Menon
38e5a5abda ARM: OMAP4: Panda: rework DMM logic
Part of DMM logic is reuse from commit
47a4bea6af ("ARM: omap4: Update sdram
setting for panda rev A6") Which broke SDP4430 with ES2.3 (uses old
DDR).

So, to maintain support for newer DDR used in Panda ES rev B3, we
should, in addition to the commit
675cc77a3a ("ARM:OMAP4+: panda-es: Support
Rev B3 Elpida DDR2 RAM"), DDR timings, also do DMM configuration
specific to Panda.

Signed-off-by: Nishanth Menon <nm@ti.com>
2015-01-05 15:13:45 -05:00
Tom Rini
b31079282e omap-common/hwinit-common.c: timer_init() doesn't need to touch gd
The gd will be cleared at first so we don't need to set arch.tbl to 0.
In addition, the checks later against lastinc also work fine with an
initial value of 0 here.  This also brings us in line with sunxi code
for example.

Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-05 15:13:45 -05:00
Tom Rini
b352dde1ea am33xx: Drop timer_init call from s_init
In both SPL and non-SPL cases we will make a call to timer_init() early
on and do not need to call it again within s_init().

Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-05 15:13:45 -05:00
Tom Rini
57b5e43e95 socfpga: Drop redundant save_boot_params
The save_boot_params function here is the same as the default weak one
from arch/arm/cpu/armv7/start.S, drop.

Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-01-05 15:13:44 -05:00
Ian Campbell
97a8196451 ARM: bootm: do not add PSCI to fdt when booting in secure mode.
Commit 8bc347e2ec "ARM: bootm: Allow booting in secure mode on hyp capable
systems" added the capability to select nonsec vs sec mode boot via an
environment var.

There is a subtle gotcha with this functionality, which is that the PSCI nodes
are still created in the fdt (via armv7_update_dt->fdt_psci) even when booting
in secure mode. Which means that if the kernel is PSCI aware then it will fail
to boot because it will try and do PSCI from secure world, which won't work.

This likely didn't get noticed before because the original purpose was to
support booting the legacy linux-sunxi kernels which don't understand PSCI.

To fix expose boot_nonsec (renaming with armv7_ prefix) outside of bootm.c and
use from the virt-dt code.

As well as avoiding the creation of the PSCI nodes we should also avoid
reserving the secure RAM, so do so.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2015-01-05 15:02:03 -05:00
Tom Rini
b4a0b4006f Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-02 07:42:58 -05:00
Tom Rini
a74a4a86a5 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-01-01 15:10:39 -05:00
Peng Fan
b93ab2ee75 arm:mx6sx add QSPI support
Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Tom Rini
6d76e2aca8 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-30 16:42:23 -05:00
Tom Rini
5523cc2b8a Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-12-30 12:17:18 -05:00
Tom Rini
f23041a38a Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2014-12-30 09:11:56 -05:00
Tom Rini
87b27c7aa7 Merge branch 'master' of git://git.denx.de/u-boot-samsung 2014-12-30 09:11:42 -05:00
Marek Vasut
cd3c5896b6 imx: i2c: Zap unnecessary malloc() calls
The malloc() calls are unnecessary, just allocate the stuff on stack.
While at it, reorder the code a little, so that only one variable is
used for the text, use snprintf() instead of sprintf() and use %01d
as a formatting string to avoid any possible overflows.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2014-12-30 14:05:48 +01:00
Pierre Aubert
248802d401 imx SPL: enable boot from eMMC boot partitions.
Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
2014-12-30 14:05:36 +01:00
Stefano Babic
4e0114d967 Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-12-30 13:04:38 +01:00
Masahiro Yamada
7b77c9ab6f ARM: UniPhier: display boot swap pin status by pinmon command
This information would be useful enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-30 17:45:40 +09:00
Masahiro Yamada
c67b2afd6b ARM: UniPhier: add dump command of DDR PHY parameters
This commit adds a dump command of DDR PHY parameters of UniPhier
SoC family.  It might not be used very often for the regular operation
but it would be useful when something goes wrong with DDR memories.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-30 17:45:37 +09:00
Masahiro Yamada
b614e16cc0 ARM: UniPhier: add DDR PHY training code
This training code provides run-time adjustment of DDR PHY parameters
for stable DDR operation.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-30 17:45:25 +09:00
Steve Rae
4d013d8fa8 bcm281xx: add support for "USB OTG clock"
enable this clock with the following:
  clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)

Signed-off-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
2014-12-29 16:31:23 -05:00
Stephen Warren
47705eff7a ARM: rpi: support model A+
Add a board rev entry for the new model A+, and augment the board
rev error handling code to be a bit more verbose.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-29 16:31:22 -05:00
Linus Walleij
9be5c661be arm: semihosting: get rid of forward declarations
By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions follow at the end.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-29 07:44:06 -05:00
Linus Walleij
4e1ef15091 arm: semihosting: fix up compile bugs
There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.

The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and interface, and voila:
the code now works again.

Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Suggested-by: Mark Hambleton <mark.hambleton@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-29 07:44:06 -05:00
Linus Walleij
50b5639430 arm: semihosting: staticize internal functions
The semihosting code exposes internal file handle handling
functions to read(), open(), close() and get the length of
a certain file handle.

However the code using it is only interested in either
reading and entire named file into memory or getting the
file length of a file referred by name. No file handles
are used.

Thus make the file handle code internal to this file by
removing these functions from the semihosting header file
and staticize them.

This gives us some freedom to rearrange the semihosting
code without affecting the external interface.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-29 07:44:06 -05:00
Joonyoung Shim
fb56435f50 arm: exynos: clock: support SPLL as mmc source clock for exynos5420
MMC of exynos5420 can select SPLL as source clock, so add to support
SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-24 10:56:24 +09:00
Sjoerd Simons
ce88a25cc2 odroid-XU3: Add entry for DTS EHCI GPIO
Add samsung,vbus-gpio information for the XU3. This allows the usage of
the EHCI controller on the XU3, which is connected to the SMSC LAN9514
chip (usb hub + network).

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:48:01 +09:00
Sjoerd Simons
a7b99204a0 exynos5420: fix compilation without parade video
Not all exynos 5420 based devices with an LCD also have a parade LVDS
bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled
and CONFIG_VIDEO_PARADE is not.

As a side-effect move the parade functions from the exynos system header
file to its own file.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:38:27 +09:00
Sjoerd Simons
307e90e617 Exynos5800: The Peach-Pi board does not have a Parade video bridge
Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the
Pi. So drop it from  device-tree

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:38:22 +09:00
Hyungwon Hwang
6207604f9c Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:37:10 +09:00
Stefan Roese
d0e932de7c arm: socfpga: Change watchdog timeout
The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.

Also we now call the hw_watchdog_init() function so that we override
the value already configured from the Preloader.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
2014-12-21 14:39:04 +01:00
Peng Fan
eb412d79e4 imx:mx6 fix return value of mxc_get_clock
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0xffffffff', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.

Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-19 10:43:04 +01:00
Thierry Reding
1dfdd9ba4e ARM: Implement non-cached memory support
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).

The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).

While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
6e2fca94ff ARM: tegra: Enable PCIe on Jetson TK1
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
9c46e6cb45 ARM: tegra: Add Tegra124 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra124 SoCs.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
12e5f6acda ARM: tegra: Add GIC for Tegra124
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
affe026928 ARM: tegra: Enable PCIe on Beaver
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.

In addition the board has a mini-PCIe expansion slot.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
5a2c96a0e5 ARM: tegra: Enable PCIe on Cardhu
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
a1811bc5b9 ARM: tegra: Add Tegra30 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra30 SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
cd99876120 ARM: tegra: Add GIC for Tegra30
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use
it directly but subsequent patches will add device tree nodes that
reference it by phandle.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
7dd8738f08 ARM: tegra: Enable PCIe on TrimSlice
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
65d2465d5d ARM: tegra: Add Tegra20 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
b02f3e0c2d ARM: tegra: Enable XUSB pad controller on Jetson TK1
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
78e9f1c4f3 ARM: tegra: Add XUSB pad controller on Tegra124
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
79c7a90f6c ARM: tegra: Implement XUSB pad controller
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
48510c089b ARM: tegra: Implement powergate support
Implement the powergate API that allows various power partitions to be
power up and down.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
59cb3bf4c6 ARM: tegra: Provide PCIEXCLK reset ID
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch defines it
consistently for all supported SoC generations.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
a723074550 ARM: tegra: Implement tegra_plle_enable()
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Marcel Ziswiler
839e4f7c66 ARM: tegra: colibri_t30: comment style fix
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 12:47:11 -07:00
Masahiro Yamada
992e874885 ARM: UniPhier: select CONFIG_SPL
Now UniPhier platform is only supported with SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:27 +09:00
Masahiro Yamada
d4d45ead23 ARM: UniPhier: remove unnecessary ifdef conditional
init_page_table is only set on SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:12 +09:00
Masahiro Yamada
490f55c4a6 ARM: UniPhier: fix property names of aliases nodes of device trees
The property name of the "aliases" node should be "serial*"
to assign a desired number for the device sequence number.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:01 +09:00
Tom Rini
3bfbf32b6f Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-16 09:41:00 -05:00
Tom Rini
a5a5882611 Merge git://git.denx.de/u-boot-dm 2014-12-11 20:47:34 -05:00
Tom Rini
fc9b0b8043 Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11 18:40:49 -05:00
Tom Rini
2c49323d5d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-12-11 18:28:09 -05:00
Simon Glass
b0e6ef4640 dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:44 -07:00
Allen Martin
a6c7b46181 ARM: tegra: Add support for nyan-big board
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.

This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.

The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
2014-12-11 13:18:44 -07:00
Simon Glass
754204b5c2 tegra: dts: Sync tegra124.dtsi with linux kernel
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-12-11 13:18:44 -07:00
Simon Glass
6ee350bb93 dts: Bring in Chrome OS keyboard device tree definition
This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:43 -07:00
Alison Wang
0de15707a7 kconfig: ls102xa: Change the prompt messages
As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message "Support ls1021aqds_nor" in
Kconfig is not clear. This patch changes it to
"Support ls1021aqds".

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:41 -08:00
Xiubo Li
660673af4f ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:22 -08:00