Commit graph

457 commits

Author SHA1 Message Date
Stefan Roese
f31d38b9ee ppc4xx: Enable 405EX PCIe UTL register configuration
Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-16 14:16:54 +01:00
Stefan Roese
aee747f19b ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms
- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-15 14:23:55 +01:00
Stefan Roese
7d0a4066b5 ppc4xx: Fix 405EX PCIe UTLSET register setup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-13 08:06:11 +01:00
Matthias Fuchs
9be659ac08 ppc4xx: Make USB working with CONFIG_4xx_DCACHE defined
This patch disables the 44x d-cache on 'usb start' and
reenables it on 'usb stop'. This should be seen as a
temporary fix until the generic usb-ohci driver can
life with d-cache enabled.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-09 16:42:15 +01:00
Matthias Fuchs
fbde2169d2 ppc4xx: Remove redundant code from 4xx network driver
This patch removes some redundant code and decrements the end
address of cache flush and invalidate by 1.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-09 16:42:15 +01:00
Stefan Roese
c7f69c3402 ppc4xx: Make output a little shorter on I2C bootrom detection
Most 4xx PPC capable of using an I2C bootrom for bootstrap setting
already print a line with the information which I2C bootrom is
used for bootstrap configuration. So we don't need this extra line
with "I2C boot EEPROM en-/dis-abled".

This patch also has a little code cleanup integrated.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-09 12:18:54 +01:00
Stefan Roese
ea2e142843 ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM
This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.

This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
ff768cb168 ppc4xx: Change 4xx ethernet driver to handle cached memory too
This patch enables the 4xx EMAC driver to work too, when dcache is
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
483e09a223 ppc4xx: Add change_tlb function to modify I attribute of TLB(s)
This function is used to either turn cache on or off in a specific
memory area.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
9b94ac61d2 ppc4xx: Rework 4xx cache support
New cache handling functions added and all existing functions
moved from start.S into seperate cache.S.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
1338e6a818 ppc4xx: Change autonegotiation timeout from 4 to 5 seconds
I lately noticed, that newer 4xx board with GBit support sometimes don't
finish link autonegotiation in 4 seconds. Changing this timeout to 5
seconds seems fine here.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
2d83476a4c ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friends
This patch changes all in32/out32 calls to use the recommended in_be32/
out_be32 macros instead.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
f10493c6d7 ppc4xx: Correct UART input clock calculation and passing to fdt
We now use a value in the gd (global data) structure for the UART input
frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely
in get_sys_info().

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
353f2688b4 ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board support
The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
3248f63ad8 ppc4xx: Rework of 4xx serial driver (4)
Change 4xx_uart.c:

- Use in_8/out_8 macros instead of in8/out8
- No need for UART_BASE marco anymore, now really handled via function
  parameter
- serial_init_common() introduced
- Further coding style cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
ad31e40bed ppc4xx: Rework of 4xx serial driver (1)
This patch starts the rework of the PPC4xx serial driver. First we split
the file into two seperate files, one 4xx_uart.c with the 405/440 UART
handling code and the other one iop480_uart.c with the UART code for the
PLX-Tech IOP480 PPC (PPC403 based).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
764e7417ee ppc4xx: Correct UART input clock calculation and passing to fdt
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
fa8aea2045 ppc4xx: Add freqUART to CPU speed detection
This value is needed later for the device tree configuration of
the uart clock.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
087dfdb79b ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
5cb4af4791 ppc4xx: Add PCIe endpoint support on Kilauea (405EX)
This patch adds endpoint support for the AMCC Kilauea eval board. It can
be tested by connecting a reworked PCIe cable (only 1x lane singles
connected) to another root-complex.

In this test setup, a 64MB inbound window is configured at BAR0 which maps
to 0 on the PLB side. So accessing this BAR0 from the root-complex will
access the first 64MB of the SDRAM on the PPC side.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
d4cb2d1794 ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.

This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:

pcie_mode=RP:EP:EP

This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.

Per default Yucca will be configured as:
pcie_mode=RP:EP:EP

Per default Katmai will be configured as:
pcie_mode=RP:RP:REP

Per default Kilauea will be configured as:
pcie_mode=RP:RP

Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
4994ffd890 ppc4xx: Add additional debug info to 4xx fdt support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
1941cce71b ppc4xx: Fix small merge problem in 4xx_enet.c
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
dbbd125721 ppc4xx: Add PPC405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
1d7b874e9c ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming)
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
4f14ed6230 ppc4xx: Add initial fdt support to 4xx (first needed on 405EX)
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
19e93b1e16 ppc4xx: 4xx_pcie: Change PCIe status output to match common style
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
ff68f66bcb ppc4xx: 4xx_pcie: Disable debug output as default
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
97923770cb ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
4dbee8a90d ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & Katmai
128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.

One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.

This patch adds debug output to the 4xx pcie driver too.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
6d95289281 ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idx
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
3048bcbf0b ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platforms
These files were introduced with the IBM 405GP but are currently used on all
4xx PPC platforms. So the name doesn't match the content anymore. This patch
renames the files to 4xx_pci.c/h.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
94276eb0a7 ppc4xx: Add a comment for 405EX PCIe endpoint configuration
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
03d344bb6a ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
    the SDR registers of the PCIe ports. This makes the overall design
    clearer, since it removed a lot of switch statements which are not
    needed anymore.

    Also, the functions ppc4xx_init_pcie_rootport() and
    ppc4xx_init_pcie_entport() are merged into a single function
    ppc4xx_init_pcie_port(), since most of the code was duplicated.
    This makes maintainance and porting to other 4xx platforms
    easier.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
026f711068 ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(2) This patch renames the functions from 440spe_ to 4xx_ with a
    little additional cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
c7c6da2302 ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(1) This patch renames the files from 440spe_pcie to 4xx_pcie

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:48 +01:00
Stefan Roese
738815c0cc ppc4xx: Coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-02 11:44:46 +02:00
Grzegorz Bernacki
2db6478406 Program EPLD to force full duplex mode for PHY.
EPLD forces modes of PHY operation. By default full duplex is turned off.
This fix turns it on.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-10-02 11:30:37 +02:00
Grzegorz Bernacki
7f19139389 [PPC440SPe] Improve PCIe configuration space access
- correct configuration space mapping
- correct bus numbering
- better access to config space

Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-07 18:20:23 +02:00
Grzegorz Bernacki
15ee4734e4 [PPC440SPe] Convert machine check exceptions handling
Convert using fixup mechanism to suppressing MCK for the duration of config
read/write transaction: while fixups work fine with the case of a precise
exception, we identified a major drawback with this approach when there's
an imprecise case. In this scenario there is the following race condition:
the fixup is (by design) set to catch the instruction following the one
actually causing the exception; if an interrupt (e.g. decrementer) happens
between those two instructions, the ISR code is executed before the fixup
handler the machine check is no longer protected by the fixup handler as it
appears as within the ISR code. In consequence the fixup approach is being
phased out and replaced with explicit suppressing of MCK during a PCIe
config read/write cycle.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-07 17:46:18 +02:00
Kim Phillips
79f240f7ec lib_ppc: make board_add_ram_info weak
platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.

this consequently eliminates CONFIG_ADD_RAM_INFO.

Thanks to Stefan for the hint.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-18 21:39:46 +02:00
Stefan Roese
3b3bff4cbf Merge with git://www.denx.de/git/u-boot.git 2007-08-14 16:36:29 +02:00
Stefan Roese
429d9571f6 Coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-14 15:03:17 +02:00
Stefan Roese
34886bbea2 Merge with /home/stefan/git/u-boot/zeus 2007-08-14 15:00:42 +02:00
Stefan Roese
779e975117 ppc4xx: Add initial Zeus (PPC405EP) board support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-14 14:44:41 +02:00
Stefan Roese
273db7e1bd ppc4xx: Fix problem in PLL clock calculation
This patch was originall provided by David Mitchell <dmitchell@amcc.com>
and fixes a bug in the PLL clock calculation.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-13 09:05:33 +02:00
Markus Klotzbuecher
78549bbf44 Merge with git://www.denx.de/git/u-boot.git 2007-08-07 22:30:29 +02:00
Wolfgang Denk
f2c2a937d8 Merge with /home/wd/git/u-boot/custodian/u-boot-testing 2007-08-06 01:11:08 +02:00
Wolfgang Denk
5728be389e Coding style cleanup. Update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-08-06 01:01:49 +02:00
Andy Fleming
6bf6f114dc Merge branch 'testing' into working
Conflicts:

	CHANGELOG
	fs/fat/fat.c
	include/configs/MPC8560ADS.h
	include/configs/pcs440ep.h
	net/eth.c
2007-08-03 02:23:23 -05:00
Stefan Roese
9ca8d79de0 ppc4xx: Code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-02 08:33:56 +02:00
Grzegorz Bernacki
c924098122 [ppc440SPe] Graceful recovery from machine check during PCIe configuration
During config transactions on the PCIe bus an attempt to scan for a
non-existent device can lead to a machine check exception with certain
peripheral devices. In order to avoid crashing in such scenarios the
instrumented versions of the config cycle read routines are introduced, so
the exceptions fixups framework can gracefully recover.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Rafal Jaworowski <raj@semihalf.com>
2007-08-02 08:25:27 +02:00
Rafal Jaworowski
dec99558b9 [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A
This brings back separate settings for PCIe bus numbers depending on chip
revision, which got eliminated in 2b393b0f0a
commit. 440SPe rev. A does NOT work properly with the same settings as for
the rev. B (no devices are seen on the bus during enumeration).

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2007-08-02 08:25:18 +02:00
Eugene OBrien
d2f6800662 ppc4xx: Update AMCC Bamboo 440EP support
Changed storage type of cfg_simulate_spd_eeprom to const
Changed storage type of gpio_tab to stack storage
(Cannot access global data declarations in .bss until afer code relocation)

Improved SDRAM tests to catch problems where data is not uniquely addressable
(e.g. incorrectly programmed SDRAM row or columns)

Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules
Fixed AM29LV320DT (OpCode Flash) sector map

Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-31 10:24:56 +02:00
Stefan Roese
27a528fb41 ppc4xx: Only print ECC related info when the error bis are set
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-30 11:04:57 +02:00
John Otken
d4024bb72d ppc4xx: Add support for AMCC 405EP Taihu board
Signed-off-by: John Otken <john@softadvances.com>
2007-07-26 17:49:11 +02:00
Stefan Roese
a71d96eac8 ppc4xx: Fix bug with default GPIO output value
As spotted by Matthias Fuchs, the default output values for all GPIO1
outputs were not setup correctly. This patch fixes this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-20 15:03:44 +02:00
Stefan Roese
8f085e324a Merge with git://www.denx.de/git/u-boot.git 2007-07-16 13:28:47 +02:00
Stefan Roese
8848ec858f ppc4xx: Code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16 10:02:12 +02:00
Stefan Roese
6ed14addf9 ppc4xx: Add new weak functions to support boardspecific DDR2 configuration
The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better
support non default, boardspecific DDR(2) controller configuration.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16 09:57:00 +02:00
Stefan Roese
5743a9207a ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup
The new function remove_tlb() can be used to remove the TLB's used to
map a specific memory region. This is especially useful for the DDR(2)
setup routines which configure the SDRAM area temporarily as a cached
area (for speedup on auto-calibration and ECC generation) and later
need this area uncached for normal usage.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16 08:53:51 +02:00
Stefan Roese
a2e1c7098c ppc4xx: Change receive buffer handling in the 4xx emac driver
This change fixes a bug in the receive buffer handling, that
could lead to problems upon high network traffic (broadcasts...).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-12 16:32:08 +02:00
Wolfgang Denk
239f05ee4d Update CHANGELOG, minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-07-12 01:45:34 +02:00
Jon Loeliger
068b60a0eb cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-10 10:27:39 -05:00
Jon Loeliger
3a1ed1e1f9 cpu/[7a-ln-z]*: Remove obsolete references to CONFIG_COMMANDS
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-09 18:57:22 -05:00
Wolfgang Denk
4ef218f6fd Coding style cleanup; update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-07-10 00:01:28 +02:00
Wolfgang Denk
bf6a9ca9b2 Merge with /home/hs/Atronic/u-boot 2007-07-09 23:41:45 +02:00
Stefan Roese
6b0a174a1e Fix problem with get/setdcr commands introduced by cfg patches
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-06 10:37:56 +02:00
Sergei Poselenov
b44896215a Merged POST framework with the current TOT.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2007-07-05 08:17:37 +02:00
Wolfgang Denk
52b8704d02 Fix a few file permission problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-07-04 00:43:53 +02:00
Jon Loeliger
737184114e cpu/ non-mpc*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*).
This is a compatibility step that allows both the older form
and the new form to co-exist for a while until the older can
be removed entirely.

All transformations are of the form:
Before:
    #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
After:
    #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT)

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-04 00:34:13 +02:00
Stefan Roese
e4feb7638c Merge with git://www.denx.de/git/u-boot.git 2007-06-25 20:20:30 +02:00
Heiko Schocher
a5d71e290f [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG
Signed-off-by: Heiko Schocher <hs@denx.de>
2007-06-25 19:11:37 +02:00
Niklaus Giger
a1bd6200ec ppc4xx: PPC440EPx Emit DDR0 registers on machine check interrupt
This patch prints the DDR status registers upon machine check
interrupt on the 440EPx/GRx. This can be useful especially when
ECC support is enabled.

I added some small changes to the original patch from Niklaus to
make it compile clean.

Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-25 17:03:13 +02:00
Niklaus Giger
807018fb7f ppc4xx: Fix O=buildir builds
This patch fixes the problem to assemble cpu/ppc4xx/start.S
experienced last week where building failed having specified
O=../build.sequoia.

Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
2007-06-25 16:50:55 +02:00
Matthias Fuchs
5a1c9ff0c4 ppc4xx: Add pci_pre_init() for 405 boards
This patch adds support for calling a plattform dependant
pci_pre_init() function for 405 boards. This can be used to
move the current pci_405gp_fixup_irq() function into the
board code.

This patch also makes the CFG_PCI_PRE_INIT define obsolete.
A default function with 'weak' attribute is used when
a board specific pci_pre_init() is not implemented.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-06-25 11:57:50 +02:00
Wolfgang Denk
1636d1c852 Coding stylke cleanup; rebuild CHANGELOG 2007-06-22 23:59:00 +02:00
Igor Lisitsin
a11e06965e Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440.

Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
2007-06-22 23:21:01 +02:00
Heiko Schocher
566a494f59 [PCS440EP] upgrade the PCS440EP board:
- Show on the Status LEDs, some States of the board.
                - Get the MAC addresses from the EEProm
                - use PREBOOT
                - use the CF on the board.
                - check the U-Boot image in the Flash with a SHA1
                  checksum.
                - use dynamic TLB entries generation for the SDRAM

Signed-off-by: Heiko Schocher <hs@denx.de>
2007-06-22 19:11:54 +02:00
Stefan Roese
3a1f5c81b0 ppc4xx: Fix problem with extended program_tlb() funtion
The recently extended program_tlb() function had a problem when
multiple TLB's had to be setup (for example with 512MB of SDRAM). The
virtual address was not incremented. This patch fixes this issue
and is tested on Katmai with 512MB SDRAM.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-22 16:58:40 +02:00
Rafal Jaworowski
02032e8f14 [ppc] Fix build breakage for all non-4xx PowerPC variants.
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
- minor 4xx cleanup
2007-06-22 14:58:04 +02:00
Wolfgang Denk
83b4cfa3d6 Coding style cleanup. Refresh CHANGELOG. 2007-06-20 18:14:24 +02:00
Stefan Roese
6b44466cde Merge with git://www.denx.de/git/u-boot.git 2007-06-20 08:23:42 +02:00
Stefan Roese
df8a24cdd3 [ppc4xx] Fix problem with NAND booting on AMCC Acadia
The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-19 16:42:31 +02:00
Stefan Roese
b7c3e93105 Merge with /home/stefan/git/u-boot/denx-440-exceptions 2007-06-15 11:20:13 +02:00
Grzegorz Bernacki
efa35cf12d ppc4xx: Clean up 440 exceptions handling
- Introduced dedicated switches for building 440 and 405 images required
  for 440-specific machine instructions like 'rfmci' etc.

- Exception vectors moved to the proper location (_start moved away from
  the critical exception handler space, which it occupied)

- CriticalInput now serviced (with default handler)

- MachineCheck properly serviced (added a dedicated handler and return
  subroutine)

- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  unhandled and those not relevant for 4xx were eliminated)

- Eliminated Linux leftovers, removed dead code

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 11:19:28 +02:00
Stefan Roese
85f737376d [ppc4xx] Extend 44x GPIO setup with default output state
The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup
is extended with the default GPIO output state (level).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 07:39:43 +02:00
Stefan Roese
dbca208518 [ppc4xx] Extend program_tlb() with virtual & physical addresses
Now program_tlb() allows to program a TLB (or multiple) with
different virtual and physical addresses. With this change, now one
physical region (e.g. SDRAM) can be mapped 2 times, once with caches
diabled and once with caches enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-14 11:14:32 +02:00
Wolfgang Denk
9045f33c02 Fix config problems on SC3 board; make ide_reset_timeout work. 2007-06-08 10:24:58 +02:00
Benoît Monin
fba3fb0449 [PATCH] fix gpio setting when using CFG_440_GPIO_TABLE
Set the correct value in GPIOx_TCR when configuring the gpio
with CFG_440_GPIO_TABLE.

Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-08 09:55:24 +02:00
Markus Klotzbuecher
c4e2753436 Merge with git://www.denx.de/git/u-boot.git 2007-06-06 12:36:32 +02:00
Markus Klotzbuecher
dace45acd1 USB: ohci fixes and cleanup for ppc4xx and yosemite board. 2007-06-06 11:49:43 +02:00
Stefan Roese
c440bfe6d6 ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
This patch adds NAND booting support for the AMCC Acadia eval board.

Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.

I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:

=> bootstrap 267 nor	;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand	;to configure the board for 267MHz NNAND booting

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-06 11:42:13 +02:00
Benoît Monin
e3cbe1f93c [PATCH] Fix ppc4xx bootstrap letter displayed on startup
The attached patch is mainly cosmetic, allowing u-boot to
display the correct bootstrap option letter according to the
datasheets.

The original patch was extended with 405EZ support by Stefan
Roese.

Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-04 08:36:05 +02:00
Stefan Roese
f3679aa13d Merge with /home/stefan/git/u-boot/bamboo-nand 2007-06-01 16:15:34 +02:00
Stefan Roese
cf959c7d66 ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board
This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:27:11 +02:00
Stefan Roese
91da09cfbc NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.c
This patch adds hardware ECC support to the NDFC driver. It also
changes the register access from using the "simple" in32/out32
functions to the in_be32/out_be32 functions, which make sure
that the access is correctly synced. This is the only recommended
access to SoC registers in the current Linux kernel.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:15:12 +02:00
Stefan Roese
d2d432760d ppc4xx: 44x DDR driver code cleanup and small fix for Bamboo
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:09:50 +02:00
Stefan Roese
7187db7349 ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
Add config option for 180 degree advance clock control as needed
for the AMCC Luan eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 13:45:00 +02:00
Markus Klotzbuecher
51d8e81322 Merge git://www.denx.de/git/u-boot into 2007_05_15-testing 2007-05-29 16:37:57 +02:00
Stefan Roese
6f3dfc139a ppc4xx: Add 405 support to 4xx NAND driver ndfc.c
This patch adds support for 405 PPC's to the 4xx NAND driver
ndfc.c. This is in preparation for the new AMCC 405EZ.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-22 12:46:10 +02:00
Stefan Roese
10603d7676 ppc4xx: Fix problem in 405EZ OCM initialization
As spotted by Bruce Adler this patch fixes an initialization problem
for the 405EZ OCM.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-21 07:41:22 +02:00
Markus Klotzbuecher
6ede0c8b69 Merge with git://www.denx.de/git/u-boot.git 2007-05-07 14:10:38 +02:00
Wolfgang Denk
2f15278c2e Coding stylke cleanup; update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-05-05 18:23:11 +02:00
Stefan Roese
bd38b7ecfd Merge with git://www.denx.de/git/u-boot.git 2007-04-29 16:40:31 +02:00
Matthias Fuchs
37ed6cdd41 ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-04-24 14:22:41 +02:00
Markus Klotzbuecher
61ea75aa07 Merge with git://www.denx.de/git/u-boot.git 2007-04-23 13:17:22 +02:00
Wolfgang Denk
43f6226db0 Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xx 2007-04-18 17:00:09 +02:00
Stefan Roese
90e6f41cf0 ppc4xx: Add output for bootrom location to 405EZ ports
Now 405EZ ports also show upon bootup from which boot device
they are configured to boot:

U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)

CPU:   AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
       Bootstrap Option E - Boot ROM Location EBC (32 bits)
       16 kB I-Cache 16 kB D-Cache
Board: Acadia - AMCC PPC405EZ Evaluation Board

Signed-off-by: Stefan Roese <sr@denx.de>
2007-04-18 12:05:59 +02:00
Jeffrey Mann
2ad3aba01d ppc4xx: Fix i2c divisor calcularion for PPC4xx
This patch fixes changes the i2c_init(...) function to use the function
get_OPB_freq() rather than calculating the OPB speed by
sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is
specific per processor. The prior method was not and so was calculating
the wrong speed for some PPC4xx processors.

Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-04-12 14:15:59 +02:00
Stefan Roese
cabee756a6 ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
Additional RAM information is now printed upon powerup, like
DDR2 frequency and CAS latency.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-31 13:15:06 +02:00
Stefan Roese
94f54703c3 ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
Fix a bug in the auto calibration routine. This driver now runs
more reliable with the tested modules. It's also tested with
167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-31 08:46:08 +02:00
Stefan Roese
e50b791b3f Merge with /home/stefan/git/u-boot/acadia 2007-03-24 15:59:23 +01:00
Stefan Roese
0d974d5297 [PATCH] Add 4xx GPIO functions
This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-24 15:57:09 +01:00
Stefan Roese
3cb86f3e40 [PATCH] Clean up 40EZ/Acadia support
This patch cleans up all the open issue of the preliminary
Acadia support.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-24 15:45:34 +01:00
Markus Klotzbuecher
f2b07ebd32 Merge with git://www.denx.de/git/u-boot.git#testing-USB 2007-03-23 09:52:17 +01:00
Stefan Roese
fc1e45ce6e Merge with /home/stefan/git/u-boot/acadia 2007-03-21 14:38:25 +01:00
Stefan Roese
e01bd218b0 [PATCH] Add AMCC PPC405EZ support
This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.

Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-21 13:38:59 +01:00
Matthias Fuchs
ced5b90290 [PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUS
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-03-08 22:17:04 +01:00
Wolfgang Denk
efa013df33 Merge with /home/git/u-boot 2007-03-08 11:41:19 +01:00
Wolfgang Denk
35ded29fd9 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-03-08 11:38:58 +01:00
Wolfgang Denk
d8be57669b Merge with /home/git/u-boot 2007-03-08 11:34:24 +01:00
Stefan Roese
cd84528f20 Merge with /home/stefan/git/u-boot/yucca-ddr2 2007-03-08 10:32:45 +01:00
Stefan Roese
00cdb4ce5e [PATCH] Update AMCC Luan 440SP eval board support
The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.

This patch also enables the cache in FLASH for the startup
phase of U-Boot (while running from FLASH). After relocating to
SDRAM the cache is disabled again. This will speed up the boot
process, especially the SDRAM setup, since there are some loops
for memory testing (auto calibration).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:13:16 +01:00
Stefan Roese
df29449747 ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SP
Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:06:09 +01:00
Wolfgang Denk
46270c2851 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-03-07 16:50:34 +01:00
Stefan Roese
e2ebe69681 [PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM's
This patch fixes a problem that occurs when 2 DIMM's are
used. This problem was first spotted and fixed by Gerald Jackson
<gerald.jackson@reaonixsecurity.com> but this patch fixes the
problem in a little more clever way.

This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.

As this feature is new to the "old" 44x SPD DDR driver, it
has to be enabled via the CONFIG_PROG_SDRAM_TLB define.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-07 16:39:36 +01:00
Wolfgang Denk
ad5bb451ad Restructure POST directory to support of other CPUs, boards, etc. 2007-03-06 18:08:43 +01:00
Wolfgang Denk
647d3c3eed Some code cleanup. 2007-03-04 01:36:05 +01:00
Stefan Roese
c8556d0e0b Merge with /home/stefan/git/u-boot/denx-merge-sr 2007-03-01 21:16:02 +01:00
Stefan Roese
ba58e4c9a9 [PATCH] Update AMCC Katmai 440SPe eval board support
This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.

Please note, that still some problems are left with some memory
configurations. See the driver for more details.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-01 21:11:36 +01:00
Wolfgang Denk
743571145b Minor code cleanup. 2007-02-27 14:26:04 +01:00
Stefan Roese
4745acaa1a [PATCH] Add support for the AMCC Katmai (440SPe) eval board
Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:57:08 +01:00
Stefan Roese
4037ed3b63 [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM support
This patch adds support for the DDR2 controller used on the
440SP and 440SPe. It is tested on the Katmai (440SPe) eval
board and works fine with the following DIMM modules:

- Corsair CM2X512-5400C4 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)

This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:43:34 +01:00
Stefan Roese
36d830c983 [PATCH] PPC4xx: Split 4xx SPD SDRAM init routines into 2 files
Since the existing 4xx SPD SDRAM initialization routines for the
405 SDRAM controller and the 440 DDR controller don't have much in
common this patch splits both drivers into different files.

This is in preparation for the 440 DDR2 controller support (440SP/e).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:35:42 +01:00
Stefan Roese
79b2d0bb2e [PATCH] PPC4xx: Add support for multiple I2C busses
This patch adds support for multiple I2C busses on the PPC4xx
platforms. Define CONFIG_I2C_MULTI_BUS in the board config file
to make use of this feature.

It also merges the 405 and 440 i2c header files into one common
file 4xx_i2c.h.

Also the 4xx i2c reset procedure is reworked since I experienced
some problems with the first access on the 440SPe Katmai board.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:27:08 +01:00
Stefan Roese
7372ca6822 [PATCH] Correctly display PCI arbiter en-/disabled on some 4xx boards
Previously the strapping DCR/SDR was read to determine if the internal PCI
arbiter is enabled or not. This strapping bit can be overridden, so now
the current status is read from the correct DCR/SDR register.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-02 12:44:22 +01:00
Stefan Roese
2902fadade [PATCH] Update 440EPx/440GRx cpu detection
Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-31 16:56:10 +01:00
Wolfgang Denk
15e5025a73 Merge with /home/hs/SC3/u-boot-dev 2007-01-19 12:06:32 +01:00
Heiko Schocher
cb4820725e [PATCH] Fix: Compilerwarnings for SC3 board.
The EBC Configuration Register is now by CFG_EBC_CFG definable
             Added JFFS2 support for the SC3 board.

Signed-off-by: Heiko Schocher <hs@denx.de>
2007-01-18 11:28:51 +01:00
Stefan Roese
5fb692cae5 [PATCH] Add support for AMCC Taishan PPC440GX eval board
Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-18 10:25:34 +01:00
Wolfgang Denk
f11033e739 Merge with /home/hs/SC3/u-boot
Some code cleanup.
2007-01-15 13:41:04 +01:00
Stefan Roese
5a5c56986a [PATCH] Fix 440SPe rev B detection from previous patch
Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-15 09:46:29 +01:00
Stefan Roese
95981778cf [PATCH] Update 440SP(e) cpu revisions
Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-13 08:01:03 +01:00
Heiko Schocher
ca43ba18e9 Added support for the SOLIDCARD III board from Eurodesign
Signed-off-by: Heiko Schocher <hs@denx.de>
2007-01-11 15:44:44 +01:00
Stefan Roese
f07ae7a9da [PATCH] 44x: Fix problem with DDR controller setup (refresh rate)
This patch fixes a problem with an incorrect setup for the refresh
timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-06 15:58:09 +01:00
Stefan Roese
0238898382 [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board
This code will optimize the DDR2 controller setup on a board specific
basis.

Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05 10:38:05 +01:00
Wolfgang Denk
bc5556d62b Merge with /home/hs/TQ/u-boot-dev 2006-12-24 01:30:04 +01:00
Heiko Schocher
fa23044564 Added support for the TQM8272 board from TQ
Signed-off-by: Heiko Schocher <hs@denx.de>
2006-12-21 17:17:02 +01:00
Stefan Roese
e732faec95 [PATCH] PPC4xx: 440SP Rev. C detection added
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-28 16:09:24 +01:00
Wolfgang Denk
d2c83f5493 Merge with /home/sr/git/u-boot/denx-alpr-merge-test 2006-11-27 23:11:18 +01:00
Stefan Roese
f6e495f54c [PATCH] 4xx_enet.c: Correct the setting of zmiifer register
Patch below corrects the setting of the zmiifer register, it was
overwritting the register rather than ORing the settings.

Signed-off-by: Neil Wilson <NWilson@airspan.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-27 17:43:25 +01:00
Wolfgang Denk
83dc830b16 Merge with /home/mk/git/u-boot-generic_ohci#generic_ohci 2006-11-27 16:52:20 +01:00
Stefan Roese
1729b92cde [PATCH] 4xx: Fix problem with board specific reset code (now for real)
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-27 14:52:04 +01:00
Stefan Roese
1f94d162e2 [PATCH] 4xx: Fix problem with board specific reset code
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-27 14:48:41 +01:00
Stefan Roese
ec0c2ec725 [PATCH] Remove testing 4xx enet PHY setup
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-27 14:46:06 +01:00
Stefan Roese
1c2ce22620 [PATCH] Update Prodrive ALPR board support (440GX)
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-27 14:12:17 +01:00
Stefan Roese
48c7d6dba9 Merge with /home/stefan/git/u-boot/denx 2006-11-27 14:11:22 +01:00
Markus Klotzbuecher
53e336e9ff Modified the mpc5xxx and the ppc4xx cpu to use the generic OHCI driver
and adapted board configs TQM5200 and yosemite accordingly. This commit
also makes the maximum number of root hub ports configurable 
(CFG_USB_OHCI_MAX_ROOT_PORTS).
2006-11-27 11:43:09 +01:00
Stefan Roese
2053283304 [PATCH] PPC4xx start.S: Fix for processor errata
Fixed cpu/ppc4xx/start.S for 440EPx Errata: further corrects PPC440EPx
errata 1.12: 440_33 by moving patch up in code.

Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-22 13:20:50 +01:00
Stefan Roese
dfc8a9ee00 Merge with /home/stefan/git/u-boot/denx 2006-11-10 07:48:47 +01:00
Stefan Roese
7ade0c634a Fix bug in PPC440 NAND driver cpu/ppc4xx/ndfc.c
Patch by Stefan Roese, 24 Oct 2006
2006-10-24 18:13:43 +02:00
Wolfgang Denk
ba999c531e Cleanup compile warnings. Prepare for release 1.1.5 2006-10-20 17:54:33 +02:00
Stefan Roese
43a2b0e76a Add board/cpu specific NAND chip select function to 440 NDFC
Based on idea and implementation from Jeff Mann
Patch by Stefan Roese, 20 Oct 2006
2006-10-20 15:17:55 +02:00
Stefan Roese
edf0b54338 Make 4xx bootup message shorter on 440EPx/GRx platforms
Patch by Stefan Roese, 18 Oct 2006
2006-10-18 16:00:43 +02:00
Stefan Roese
d7762337cb * PPC405EP: Add support for board configuration of CPC0_PCI register
This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
Patch by Tolunay Orkun, 07 Apr 2006
2006-10-12 20:09:31 +02:00
Stefan Roese
e0a46554c3 * PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.
- Add configuration of Open Drain GPIO Output selection
  - Add configuration of initial value of GPIO output pins
Patch by Tolunay Orkun, 07 Apr 2006
2006-10-12 20:09:27 +02:00
Wolfgang Denk
2b208f5308 Move "ar" flags to config.mk to allow for silent "make -s"
Based on patch by Mike Frysinger, 20 Jun 2006
2006-10-09 01:02:05 +02:00
Wolfgang Denk
511d0c72b8 Coding style cleanup 2006-10-09 00:42:01 +02:00
Stefan Roese
f3443867e9 Add CONFIG_BOARD_RESET to configure board specific reset function
Patch by Stefan Roese, 07 Oct 2006
2006-10-07 11:30:52 +02:00
Stefan Roese
64cd52efd1 Merge with /home/stefan/git/u-boot/denx 2006-09-18 10:48:03 +02:00
Stefan Roese
854bc8da75 Add support for AMCC Rainier PPX440GRx eval board
Patch by Stefan Roese, 13 Sep 2006
2006-09-13 13:56:49 +02:00
Stefan Roese
2d658967e1 Fix build problem cpu/ppc4xx/ndfc.c
Patch by Stefan Roese, 07 Sep 2006
2006-09-07 13:09:53 +02:00
Stefan Roese
887e2ec9ec Add support for AMCC Sequoia PPC440EPx eval board
- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
  in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
  please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
  in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006
2006-09-07 11:51:23 +02:00
Wolfgang Denk
6741ae92f3 Merge with /home/m8/git/u-boot 2006-09-04 01:03:57 +02:00
Marian Balakowicz
f93286397e Add support for a saving build objects in a separate directory.
Modifications are based on the linux kernel approach and
support two use cases:

  1) Add O= to the make command line
  'make O=/tmp/build all'

  2) Set environement variable BUILD_DIR to point to the desired location
  'export BUILD_DIR=/tmp/build'
  'make'

The second approach can also be used with a MAKEALL script
'export BUILD_DIR=/tmp/build'
'./MAKEALL'

Command line 'O=' setting overrides BUILD_DIR environent variable.

When none of the above methods is used the local build is performed and
the object files are placed in the source directory.
2006-09-01 19:49:50 +02:00
Stefan Roese
2b393b0f0a PCIe endpoint support for AMCC Yucca 440SPe board
Patch by Tirumala R Marri, 26 Aug 2006
2006-08-29 08:05:15 +02:00
Wolfgang Denk
16850919ff Code cleanup 2006-08-27 18:10:01 +02:00
Stefan Roese
899620c2d6 Add initial support for the ALPR board from Prodrive
NAND needs some additional testing
Patch by Heiko Schocher, 15 Aug 2006
2006-08-15 14:22:35 +02:00
Wolfgang Denk
7213859d11 Merge with /home/raj/git/u-boot 2006-08-11 18:19:53 +02:00
Rafal Jaworowski
36b904a7fd Fix PCI-Express on PPC440SPe rev. A. 2006-08-11 12:35:52 +02:00
Wolfgang Denk
d10afb3916 Merge with /home/raj/git/u-boot 2006-08-10 15:40:49 +02:00
Rafal Jaworowski
692519b1ed Add support for PCI-Express on PPC440SPe (Yucca board). 2006-08-10 12:43:17 +02:00
Stefan Roese
a2c95a7224 PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
2006-07-28 18:34:58 +02:00
Wolfgang Denk
b9365a26a1 Code cleanup 2006-07-21 11:56:05 +02:00
Wolfgang Denk
b87dfd2854 Add support for TB5200 board
The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006

Some code cleanup
2006-07-19 13:50:38 +02:00
Marian Balakowicz
edd6cf20e1 Fix timer problems on AMCC yucca board.
Set Timer Clock Select to use CPU clock as a timer input source.
2006-07-06 21:17:24 +02:00
Marian Balakowicz
fbb0b559ae Add system memory to the PCI region list for AMCC PPC44x CPUs.
Enabled it for Yucca board.
2006-07-04 00:55:47 +02:00
Marian Balakowicz
fe84b48a94 Cleanup config file and bootup output for Yucca board. 2006-07-03 23:42:36 +02:00
Marian Balakowicz
bba6837732 Fix CONFIG_440_GX define usage. 2006-06-30 18:35:04 +02:00
Marian Balakowicz
f6e5739a68 Merge: Add support for AMCC 440SPe CPU based eval board (Yucca). 2006-06-30 18:19:42 +02:00
Marian Balakowicz
6c5879f380 Add support for AMCC 440SPe CPU based eval board (Yucca). 2006-06-30 16:30:46 +02:00
Stefan Roese
ed4633c93a Minor cleanup for PCS440EP board
Patch by Stefan Roese, 13 Jun 2006
2006-06-13 18:55:07 +02:00
Stefan Roese
a4c8d1389f Add support for PCS440EP board
Patch by Stefan Roese, 02 Jun 2006
2006-06-02 16:20:36 +02:00
Stefan Roese
5770a1e488 Fix problem in PVR detection for 440GR
Patch by Stefan Roese, 18 May 2006
2006-05-18 19:21:53 +02:00
Stefan Roese
512f8d5d78 Add support for AMCC 440EP Rev C and 440GR Rev B
Patch by John Otken, 08 May 2006
2006-05-10 14:10:41 +02:00
Wolfgang Denk
cf48eb9abd Some code cleanup 2006-04-16 10:51:58 +02:00
Wolfgang Denk
197b049b8b Merge with /home/sr/git/u-boot/4xx-sdram 2006-04-05 23:55:15 +02:00
Wolfgang Denk
d87080b721 GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
Stefan Roese
62534beb2f Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
405 SDRAM: - The SDRAM parameters can now be defined in the board
             config file and the 405 SDRAM controller values will
             be calculated upon bootup (see PPChameleonEVB).
             When those settings are not defined in the board
             config file, the register setup will be as it is now,
             so this implementation should not break any current
             design using this code.

             Thanks to Andrea Marson from DAVE for this patch.

440 DDR:   - Added function sdram_tr1_set to auto calculate the
             TR1 value for the DDR.
           - Added ECC support (see p3p440).

Patch by Stefan Roese, 17 Mar 2006
2006-03-31 14:32:07 +02:00