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Merge with /home/stefan/git/u-boot/zeus

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This commit is contained in:
Stefan Roese 2007-08-14 15:00:42 +02:00
commit 34886bbea2
32 changed files with 4149 additions and 43 deletions
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2
MAINTAINERS
View file

@ -253,6 +253,7 @@ Tolunay Orkun <torkun@nextio.com>
John Otken <jotken@softadvances.com>
luan PPC440SP
taihu PPC405EP
Keith Outwater <Keith_Outwater@mvis.com>
@ -297,6 +298,7 @@ Stefan Roese <sr@denx.de>
walnut PPC405GP
yellowstone PPC440GR
yosemite PPC440EP
zeus PPC405EP
P3M750 PPC750FX/GX/GL

7
MAKEALL
View file

@ -89,9 +89,10 @@ LIST_4xx=" \
OCRTC ORSG p3p440 PCI405 \
pcs440ep PIP405 PLU405 PMC405 \
PPChameleonEVB sbc405 sc3 sequoia \
sequoia_nand taishan VOH405 VOM405 \
W7OLMC W7OLMG walnut WUH405 \
XPEDITE1K yellowstone yosemite yucca \
sequoia_nand taihu taishan VOH405 \
VOM405 W7OLMC W7OLMG walnut \
WUH405 XPEDITE1K yellowstone yosemite \
yucca zeus \
"
#########################################################################

6
Makefile
View file

@ -1260,6 +1260,9 @@ rainier_nand_config: unconfig
sc3_config:unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3
taihu_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
taishan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
@ -1297,6 +1300,9 @@ yellowstone_config: unconfig
yucca_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
zeus_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus
#########################################################################
## MPC8220 Systems
#########################################################################

13
board/amcc/bubinga/bubinga.c
View file

@ -20,10 +20,12 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
long int spd_sdram(void);
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
long int spd_sdram(void);
int board_early_init_f(void)
{
@ -34,6 +36,15 @@ int board_early_init_f(void)
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/*
* Configure CPC0_PCI to enable PerWE as output
* and enable the internal PCI arbiter if selected
*/
if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
else
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
return 0;
}

49
board/amcc/taihu/Makefile Normal file
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@ -0,0 +1,49 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o lcd.o update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

24
board/amcc/taihu/config.mk Normal file
View file

@ -0,0 +1,24 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000

1083
board/amcc/taihu/flash.c Normal file
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File diff suppressed because it is too large Load diff

257
board/amcc/taihu/lcd.c Normal file
View file

@ -0,0 +1,257 @@
/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/gpio.h>
#define LCD_CMD_ADDR 0x50100002
#define LCD_DATA_ADDR 0x50100003
#define LCD_BLK_CTRL CPLD_REG1_ADDR
static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
static int addr_flag = 0x80;
static void lcd_bl_ctrl(char val)
{
out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
}
static void lcd_putc(int val)
{
int i = 100;
char addr;
while (i--) {
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
udelay(50);
break;
}
udelay(50);
}
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
printf("LCD is busy\n");
return;
}
addr = in_8((u8 *) LCD_CMD_ADDR);
udelay(50);
if ((addr != 0) && (addr % 0x10 == 0)) {
addr_flag ^= 0x40;
out_8((u8 *) LCD_CMD_ADDR, addr_flag);
}
udelay(50);
out_8((u8 *) LCD_DATA_ADDR, val);
udelay(50);
}
static void lcd_puts(char *s)
{
char *p = s;
int i = 100;
while (i--) {
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
udelay(50);
break;
}
udelay(50);
}
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
printf("LCD is busy\n");
return;
}
while (*p)
lcd_putc(*p++);
}
static void lcd_put_logo(void)
{
int i = 100;
char *p = amcc_logo;
while (i--) {
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
udelay(50);
break;
}
udelay(50);
}
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
printf("LCD is busy\n");
return;
}
out_8((u8 *) LCD_CMD_ADDR, 0x80);
while (*p)
lcd_putc(*p++);
}
int lcd_init(void)
{
puts("LCD: ");
out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
udelay(50);
out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
udelay(50);
out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
udelay(2000);
out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
udelay(50);
lcd_bl_ctrl(0x02); /* set backlight on */
lcd_put_logo();
puts("ready\n");
return 0;
}
static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
out_8((u8 *) LCD_CMD_ADDR, 0x01);
udelay(2000);
return 0;
}
static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
printf("%s", cmdtp->usage);
return 1;
}
lcd_puts(argv[1]);
return 0;
}
static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
printf("%s", cmdtp->usage);
return 1;
}
lcd_putc((char)argv[1][0]);
return 0;
}
static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong count;
ulong dir;
char cur_addr;
if (argc < 3) {
printf("%s", cmdtp->usage);
return 1;
}
count = simple_strtoul(argv[1], NULL, 16);
if (count > 31) {
printf("unable to shift > 0x20\n");
count = 0;
}
dir = simple_strtoul(argv[2], NULL, 16);
cur_addr = in_8((u8 *) LCD_CMD_ADDR);
udelay(50);
if (dir == 0x0) {
if (addr_flag == 0x80) {
if (count >= (cur_addr & 0xf)) {
out_8((u8 *) LCD_CMD_ADDR, 0x80);
udelay(50);
count = 0;
}
} else {
if (count >= ((cur_addr & 0x0f) + 0x0f)) {
out_8((u8 *) LCD_CMD_ADDR, 0x80);
addr_flag = 0x80;
udelay(50);
count = 0x0;
} else if (count >= ( cur_addr & 0xf)) {
count -= cur_addr & 0xf ;
out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
addr_flag = 0x80;
udelay(50);
}
}
} else {
if (addr_flag == 0x80) {
if (count >= (0x1f - (cur_addr & 0xf))) {
count = 0x0;
addr_flag = 0xc0;
out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
udelay(50);
} else if ((count + (cur_addr & 0xf ))>= 0x0f) {
count = count + (cur_addr & 0xf) - 0x0f;
addr_flag = 0xc0;
out_8((u8 *) LCD_CMD_ADDR, 0xc0);
udelay(50);
}
} else if ((count + (cur_addr & 0xf )) >= 0x0f) {
count = 0x0;
out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
udelay(50);
}
}
while (count--) {
if (dir == 0)
out_8((u8 *) LCD_CMD_ADDR, 0x10);
else
out_8((u8 *) LCD_CMD_ADDR, 0x14);
udelay(50);
}
return 0;
}
U_BOOT_CMD(
lcd_cls, 1, 1, do_lcd_clear,
"lcd_cls - lcd clear display\n",
NULL
);
U_BOOT_CMD(
lcd_puts, 2, 1, do_lcd_puts,
"lcd_puts - display string on lcd\n",
"<string> - <string> to be displayed\n"
);
U_BOOT_CMD(
lcd_putc, 2, 1, do_lcd_putc,
"lcd_putc - display char on lcd\n",
"<char> - <char> to be displayed\n"
);
U_BOOT_CMD(
lcd_cur, 3, 1, do_lcd_cur,
"lcd_cur - shift cursor on lcd\n",
"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
" <count> - 0..31\n"
" <dir> - 0=backward 1=forward\n"
);

240
board/amcc/taihu/taihu.c Normal file
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@ -0,0 +1,240 @@
/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2005-2007
* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spi.h>
#include <asm/gpio.h>
extern int lcd_init(void);
/*
* board_early_init_f
*/
int board_early_init_f(void)
{
lcd_init();
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
mtebc(pb3cr, CFG_EBC_PB3CR);
/*
* Configure CPC0_PCI to enable PerWE as output
* and enable the internal PCI arbiter
*/
mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return 0;
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
}
static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
{
char stat;
int i;
stat = in_8((u8 *) CPLD_REG0_ADDR);
printf("SW2 status: ");
for (i=0; i<4; i++) /* 4-position */
printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
printf("\n");
return 0;
}
U_BOOT_CMD (
sw2_stat, 1, 1, do_sw_stat,
"sw2_stat - show status of switch 2\n",
NULL
);
static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
{
int led_no;
if (argc != 3) {
printf("%s", cmd_tp->usage);
return -1;
}
led_no = simple_strtoul(argv[1], NULL, 16);
if (led_no != 1 && led_no != 2) {
printf("%s", cmd_tp->usage);
return -1;
}
if (strcmp(argv[2],"off") == 0x0) {
if (led_no == 1)
gpio_write_bit(30, 1);
else
gpio_write_bit(31, 1);
} else if (strcmp(argv[2],"on") == 0x0) {
if (led_no == 1)
gpio_write_bit(30, 0);
else
gpio_write_bit(31, 0);
} else {
printf("%s", cmd_tp->usage);
return -1;
}
return 0;
}
U_BOOT_CMD (
led_ctl, 3, 1, do_led_ctl,
"led_ctl - make led 1 or 2 on or off\n",
"<led_no> <on/off> - make led <led_no> on/off,\n"
"\tled_no is 1 or 2\t"
);
#define SPI_CS_GPIO0 0
#define SPI_SCLK_GPIO14 14
#define SPI_DIN_GPIO15 15
#define SPI_DOUT_GPIO16 16
void spi_scl(int bit)
{
gpio_write_bit(SPI_SCLK_GPIO14, bit);
}
void spi_sda(int bit)
{
gpio_write_bit(SPI_DOUT_GPIO16, bit);
}
unsigned char spi_read(void)
{
return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
}
void taihu_spi_chipsel(int cs)
{
gpio_write_bit(SPI_CS_GPIO0, cs);
}
spi_chipsel_type spi_chipsel[]= {
taihu_spi_chipsel
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
#ifdef CONFIG_PCI
static unsigned char int_lines[32] = {
29, 30, 27, 28, 29, 30, 25, 27,
29, 30, 27, 28, 29, 30, 27, 28,
29, 30, 27, 28, 29, 30, 27, 28,
29, 30, 27, 28, 29, 30, 27, 28};
static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}
int pci_pre_init(struct pci_controller *hose)
{
hose->fixup_irq = taihu_pci_fixup_irq;
return 1;
}
#endif /* CONFIG_PCI */
#ifdef CFG_DRAM_TEST
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
unsigned long msr;
unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
msr = mfmsr();
mtmsr(msr & ~(MSR_EE));
for (k = 0; k < total_kbytes ;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0)
printf("%3d MB\r", k / 1024);
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
mtmsr(msr);
return 0;
}
#endif /* CFG_DRAM_TEST */

150
board/amcc/taihu/u-boot.lds Normal file
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@ -0,0 +1,150 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

132
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/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <i2c.h>
#define PCI_M66EN 0x10
static uchar buf_33[] =
{
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
0x00,
0x00,
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
0x00,
0x00,
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
0x00,
0x00,
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
0x00,
0x00,
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
0x14,
0x00, /* 0x0f~0x10:device id 0x0000*/
0x00,
0x00, /* 0x11:revision 0x00 */
0x00, /* 0x12~0x14:class 0x000000 */
0x00,
0x00,
0x10, /* 0x15~0x16:subsystem vendor id */
0xe8,
0x00, /* 0x17~0x18:subsystem device id */
0x00,
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
0xbe, /* 0x1d: tun[24-31]=0xbe */
0x00,
0x00
};
static uchar buf_66[] =
{
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
0x00,
0x00,
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
0x00,
0x00,
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
0x00,
0x00,
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
0x00,
0x00,
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
0x14,
0x00, /* 0x0f~0x10:device id 0x0000*/
0x00,
0x00, /* 0x11:revision 0x00 */
0x00, /* 0x12~0x14:class 0x000000 */
0x00,
0x00,
0x10, /* 0x15~0x16:subsystem vendor id */
0xe8,
0x00, /* 0x17~0x18:subsystem device id */
0x00,
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
0xbe, /* 0x1d: tun[24-31]=0xbe */
0x00,
0x00
};
static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[])
{
ulong len = 0x20;
uchar chip = CFG_I2C_EEPROM_ADDR;
uchar *pbuf;
uchar base;
int i;
if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
pbuf = buf_33;
base = 0x00;
} else {
pbuf = buf_66;
base = 0x40;
}
for (i = 0; i< len; i++, base++) {
if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
printf("i2c_write fail\n");
return 1;
}
udelay(11000);
}
return 0;
}
U_BOOT_CMD (
update_boot_eeprom, 1, 1, update_boot_eeprom,
"update_boot_eeprom - update boot eeprom content\n",
NULL
);

51
board/zeus/Makefile Normal file
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#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o update.o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

24
board/zeus/config.mk Normal file
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#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000

133
board/zeus/u-boot.lds Normal file
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

105
board/zeus/update.c Normal file
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/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <i2c.h>
#if defined(CONFIG_ZEUS)
u8 buf_zeus_ce[] = {
/*00 01 02 03 04 05 06 07 */
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/*08 09 0a 0b 0c 0d 0e 0f */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/*10 11 12 13 14 15 16 17 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/*18 19 1a 1b 1c 1d 1e 1f */
0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
u8 buf_zeus_pe[] = {
/* CPU_CLOCK_DIV 1 = 00
CPU_PLB_FREQ_DIV 3 = 10
OPB_PLB_FREQ_DIV 2 = 01
EBC_PLB_FREQ_DIV 2 = 00
MAL_PLB_FREQ_DIV 1 = 00
PCI_PLB_FRQ_DIV 3 = 10
PLL_PLLOUTA = IS SET
PLL_OPERATING = IS NOT SET
PLL_FDB_MUL 10 = 1010
PLL_FWD_DIV_A 3 = 101
PLL_FWD_DIV_B 3 = 101
TUNE = 0x2be */
/*00 01 02 03 04 05 06 07 */
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/*08 09 0a 0b 0c 0d 0e 0f */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/*10 11 12 13 14 15 16 17 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/*18 19 1a 1b 1c 1d 1e 1f */
0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
static int update_boot_eeprom(void)
{
u32 len = 0x20;
u8 chip = CFG_I2C_EEPROM_ADDR;
u8 *pbuf;
u8 base;
int i;
if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) {
pbuf = buf_zeus_pe;
base = 0x40;
} else {
pbuf = buf_zeus_ce;
base = 0x00;
}
for (i = 0; i < len; i++, base++) {
if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
printf("i2c_write fail\n");
return 1;
}
udelay(11000);
}
return 0;
}
int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
{
return update_boot_eeprom();
}
U_BOOT_CMD (
update_boot_eeprom, 1, 1, do_update_boot_eeprom,
"update_boot_eeprom - update boot eeprom content\n",
NULL
);
#endif

511
board/zeus/zeus.c Normal file
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@ -0,0 +1,511 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <environment.h>
#include <logbuff.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#define REBOOT_MAGIC 0x07081967
#define REBOOT_NOP 0x00000000
#define REBOOT_DO_POST 0x00000001
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern env_t *env_ptr;
extern uchar default_environment[];
ulong flash_get_size(ulong base, int banknum);
void env_crc_update(void);
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
static u32 start_time;
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
/*
* Configure CPC0_PCI to enable PerWE as output
*/
mtdcr(cpc0_pci, CPC0_PCI_SPE);
return 0;
}
int misc_init_r(void)
{
u32 pbcr;
int size_val = 0;
u32 post_magic;
u32 post_val;
post_magic = in_be32((void *)CFG_POST_MAGIC);
post_val = in_be32((void *)CFG_POST_VAL);
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
/*
* Set special bootline bootparameter to pass this POST boot
* mode to Linux to reset the username/password
*/
setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
/*
* Normally don't run POST tests, only when enabled
* via the sw-reset button. So disable further tests
* upon next bootup here.
*/
out_be32((void *)CFG_POST_VAL, REBOOT_NOP);
} else {
/*
* Only run POST when initiated via the sw-reset button mechanism
*/
post_word_store(0);
}
/*
* Get current time
*/
start_time = get_timer(0);
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* adjust flash start and offset */
mfebc(pb0cr, pbcr);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(pb0cr, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
puts("Board: Zeus-");
if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE))
puts("PE");
else
puts("CE");
puts(" of BulletEndPoint");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
/* both LED's off */
gpio_write_bit(CFG_GPIO_LED_RED, 0);
gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
udelay(10000);
/* and on again */
gpio_write_bit(CFG_GPIO_LED_RED, 1);
gpio_write_bit(CFG_GPIO_LED_GREEN, 1);
return (0);
}
static u32 detect_sdram_size(void)
{
u32 val;
u32 size;
mfsdram(mem_mb0cf, val);
size = (4 << 20) << ((val & 0x000e0000) >> 17);
/*
* Check if 2nd bank is enabled too
*/
mfsdram(mem_mb1cf, val);
if (val & 1)
size += (4 << 20) << ((val & 0x000e0000) >> 17);
return size;
}
long int initdram (int board_type)
{
return detect_sdram_size();
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
unsigned long msr;
unsigned long total_kbytes;
total_kbytes = detect_sdram_size();
msr = mfmsr();
mtmsr(msr & ~(MSR_EE));
for (k = 0; k < total_kbytes ;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
mtmsr(msr);
return 0;
}
#endif
static int default_env_var(char *buf, char *var)
{
char *ptr;
char *val;
/*
* Find env variable
*/
ptr = strstr(buf + 4, var);
if (ptr == NULL) {
printf("ERROR: %s not found!\n", var);
return -1;
}
ptr += strlen(var) + 1;
/*
* Now the ethaddr needs to be updated in the "normal"
* environment storage -> redundant flash.
*/
val = ptr;
setenv(var, val);
printf("Updated %s from eeprom to %s!\n", var, val);
return 0;
}
static int restore_default(void)
{
char *buf;
char *buf_save;
u32 crc;
/*
* Unprotect and erase environment area
*/
flash_protect(FLAG_PROTECT_CLEAR,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
flash_sect_erase(CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1);
/*
* Now restore default environment from U-Boot image
* -> ipaddr, serverip...
*/
memset(env_ptr, 0, sizeof(env_t));
memcpy(env_ptr->data, default_environment, ENV_SIZE);
#ifdef CFG_REDUNDAND_ENVIRONMENT
env_ptr->flags = 0xFF;
#endif
env_crc_update();
gd->env_valid = 1;
/*
* Read board specific values from I2C EEPROM
* and set env variables accordingly
* -> ethaddr, eth1addr, serial#
*/
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
(u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
puts("\nError reading EEPROM!\n");
} else {
crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
if (crc != *(u32 *)buf) {
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf);
return -1;
}
default_env_var(buf, "ethaddr");
buf += 8 + 18;
default_env_var(buf, "eth1addr");
buf += 9 + 18;
default_env_var(buf, "serial#");
}
/*
* Finally save updated env variables back to flash
*/
saveenv();
free(buf_save);
return 0;
}
int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *buf;
char *buf_save;
char str[32];
u32 crc;
char var[32];
if (argc < 4) {
puts("ERROR!\n");
return -1;
}
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
memset(buf, 0, FACTORY_RESET_ENV_SIZE);
strcpy(var, "ethaddr");
printf("Setting %s to %s\n", var, argv[1]);
sprintf(str, "%s=%s", var, argv[1]);
strcpy(buf + 4, str);
buf += strlen(str) + 1;
strcpy(var, "eth1addr");
printf("Setting %s to %s\n", var, argv[2]);
sprintf(str, "%s=%s", var, argv[2]);
strcpy(buf + 4, str);
buf += strlen(str) + 1;
strcpy(var, "serial#");
printf("Setting %s to %s\n", var, argv[3]);
sprintf(str, "%s=%s", var, argv[3]);
strcpy(buf + 4, str);
crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
*(u32 *)buf_save = crc;
if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
(u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
puts("\nError writing EEPROM!\n");
return -1;
}
free(buf_save);
return 0;
}
U_BOOT_CMD(
setdef, 4, 1, do_set_default,
"setdef - write board-specific values to EEPROM (ethaddr...)\n",
"ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n"
);
static inline int sw_reset_pressed(void)
{
return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET));
}
int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
{
int delta;
int count = 0;
int post = 0;
int factory_reset = 0;
if (!sw_reset_pressed()) {
printf("SW-Reset already high (Button released)\n");
printf("-> No action taken!\n");
return 0;
}
printf("Waiting for SW-Reset button to be released.");
while (1) {
delta = get_timer(start_time);
if (!sw_reset_pressed())
break;
if ((delta > CFG_TIME_POST) && !post) {
printf("\nWhen released now, POST tests will be started.");
gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
post = 1;
}
if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) {
printf("\nWhen released now, factory default values"
" will be restored.");
gpio_write_bit(CFG_GPIO_LED_RED, 0);
factory_reset = 1;
}
udelay(1000);
if (!(count++ % 1000))
printf(".");
}
printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
if (delta > CFG_TIME_FACTORY_RESET) {
printf("Starting factory reset value restoration...\n");
/*
* Restore default setting
*/
restore_default();
/*
* Reset the board for default to become valid
*/
do_reset(NULL, 0, 0, NULL);
return 0;
}
if (delta > CFG_TIME_POST) {
printf("Starting POST configuration...\n");
/*
* Enable POST upon next bootup
*/
out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC);
out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST);
post_bootmode_init();
/*
* Reset the logbuffer for a clean start
*/
logbuff_reset();
do_reset(NULL, 0, 0, NULL);
return 0;
}
return 0;
}
U_BOOT_CMD (
chkreset, 1, 1, do_chkreset,
"chkreset- Check for status of SW-reset button and act accordingly\n",
NULL
);
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
u32 post_magic;
u32 post_val;
post_magic = in_be32((void *)CFG_POST_MAGIC);
post_val = in_be32((void *)CFG_POST_VAL);
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
return 1;
else
return 0;
}
#endif /* CONFIG_POST */

2
common/soft_spi.c
View file

@ -79,7 +79,9 @@ void spi_init (void)
*/
int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
{
#ifdef CFG_IMMR
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
uchar tmpdin = 0;
uchar tmpdout = 0;
int j;

2
cpu/ppc4xx/gpio.c
View file

@ -186,6 +186,7 @@ void gpio_set_chip_configuration(void)
out32(GPIO0_TCR, reg);
}
#ifdef GPIO1
if (gpio_core == GPIO1) {
/*
* Setup output value
@ -203,6 +204,7 @@ void gpio_set_chip_configuration(void)
reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
out32(GPIO1_TCR, reg);
}
#endif /* GPIO1 */
reg = in32(GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));

32
cpu/ppc4xx/sdram.c
View file

@ -187,14 +187,14 @@ void sdram_init(void)
/*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
mtsdram(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
mtsdram0(mem_mb0cf, mb0cf[i].reg);
mtsdram0(mem_sdtr1, sdtr1);
mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
mtsdram(mem_mb0cf, mb0cf[i].reg);
mtsdram(mem_sdtr1, sdtr1);
mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
@ -203,14 +203,34 @@ void sdram_init(void)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram0(mem_mcopt1, 0x80800000);
mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
/*
* OK, size detected -> all done
* OK, size detected. Enable second bank if
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
mtsdram(mem_mcopt1, 0x00000000);
mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
/*
* Check if 2nd bank is really available.
* If the size not equal to the size of the first
* bank, then disable the 2nd bank completely.
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
mb0cf[i].size) {
mtsdram(mem_mb1cf, 0);
mtsdram(mem_mcopt1, 0);
}
#endif
return;
}
}

2
cpu/ppc4xx/sdram.h
View file

@ -29,8 +29,6 @@
#include <config.h>
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
#define ONE_BILLION 1000000000
struct sdram_conf_s {

61
cpu/ppc4xx/start.S
View file

@ -1870,28 +1870,6 @@ ppc405ep_init:
mtdcr ebccfgd,r3
#endif
#ifndef CFG_CPC0_PCI
li r3,CPC0_PCI_HOST_CFG_EN
#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
! Check FPGA for PCI internal/external arbitration
! If board is set to internal arbitration, update cpc0_pci
!-----------------------------------------------------------------------
*/
addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
ori r5,r5,FPGA_REG1@l
lbz r5,0x0(r5) /* read to get PCI arb selection */
andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
beq ..pci_cfg_set /* if not set, then bypass reg write*/
#endif
ori r3,r3,CPC0_PCI_ARBIT_EN
#else /* CFG_CPC0_PCI */
li r3,CFG_CPC0_PCI
#endif /* CFG_CPC0_PCI */
..pci_cfg_set:
mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
/*
!-----------------------------------------------------------------------
! Check to see if chip is in bypass mode.
@ -1947,11 +1925,50 @@ ppc405ep_init:
..no_pllset:
#endif /* CONFIG_BUBINGA */
#ifdef CONFIG_TAIHU
mfdcr r4, CPC0_BOOT
andi. r5, r4, CPC0_BOOT_SEP@l
bne strap_1 /* serial eeprom present */
addis r5,0,CPLD_REG0_ADDR@h
ori r5,r5,CPLD_REG0_ADDR@l
andi. r5, r5, 0x10
bne _pci_66mhz
#endif /* CONFIG_TAIHU */
#if defined(CONFIG_ZEUS)
mfdcr r4, CPC0_BOOT
andi. r5, r4, CPC0_BOOT_SEP@l
bne strap_1 /* serial eeprom present */
lis r3,0x0000
addi r3,r3,0x3030
lis r4,0x8042
addi r4,r4,0x223e
b 1f
strap_1:
mfdcr r3, CPC0_PLLMR0
mfdcr r4, CPC0_PLLMR1
b 1f
#endif
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
ori r4,r4,PLLMR1_DEFAULT@l /* */
#ifdef CONFIG_TAIHU
b 1f
_pci_66mhz:
addis r3,0,PLLMR0_DEFAULT_PCI66@h
ori r3,r3,PLLMR0_DEFAULT_PCI66@l
addis r4,0,PLLMR1_DEFAULT_PCI66@h
ori r4,r4,PLLMR1_DEFAULT_PCI66@l
b 1f
strap_1:
mfdcr r3, CPC0_PLLMR0
mfdcr r4, CPC0_PLLMR1
#endif /* CONFIG_TAIHU */
1:
b pll_write /* Write the CPC0_PLLMR with new value */
pll_done:

73
doc/README.zeus Normal file
View file

@ -0,0 +1,73 @@
Storage of the board specific values (ethaddr...)
-------------------------------------------------
The board specific environment variables that should be unique
for each individual board, can be stored in the I2C EEPROM. This
will be done from offset 0x80 with the length of 0x80 bytes. The
following command can be used to store the values here:
=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
ethaddr eth1addr serial#
Now those 3 values are stored into the I2C EEPROM. A CRC is added
to make sure that the values get not corrupted.
SW-Reset Pushbutton handling:
-----------------------------
The SW-reset push button is connected to a GPIO input too. This
way U-Boot can "see" how long the SW-reset was pressed, and a
specific action can be taken. Two different actions are supported:
a) Release after more than 5 seconds and less then 10 seconds:
-> Run POST
Please note, that the POST test will take a while (approx. 1 min
on the 128MByte board). This is mainly due to the system memory
test.
b) Release after more than 10 seconds:
-> Restore factory default settings
The factory default values are restored. The default environment
variables are restored (ipaddr, serverip...) and the board
specific values (ethaddr, eth1addr and serial#) are restored
to the environment from the I2C EEPROM. Also a bootline parameter
is added to the Linux bootline to signal the Linux kernel upon
the next startup, that the factory defaults should be restored.
The command to check this sw-reset status and act accordingly is
=> chkreset
This command is added to the default "bootcmd", so that it is called
automatically upon startup.
Also, the 2 LED's are used to indicate the current status of this
command (time passed since pushing the button). When the POST test
will be run, the green LED will be switched off, and when the
factory restore will be initiated, the reg LED will be switched off.
Loggin of POST results:
-----------------------
The results of the POST tests are logged in a logbuffer located at the end
of the onboard memory. It can be accessed with the U-Boot command "log":
=> log show
<4>POST memory PASSED
<4>POST cache PASSED
<4>POST cpu PASSED
<4>POST uart PASSED
<4>POST ethernet PASSED
The DENX Linux kernel tree has support for this log buffer included. Exactly
this buffer is used for logging of all kernel messages too. By enabling the
compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
can access the U-Boot log messages from Linux too.
2007-08-10, Stefan Roese <sr@denx.de>

2
dtt/Makefile
View file

@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdtt.a
COBJS = lm75.o ds1621.o adm1021.o lm81.o
COBJS = lm75.o ds1621.o adm1021.o lm81.o ds1775.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

156
dtt/ds1775.c Normal file
View file

@ -0,0 +1,156 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Dallas Semiconductor's DS1775 Digital Thermometer and Thermostat
*/
#include <common.h>
#ifdef CONFIG_DTT_DS1775
#include <i2c.h>
#include <dtt.h>
#define DTT_I2C_DEV_CODE 0x49 /* Dallas Semi's DS1775 device code */
int dtt_read(int sensor, int reg)
{
int dlen;
uchar data[2];
/*
* Calculate sensor address and command
*/
sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1775 */
/*
* Prepare to handle 2 byte result
*/
if ((reg == DTT_READ_TEMP) ||
(reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST))
dlen = 2;
else
dlen = 1;
/*
* Now try to read the register
*/
if (i2c_read(sensor, reg, 1, data, dlen) != 0)
return 1;
/*
* Handle 2 byte result
*/
if (dlen == 2)
return ((int)((short)data[1] + (((short)data[0]) << 8)));
return (int) data[0];
}
int dtt_write(int sensor, int reg, int val)
{
int dlen;
uchar data[2];
/*
* Calculate sensor address and register
*/
sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
/*
* Handle various data sizes
*/
if ((reg == DTT_READ_TEMP) ||
(reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) {
dlen = 2;
data[0] = (char)((val >> 8) & 0xff); /* MSB first */
data[1] = (char)(val & 0xff);
} else {
dlen = 1;
data[0] = (char)(val & 0xff);
}
/*
* Write value to device
*/
if (i2c_write(sensor, reg, 1, data, dlen) != 0)
return 1;
return 0;
}
static int _dtt_init(int sensor)
{
int val;
/*
* Setup High Temp
*/
val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80;
if (dtt_write(sensor, DTT_TEMP_OS, val) != 0)
return 1;
udelay(50000); /* Max 50ms */
/*
* Setup Low Temp - hysteresis
*/
val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0)
return 1;
udelay(50000); /* Max 50ms */
/*
* Setup configuraton register
*
* Fault Tolerance limits 4, Thermometer resolution bits is 9,
* Polarity = Active Low,continuous conversion mode, Thermostat
* mode is interrupt mode
*/
val = 0xa;
if (dtt_write(sensor, DTT_CONFIG, val) != 0)
return 1;
udelay(50000); /* Max 50ms */
return 0;
}
int dtt_init (void)
{
int i;
unsigned char sensors[] = CONFIG_DTT_SENSORS;
for (i = 0; i < sizeof(sensors); i++) {
if (_dtt_init(sensors[i]) != 0)
printf("DTT%d: FAILED\n", i+1);
else
printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
}
return (0);
}
int dtt_get_temp(int sensor)
{
return (dtt_read(sensor, DTT_READ_TEMP) / 256);
}
#endif /* CONFIG_DTT_DS1775 */

473
include/configs/taihu.h Normal file
View file

@ -0,0 +1,473 @@
/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2005-2007
* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_TAIHU 1 /* on a taihu board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_NO_SERIAL_EEPROM
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM
/*
!-------------------------------------------------------------------------------
! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
! assuming a 33MHz input clock to the 405EP from the C9531.
!-------------------------------------------------------------------------------
*/
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
PLL_MALDIV_1 | PLL_PCIDIV_3)
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
PLL_MALDIV_1 | PLL_PCIDIV_1)
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
#endif
/*----------------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootfile=/tftpboot/taihu/uImage\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
"load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
"update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
"cp.b 200000 FFFC0000 40000\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0x14 /* PHY address */
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_PHY_RESET 1
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_CACHE | \
CFG_CMD_DHCP | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_SPI | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
#define CFG_SDRAM_BANKS 2
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
/* SDRAM timings used in datasheet */
#define CFG_SDRAM_CL 3 /* CAS latency */
#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
/*
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
* The Linux BASE_BAUD define should match this configuration.
* baseBaud = cpuClock/(uartDivisor*16)
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
#define CONFIG_UART1_CONSOLE 1
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#endif
#define CONFIG_SOFT_SPI
#define SPI_SCL spi_scl
#define SPI_SDA spi_sda
#define SPI_READ spi_read()
#define SPI_DELAY udelay(2)
#ifndef __ASSEMBLY__
void spi_scl(int);
void spi_sda(int);
unsigned char spi_read(void);
#endif
/* standard dtt sensor configuration */
#define CONFIG_DTT_DS1775 1
#define CONFIG_DTT_SENSORS { 0 }
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
#define CONFIG_EEPRO100 1
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_ADDR0 0x555
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned short
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* NVRAM organization
*/
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/
#endif
/*-----------------------------------------------------------------------
* PPC405 GPIO Configuration
*/
#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
} \
}
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x1000
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (Flash/SRAM) initialization */
#define CFG_EBC_PB0AP 0x03815600
#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (NVRAM/RTC) initialization */
#define CFG_EBC_PB1AP 0x05815600
#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
/* Memory Bank 2 (USB device) initialization */
#define CFG_EBC_PB2AP 0x03016600
#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (LCM and D-flip-flop) initialization */
#define CFG_EBC_PB3AP 0x158FF600
#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 4 (not install) initialization */
#define CFG_EBC_PB4AP 0x158FF600
#define CFG_EBC_PB4CR 0x5021A000
/*-----------------------------------------------------------------------
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
* GPIO0[1-9] - Instruction trace outputs
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
* GPIO0[24-27] - UART0 control signal inputs/outputs
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */
#define CFG_GPIO0_OSRL 0x00000110
#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */
#define CFG_GPIO0_ISR1L 0x15545440
#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */
#define CFG_GPIO0_TSRL 0x00000000
#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */
#define CFG_GPIO0_ODR 0x00000000 /* open drain */
#define GPIO0 0 /* GPIO controller 0 */
/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */
#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE)
#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE)
#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE)
#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE)
#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE)
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */
#define GPIO_IS2(x) (x+GPIOx_IS1L)
#define GPIO_IS3(x) (x+GPIOx_IS1L)
#define CPLD_REG0_ADDR 0x50100000
#define CPLD_REG1_ADDR 0x50100001
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* zeus.h - configuration for Zeus board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_ZEUS 1 /* Board is Zeus */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EP 1 /* Specifc 405EP support*/
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0x01 /* PHY address */
#define CONFIG_HAS_ETH1 1
#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_PHY_RESET 1
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_CACHE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_LOG | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PING | \
CFG_CMD_REGINFO)
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_CACHE | \
CFG_POST_UART | \
CFG_POST_ETHER)
#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
/* Define here the base-addresses of the UARTs to test in POST */
#define CFG_POST_UART_TABLE {UART0_BASE}
#define CONFIG_LOGBUFFER
#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------
* SDRAM
*----------------------------------------------------------------------*/
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
/* SDRAM timings used in datasheet */
#define CFG_SDRAM_CL 3 /* CAS latency */
#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CFG_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/* these are for the ST M24C02 2kbit serial i2c eeprom */
#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* The layout of the I2C EEPROM, used for bootstrap setup and for board-
* specific values, like ethaddr... that can be restored via the sw-reset
* button
*/
#define FACTORY_RESET_I2C_EEPROM 0x50
#define FACTORY_RESET_ENV_OFFS 0x80
#define FACTORY_RESET_ENV_SIZE 0x80
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF000000
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x1000
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/* reserve some memory for POST and BOOT limit info */
#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
/* extra data in OCM */
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (Flash 16M) initialization */
#define CFG_EBC_PB0AP 0x05815600
#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
* GPIO0[1-9] - Instruction trace outputs
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
* GPIO0[24-27] - UART0 control signal inputs/outputs
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */
#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
#define CFG_GPIO0_TSRH 0x00000000
#define CFG_GPIO0_TSRL 0x00000000
#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
#define CFG_GPIO0_ODR 0x00000000
#define CFG_GPIO_SW_RESET 1
#define CFG_GPIO_ZEUS_PE 12
#define CFG_GPIO_LED_RED 22
#define CFG_GPIO_LED_GREEN 23
/* Time in milli-seconds */
#define CFG_TIME_POST 5000
#define CFG_TIME_FACTORY_RESET 10000
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* ENVIRONMENT VARS */
#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
#define CONFIG_IPADDR 192.168.1.10
#define CONFIG_SERVERIP 192.168.1.100
#define CONFIG_GATEWAYIP 192.168.1.100
#define CONFIG_ETHADDR 50:00:00:00:06:00
#define CONFIG_ETH1ADDR 50:00:00:00:06:01
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"logversion=2\0" \
"hostname=zeus\0" \
"netdev=eth0\0" \
"ethact=ppc_4xx_eth0\0" \
"netmask=255.255.255.0\0" \
"ramdisk_size=50000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw" \
" nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw" \
" ramdisk=${ramdisk_size}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0," \
"${baudrate}\0" \
"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
"run nfsargs addip addtty;bootm\0" \
"net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
"tftp ${ramdisk_mem_addr} ${file_fs};" \
"run ramargs addip addtty;" \
"bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
"rootpath=/target_fs/zeus\0" \
"kernel_fl_addr=ff000000\0" \
"kernel_mem_addr=200000\0" \
"ramdisk_fl_addr=ff300000\0" \
"ramdisk_mem_addr=4000000\0" \
"uboot_fl_addr=fffc0000\0" \
"uboot_mem_addr=100000\0" \
"file_uboot=/zeus/u-boot.bin\0" \
"tftp_uboot=tftp 100000 ${file_uboot}\0" \
"update_uboot=protect off fffc0000 ffffffff;" \
"era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
"protect on fffc0000 ffffffff\0" \
"upd_uboot=run tftp_uboot;run update_uboot\0" \
"file_kernel=/zeus/uImage_ba\0" \
"tftp_kernel=tftp 100000 ${file_kernel}\0" \
"update_kernel=protect off ff000000 ff17ffff;" \
"era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
"upd_kernel=run tftp_kernel;run update_kernel\0" \
"file_fs=/zeus/rootfs_ba.img\0" \
"tftp_fs=tftp 100000 ${file_fs}\0" \
"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
"cp.b 100000 ff300000 580000\0" \
"upd_fs=run tftp_fs;run update_fs\0" \
"bootcmd=chkreset;run ramargs addip addtty addmisc;" \
"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
""
#endif /* __CONFIG_H */

8
include/dtt.h
View file

@ -29,6 +29,7 @@
#if defined(CONFIG_DTT_LM75) || \
defined(CONFIG_DTT_DS1621) || \
defined(CONFIG_DTT_DS1775) || \
defined(CONFIG_DTT_LM81) || \
defined(CONFIG_DTT_ADM1021)
@ -78,6 +79,13 @@ extern int dtt_get_temp(int sensor);
#define DTT_CONFIG 0xAC
#endif
#if defined(CONFIG_DTT_DS1775)
#define DTT_READ_TEMP 0x0
#define DTT_CONFIG 0x1
#define DTT_TEMP_HYST 0x2
#define DTT_TEMP_OS 0x3
#endif
#if defined(CONFIG_DTT_ADM1021)
#define DTT_READ_LOC_VALUE 0x00
#define DTT_READ_REM_VALUE 0x01

14
include/ppc405.h
View file

@ -541,6 +541,18 @@
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
PLL_MALDIV_1 | PLL_PCIDIV_3)
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
PLL_MALDIV_1 | PLL_PCIDIV_1)
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
/*
* PLL Voltage Controlled Oscillator (VCO) definitions
@ -1228,6 +1240,8 @@
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
#ifndef __ASSEMBLY__

16
post/cpu/ppc4xx/cache.c
View file

@ -53,14 +53,25 @@ int cache_post_test6 (int tlb, void *p, int size);
static int tlb = -1; /* index to the victim TLB entry */
#ifdef CONFIG_440
static unsigned char testarea[CACHE_POST_SIZE]
__attribute__((__aligned__(CACHE_POST_SIZE)));
#endif
int cache_post_test (int flags)
{
void* virt = (void*)CFG_POST_CACHE_ADDR;
int ints, i, res = 0;
u32 word0;
int ints;
int res = 0;
/*
* All 44x variants deal with cache management differently
* because they have the address translation always enabled.
* The 40x ppc's don't use address translation in U-Boot at all,
* so we have to distinguish here between 40x and 44x.
*/
#ifdef CONFIG_440
int word0, i;
if (tlb < 0) {
/*
@ -83,6 +94,7 @@ int cache_post_test (int flags)
}
}
}
#endif
ints = disable_interrupts ();
WATCHDOG_RESET ();

44
post/cpu/ppc4xx/cache_4xx.S
View file

@ -37,6 +37,13 @@
.text
/*
* All 44x variants deal with cache management differently
* because they have the address translation always enabled.
* The 40x ppc's don't use address translation in U-Boot at all,
* so we have to distinguish here between 40x and 44x.
*/
#ifdef CONFIG_440
/* void cache_post_disable (int tlb)
*/
cache_post_disable:
@ -68,6 +75,43 @@ cache_post_wb:
sync
isync
blr
#else
/* void cache_post_disable (int tlb)
*/
cache_post_disable:
lis r0, 0x0000
ori r0, r0, 0x0000
mtdccr r0
sync
isync
blr
/* void cache_post_wt (int tlb)
*/
cache_post_wt:
lis r0, 0x8000
ori r0, r0, 0x0000
mtdccr r0
lis r0, 0x8000
ori r0, r0, 0x0000
mtdcwr r0
sync
isync
blr
/* void cache_post_wb (int tlb)
*/
cache_post_wb:
lis r0, 0x8000
ori r0, r0, 0x0000
mtdccr r0
lis r0, 0x0000
ori r0, r0, 0x0000
mtdcwr r0
sync
isync
blr
#endif
/* void cache_post_dinvalidate (void *p, int size)
*/

9
post/cpu/ppc4xx/ether.c
View file

@ -68,10 +68,10 @@ static char *rx_buf;
static void ether_post_init (int devnum, int hw_addr)
{
int i;
unsigned mode_reg;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned mode_reg;
sys_info_t sysinfo;
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
@ -185,10 +185,17 @@ static void ether_post_init (int devnum, int hw_addr)
mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
/* set internal loopback mode */
#ifdef CFG_POST_ETHER_EXT_LOOPBACK
out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
EMAC_M1_MF_100MBPS | EMAC_M1_IST |
in32 (EMAC_M1));
#else
out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
EMAC_M1_MF_100MBPS | EMAC_M1_IST |
in32 (EMAC_M1));
#endif
/* set transmit enable & receive enable */
out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);

136
post/cpu/ppc4xx/uart.c
View file

@ -38,24 +38,77 @@
#if CONFIG_POST & CFG_POST_UART
/*
* This table defines the UART's that should be tested and can
* be overridden in the board config file
*/
#ifndef CFG_POST_UART_TABLE
#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
#endif
#include <asm/processor.h>
#include <serial.h>
#if defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
#else
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
#endif
#if defined(CONFIG_440GP)
#define CR0_MASK 0x3fff0000
#define CR0_EXTCLK_ENA 0x00600000
#define CR0_UDIV_POS 16
#define UDIV_SUBTRACT 1
#define UART0_SDR cntrl0
#define MFREG(a, d) d = mfdcr(a)
#define MTREG(a, d) mtdcr(a, d)
#else /* #if defined(CONFIG_440GP) */
/* all other 440 PPC's access clock divider via sdr register */
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPe)
#define UART2_SDR sdr_uart2
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRx)
#define UART3_SDR sdr_uart3
#endif
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
#endif /* #if defined(CONFIG_440GP) */
#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
#define UCR0_MASK 0x0000007f
#define UCR1_MASK 0x00007f00
#define UCR0_UDIV_POS 0
#define UCR1_UDIV_POS 8
#define UDIV_MAX 127
#else /* CONFIG_405GP || CONFIG_405CR */
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
#define CR0_MASK 0x00001fff
#define CR0_EXTCLK_ENA 0x000000c0
#define CR0_UDIV_POS 1
#define UDIV_MAX 32
#endif
#define UART_RBR 0x00
#define UART_THR 0x00
@ -71,8 +124,8 @@
#define UART_DLM 0x01
/*
Line Status Register.
*/
* Line Status Register.
*/
#define asyncLSRDataReady1 0x01
#define asyncLSROverrunError1 0x02
#define asyncLSRParityError1 0x04
@ -84,6 +137,7 @@
DECLARE_GLOBAL_DATA_PTR;
<<<<<<< master
#if !defined(CFG_EXT_SERIAL_CLOCK)
static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned short *pbdiv)
@ -127,6 +181,9 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
}
#endif
=======
#if defined(CONFIG_440)
>>>>>>> zeus
static int uart_post_init (unsigned long dev_base)
{
unsigned long reg;
@ -190,6 +247,77 @@ static int uart_post_init (unsigned long dev_base)
return 0;
}
#else /* CONFIG_440 */
static int uart_post_init (unsigned long dev_base)
{
unsigned long reg;
unsigned long tmp;
unsigned long clk;
unsigned long udiv;
unsigned short bdiv;
volatile char val;
int i;
for (i = 0; i < 3500; i++) {
if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
break;
udelay (100);
}
#if defined(CONFIG_405EZ)
serial_divs(gd->baudrate, &udiv, &bdiv);
clk = tmp = reg = 0;
#else
#ifdef CONFIG_405EP
reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
tmp = CFG_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
mtdcr (cpc0_ucr, reg);
#else /* CONFIG_405EP */
reg = mfdcr(cntrl0) & ~CR0_MASK;
#ifdef CFG_EXT_SERIAL_CLOCK
clk = CFG_EXT_SERIAL_CLOCK;
udiv = 1;
reg |= CR0_EXTCLK_ENA;
#else
clk = gd->cpu_clk;
#ifdef CFG_405_UART_ERRATA_59
udiv = 31; /* Errata 59: stuck at 31 */
#else
tmp = CFG_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
#endif
#endif
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (cntrl0, reg);
#endif /* CONFIG_405EP */
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
#endif /* CONFIG_405EZ */
out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
val = in8(dev_base + UART_LSR); /* clear line status */
val = in8(dev_base + UART_RBR); /* read receive buffer */
out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
return (0);
}
#endif /* CONFIG_440 */
static void uart_post_putc (unsigned long dev_base, char c)
{
int i;
@ -241,9 +369,7 @@ done:
int uart_post_test (int flags)
{
int i, res = 0;
static unsigned long base[] = {
UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
};
static unsigned long base[] = CFG_POST_UART_TABLE;
for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
if (test_ctlr (base[i], i))