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ppc4xx: Add change_tlb function to modify I attribute of TLB(s)

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This function is used to either turn cache on or off in a specific
memory area.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-10-31 17:59:22 +01:00
parent d25dfe08fb
commit 483e09a223
2 changed files with 88 additions and 1 deletions
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88
cpu/ppc4xx/tlb.c
View file

@ -26,6 +26,7 @@
#if defined(CONFIG_440)
#include <ppc440.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/mmu.h>
@ -42,7 +43,6 @@ void remove_tlb(u32 vaddr, u32 size)
u32 tlb_vaddr;
u32 tlb_size = 0;
/* First, find the index of a TLB entry not being used */
for (i=0; i<PPC4XX_TLB_SIZE; i++) {
tlb_word0_value = mftlb1(i);
tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
@ -96,6 +96,92 @@ void remove_tlb(u32 vaddr, u32 size)
asm("isync");
}
/*
* Change the I attribute (cache inhibited) of a TLB or multiple TLB's.
* This function is used to either turn cache on or off in a specific
* memory area.
*/
void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
{
int i;
u32 tlb_word0_value;
u32 tlb_word2_value;
u32 tlb_vaddr;
u32 tlb_size = 0;
for (i=0; i<PPC4XX_TLB_SIZE; i++) {
tlb_word0_value = mftlb1(i);
tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
(tlb_vaddr >= vaddr)) {
/*
* TLB is enabled and start address is lower or equal
* than the area we are looking for. Now we only have
* to check the size/end address for a match.
*/
switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
case TLB_WORD0_SIZE_1KB:
tlb_size = 1 << 10;
break;
case TLB_WORD0_SIZE_4KB:
tlb_size = 4 << 10;
break;
case TLB_WORD0_SIZE_16KB:
tlb_size = 16 << 10;
break;
case TLB_WORD0_SIZE_64KB:
tlb_size = 64 << 10;
break;
case TLB_WORD0_SIZE_256KB:
tlb_size = 256 << 10;
break;
case TLB_WORD0_SIZE_1MB:
tlb_size = 1 << 20;
break;
case TLB_WORD0_SIZE_16MB:
tlb_size = 16 << 20;
break;
case TLB_WORD0_SIZE_256MB:
tlb_size = 256 << 20;
break;
}
/*
* Now check the end-address if it's in the range
*/
if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) {
/*
* Found a TLB in the range.
* Change cache attribute in tlb2 word.
*/
tlb_word2_value =
TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
TLB_WORD2_W_DISABLE | tlb_word2_i_value |
TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
TLB_WORD2_SR_ENABLE;
/*
* Now either flush or invalidate the dcache
*/
if (tlb_word2_i_value)
flush_dcache();
else
invalidate_dcache();
mttlb3(i, tlb_word2_value);
asm("iccci 0,0");
}
}
}
/* Execute an ISYNC instruction so that the new TLB entry takes effect */
asm("isync");
}
static int add_tlb_entry(unsigned long phys_addr,
unsigned long virt_addr,
unsigned long tlb_word0_size_value,

1
include/asm-ppc/mmu.h
View file

@ -648,6 +648,7 @@ unsigned long mftlb3(unsigned long index);
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void remove_tlb(u32 vaddr, u32 size);
void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */