mirror of
https://github.com/AsahiLinux/u-boot
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[PATCH] Add support for AMCC Taishan PPC440GX eval board
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
1bbbbdd20f
commit
5fb692cae5
14 changed files with 1486 additions and 80 deletions
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@ -292,6 +292,7 @@ Stefan Roese <sr@denx.de>
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pcs440ep PPC440EP
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sequoia PPC440EPx
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sycamore PPC405GPr
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taishan PPC440GX
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walnut PPC405GP
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yellowstone PPC440GR
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yosemite PPC440EP
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6
MAKEALL
6
MAKEALL
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@ -86,9 +86,9 @@ LIST_4xx=" \
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ocotea OCRTC ORSG p3p440 \
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PCI405 pcs440ep PIP405 PLU405 \
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PMC405 PPChameleonEVB sbc405 sequoia \
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sequoia_nand VOH405 VOM405 W7OLMC \
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W7OLMG walnut WUH405 XPEDITE1K \
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yellowstone yosemite yucca \
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sequoia_nand taishan VOH405 VOM405 \
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W7OLMC W7OLMG walnut WUH405 \
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XPEDITE1K yellowstone yosemite yucca \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -1207,6 +1207,9 @@ sycamore_config: unconfig
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@echo "Configuring for sycamore board as subset of walnut..."
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@$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc
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taishan_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
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VOH405_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
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51
board/amcc/taishan/Makefile
Normal file
51
board/amcc/taishan/Makefile
Normal file
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@ -0,0 +1,51 @@
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#
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# (C) Copyright 2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o lcd.o update.o showinfo.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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44
board/amcc/taishan/config.mk
Normal file
44
board/amcc/taishan/config.mk
Normal file
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# AMCC 440GX Reference Platform (Taishan) board
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#
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#TEXT_BASE = 0xFFFE0000
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ifeq ($(ramsym),1)
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TEXT_BASE = 0x07FD0000
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else
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TEXT_BASE = 0xFFFC0000
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endif
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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endif
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ifeq ($(dbcr),1)
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif
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97
board/amcc/taishan/init.S
Normal file
97
board/amcc/taishan/init.S
Normal file
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@ -0,0 +1,97 @@
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <config.h>
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/* General */
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#define TLB_VALID 0x00000200
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#define _256M 0x10000000
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/* Supported page sizes */
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#define SZ_1K 0x00000000
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#define SZ_4K 0x00000010
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#define SZ_16K 0x00000020
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#define SZ_64K 0x00000030
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#define SZ_256K 0x00000040
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#define SZ_1M 0x00000050
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#define SZ_8M 0x00000060
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#define SZ_16M 0x00000070
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#define SZ_256M 0x00000090
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/* Storage attributes */
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#define SA_W 0x00000800 /* Write-through */
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#define SA_I 0x00000400 /* Caching inhibited */
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#define SA_M 0x00000200 /* Memory coherence */
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#define SA_G 0x00000100 /* Guarded */
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#define SA_E 0x00000080 /* Endian */
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/* Access control */
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#define AC_X 0x00000024 /* Execute */
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#define AC_W 0x00000012 /* Write */
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#define AC_R 0x00000009 /* Read */
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/* Some handy macros */
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#define EPN(e) ((e) & 0xfffffc00)
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#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
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#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
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#define TLB2(a) ( (a)&0x00000fbf )
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#define tlbtab_start\
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mflr r1 ;\
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bl 0f ;
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#define tlbtab_end\
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.long 0, 0, 0 ; \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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#define tlbentry(epn,sz,rpn,erpn,attr)\
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.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
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/**************************************************************************
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*************************************************************************/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
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tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
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tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
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tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
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tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
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tlbtab_end
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380
board/amcc/taishan/lcd.c
Normal file
380
board/amcc/taishan/lcd.c
Normal file
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@ -0,0 +1,380 @@
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <miiphy.h>
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#ifdef CONFIG_TAISHAN
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#define LCD_DELAY_NORMAL_US 100
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#define LCD_DELAY_NORMAL_MS 2
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#define LCD_CMD_ADDR ((volatile char *)(CFG_EBC2_LCM_BASE))
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#define LCD_DATA_ADDR ((volatile char *)(CFG_EBC2_LCM_BASE+1))
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#define LCD_BLK_CTRL ((volatile char *)(CFG_EBC1_FPGA_BASE+0x2))
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#define mdelay(t) ({unsigned long msec=(t); while (msec--) { udelay(1000);}})
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static int g_lcd_init_b = 0;
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static char *amcc_logo = " AMCC TAISHAN 440GX EvalBoard";
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static char addr_flag = 0x80;
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static void lcd_bl_ctrl(char val)
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{
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char cpld_val;
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cpld_val = *LCD_BLK_CTRL;
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*LCD_BLK_CTRL = val | cpld_val;
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}
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static void lcd_putc(char val)
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{
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int i = 100;
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char addr;
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while (i--) {
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if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
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udelay(LCD_DELAY_NORMAL_US);
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break;
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}
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udelay(LCD_DELAY_NORMAL_US);
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}
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if (*LCD_CMD_ADDR & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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addr = *LCD_CMD_ADDR;
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udelay(LCD_DELAY_NORMAL_US);
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if ((addr != 0) && (addr % 0x10 == 0)) {
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addr_flag ^= 0x40;
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*LCD_CMD_ADDR = addr_flag;
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}
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udelay(LCD_DELAY_NORMAL_US);
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*LCD_DATA_ADDR = val;
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udelay(LCD_DELAY_NORMAL_US);
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}
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static void lcd_puts(char *s)
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{
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char *p = s;
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int i = 100;
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while (i--) {
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if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
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udelay(LCD_DELAY_NORMAL_US);
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break;
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}
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udelay(LCD_DELAY_NORMAL_US);
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}
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if (*LCD_CMD_ADDR & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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while (*p)
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lcd_putc(*p++);
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}
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static void lcd_put_logo(void)
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{
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int i = 100;
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char *p = amcc_logo;
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while (i--) {
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if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
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udelay(LCD_DELAY_NORMAL_US);
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break;
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}
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udelay(LCD_DELAY_NORMAL_US);
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}
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if (*LCD_CMD_ADDR & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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*LCD_CMD_ADDR = 0x80;
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while (*p)
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lcd_putc(*p++);
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}
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int lcd_init(void)
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{
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if (g_lcd_init_b == 0) {
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puts("LCD: ");
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mdelay(100); /* Waiting for the LCD initialize */
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*LCD_CMD_ADDR = 0x38; /*set function:8-bit,2-line,5x7 font type */
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udelay(LCD_DELAY_NORMAL_US);
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*LCD_CMD_ADDR = 0x0f; /*set display on,cursor on,blink on */
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udelay(LCD_DELAY_NORMAL_US);
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*LCD_CMD_ADDR = 0x01; /*display clear */
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mdelay(LCD_DELAY_NORMAL_MS);
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*LCD_CMD_ADDR = 0x06; /*set entry */
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udelay(LCD_DELAY_NORMAL_US);
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lcd_bl_ctrl(0x02);
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lcd_put_logo();
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puts(" ready\n");
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g_lcd_init_b = 1;
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}
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return 0;
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}
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static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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lcd_init();
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return 0;
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}
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static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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*LCD_CMD_ADDR = 0x01;
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mdelay(LCD_DELAY_NORMAL_MS);
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return 0;
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}
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static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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if (argc < 2) {
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printf("%s", cmdtp->usage);
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return 1;
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}
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lcd_puts(argv[1]);
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return 0;
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}
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static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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if (argc < 2) {
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printf("%s", cmdtp->usage);
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return 1;
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}
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lcd_putc((char)argv[1][0]);
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return 0;
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}
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static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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ulong count;
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ulong dir;
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char cur_addr;
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if (argc < 3) {
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printf("%s", cmdtp->usage);
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return 1;
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}
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count = simple_strtoul(argv[1], NULL, 16);
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if (count > 31) {
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printf("unable to shift > 0x20\n");
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count = 0;
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}
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dir = simple_strtoul(argv[2], NULL, 16);
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cur_addr = *LCD_CMD_ADDR;
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udelay(LCD_DELAY_NORMAL_US);
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if (dir == 0x0) {
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if (addr_flag == 0x80) {
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if (count >= (cur_addr & 0xf)) {
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*LCD_CMD_ADDR = 0x80;
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udelay(LCD_DELAY_NORMAL_US);
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count = 0;
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}
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} else {
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if (count >= ((cur_addr & 0x0f) + 0x0f)) {
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*LCD_CMD_ADDR = 0x80;
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addr_flag = 0x80;
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udelay(LCD_DELAY_NORMAL_US);
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count = 0x0;
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} else if (count >= (cur_addr & 0xf)) {
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count -= cur_addr & 0xf;
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*LCD_CMD_ADDR = 0x80 | 0xf;
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addr_flag = 0x80;
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udelay(LCD_DELAY_NORMAL_US);
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}
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}
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} else {
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if (addr_flag == 0x80) {
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||||
if (count >= (0x1f - (cur_addr & 0xf))) {
|
||||
count = 0x0;
|
||||
addr_flag = 0xc0;
|
||||
*LCD_CMD_ADDR = 0xc0 | 0xf;
|
||||
udelay(LCD_DELAY_NORMAL_US);
|
||||
} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
|
||||
count = count + (cur_addr & 0xf) - 0x0f;
|
||||
addr_flag = 0xc0;
|
||||
*LCD_CMD_ADDR = 0xc0;
|
||||
udelay(LCD_DELAY_NORMAL_US);
|
||||
}
|
||||
} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
|
||||
count = 0x0;
|
||||
*LCD_CMD_ADDR = 0xc0 | 0xf;
|
||||
udelay(LCD_DELAY_NORMAL_US);
|
||||
}
|
||||
}
|
||||
|
||||
while (count--) {
|
||||
if (dir == 0) {
|
||||
*LCD_CMD_ADDR = 0x10;
|
||||
} else {
|
||||
*LCD_CMD_ADDR = 0x14;
|
||||
}
|
||||
udelay(LCD_DELAY_NORMAL_US);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd_test - lcd test display\n", NULL);
|
||||
U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd_cls - lcd clear display\n", NULL);
|
||||
U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
|
||||
"lcd_puts - display string on lcd\n",
|
||||
"<string> - <string> to be displayed\n");
|
||||
U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
|
||||
"lcd_putc - display char on lcd\n",
|
||||
"<char> - <char> to be displayed\n");
|
||||
U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
|
||||
"lcd_cur - shift cursor on lcd\n",
|
||||
"<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
|
||||
" <count> - 0~31\n" " <dir> - 0,backward; 1, forward\n");
|
||||
|
||||
#if 0 // test-only
|
||||
void set_phy_loopback_mode(void)
|
||||
{
|
||||
char devemac2[32];
|
||||
char devemac3[32];
|
||||
|
||||
sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
|
||||
sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
|
||||
|
||||
#if 0
|
||||
unsigned short reg_short;
|
||||
|
||||
miiphy_read(devemac2, 0x1, 1, ®_short);
|
||||
if (reg_short & 0x04) {
|
||||
/*
|
||||
* printf("EMAC2 link up,do nothing\n");
|
||||
*/
|
||||
} else {
|
||||
udelay(1000);
|
||||
miiphy_write(devemac2, 0x1, 0, 0x6000);
|
||||
udelay(1000);
|
||||
miiphy_read(devemac2, 0x1, 0, ®_short);
|
||||
if (reg_short != 0x6000) {
|
||||
printf
|
||||
("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n",
|
||||
reg_short);
|
||||
}
|
||||
}
|
||||
|
||||
miiphy_read(devemac3, 0x3, 1, ®_short);
|
||||
if (reg_short & 0x04) {
|
||||
/*
|
||||
* printf("EMAC3 link up,do nothing\n");
|
||||
*/
|
||||
} else {
|
||||
udelay(1000);
|
||||
miiphy_write(devemac3, 0x3, 0, 0x6000);
|
||||
udelay(1000);
|
||||
miiphy_read(devemac3, 0x3, 0, ®_short);
|
||||
if (reg_short != 0x6000) {
|
||||
printf
|
||||
("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n",
|
||||
reg_short);
|
||||
}
|
||||
}
|
||||
#else
|
||||
/* Set PHY as LOOPBACK MODE, for Linux emac initializing */
|
||||
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000);
|
||||
udelay(1000);
|
||||
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000);
|
||||
udelay(1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
void set_phy_normal_mode(void)
|
||||
{
|
||||
char devemac2[32];
|
||||
char devemac3[32];
|
||||
unsigned short reg_short;
|
||||
|
||||
sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
|
||||
sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
|
||||
|
||||
/* Set phy of EMAC2 */
|
||||
miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, ®_short);
|
||||
reg_short &= ~(0x7);
|
||||
reg_short |= 0x6; /* RGMII DLL Delay */
|
||||
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short);
|
||||
|
||||
miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, ®_short);
|
||||
reg_short &= ~(0x40);
|
||||
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short);
|
||||
|
||||
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0);
|
||||
|
||||
/* Set phy of EMAC3 */
|
||||
miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, ®_short);
|
||||
reg_short &= ~(0x7);
|
||||
reg_short |= 0x6; /* RGMII DLL Delay */
|
||||
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short);
|
||||
|
||||
miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, ®_short);
|
||||
reg_short &= ~(0x40);
|
||||
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short);
|
||||
|
||||
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
volatile unsigned int *GpioOr =
|
||||
(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
|
||||
*GpioOr |= 0x00300000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
volatile unsigned int *GpioOr =
|
||||
(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
|
||||
*GpioOr &= ~0x00300000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
|
||||
"ledon - led test light on\n", NULL);
|
||||
|
||||
U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
|
||||
"ledoff - led test light off\n", NULL);
|
||||
#endif
|
||||
236
board/amcc/taishan/showinfo.c
Normal file
236
board/amcc/taishan/showinfo.c
Normal file
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <pci.h>
|
||||
|
||||
void show_reset_reg(void)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
/* read clock regsiter */
|
||||
printf("===== Display reset and initialize register Start =========\n");
|
||||
mfclk(clk_pllc,reg);
|
||||
printf("cpr_pllc = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_plld,reg);
|
||||
printf("cpr_plld = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_primad,reg);
|
||||
printf("cpr_primad = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_primbd,reg);
|
||||
printf("cpr_primbd = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_opbd,reg);
|
||||
printf("cpr_opbd = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_perd,reg);
|
||||
printf("cpr_perd = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_mald,reg);
|
||||
printf("cpr_mald = %#010x\n",reg);
|
||||
|
||||
/* read sdr register */
|
||||
mfsdr(sdr_ebc,reg);
|
||||
printf("sdr_ebc = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_cp440,reg);
|
||||
printf("sdr_cp440 = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_xcr,reg);
|
||||
printf("sdr_xcr = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_xpllc,reg);
|
||||
printf("sdr_xpllc = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_xplld,reg);
|
||||
printf("sdr_xplld = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_pfc0,reg);
|
||||
printf("sdr_pfc0 = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_pfc1,reg);
|
||||
printf("sdr_pfc1 = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_cust0,reg);
|
||||
printf("sdr_cust0 = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_cust1,reg);
|
||||
printf("sdr_cust1 = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_uart0,reg);
|
||||
printf("sdr_uart0 = %#010x\n",reg);
|
||||
|
||||
mfsdr(sdr_uart1,reg);
|
||||
printf("sdr_uart1 = %#010x\n",reg);
|
||||
|
||||
printf("===== Display reset and initialize register End =========\n");
|
||||
}
|
||||
|
||||
void show_xbridge_info(void)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
printf("PCI-X chip control registers\n");
|
||||
mfsdr(sdr_xcr, reg);
|
||||
printf("sdr_xcr = %#010x\n", reg);
|
||||
|
||||
mfsdr(sdr_xpllc, reg);
|
||||
printf("sdr_xpllc = %#010x\n", reg);
|
||||
|
||||
mfsdr(sdr_xplld, reg);
|
||||
printf("sdr_xplld = %#010x\n", reg);
|
||||
|
||||
printf("PCI-X Bridge Configure registers\n");
|
||||
printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
|
||||
printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID));
|
||||
printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD));
|
||||
printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS));
|
||||
printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID));
|
||||
printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS));
|
||||
printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM));
|
||||
printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
|
||||
printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
|
||||
|
||||
printf("PCIX0_BAR0 = %#010x\n", in32r(PCIX0_BAR0));
|
||||
printf("PCIX0_BAR1 = %#010x\n", in32r(PCIX0_BAR1));
|
||||
printf("PCIX0_BAR2 = %#010x\n", in32r(PCIX0_BAR2));
|
||||
printf("PCIX0_BAR3 = %#010x\n", in32r(PCIX0_BAR3));
|
||||
printf("PCIX0_BAR4 = %#010x\n", in32r(PCIX0_BAR4));
|
||||
printf("PCIX0_BAR5 = %#010x\n", in32r(PCIX0_BAR5));
|
||||
|
||||
printf("PCIX0_CISPTR = %#010x\n", in32r(PCIX0_CISPTR));
|
||||
printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
|
||||
printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
|
||||
printf("PCIX0_EROMBA = %#010x\n", in32r(PCIX0_EROMBA));
|
||||
printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
|
||||
printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
|
||||
printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
|
||||
printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
|
||||
printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
|
||||
|
||||
printf("PCIX0_BRDGOPT1 = %#010x\n", in32r(PCIX0_BRDGOPT1));
|
||||
printf("PCIX0_BRDGOPT2 = %#010x\n", in32r(PCIX0_BRDGOPT2));
|
||||
|
||||
printf("PCIX0_POM0LAL = %#010x\n", in32r(PCIX0_POM0LAL));
|
||||
printf("PCIX0_POM0LAH = %#010x\n", in32r(PCIX0_POM0LAH));
|
||||
printf("PCIX0_POM0SA = %#010x\n", in32r(PCIX0_POM0SA));
|
||||
printf("PCIX0_POM0PCILAL = %#010x\n", in32r(PCIX0_POM0PCIAL));
|
||||
printf("PCIX0_POM0PCILAH = %#010x\n", in32r(PCIX0_POM0PCIAH));
|
||||
printf("PCIX0_POM1LAL = %#010x\n", in32r(PCIX0_POM1LAL));
|
||||
printf("PCIX0_POM1LAH = %#010x\n", in32r(PCIX0_POM1LAH));
|
||||
printf("PCIX0_POM1SA = %#010x\n", in32r(PCIX0_POM1SA));
|
||||
printf("PCIX0_POM1PCILAL = %#010x\n", in32r(PCIX0_POM1PCIAL));
|
||||
printf("PCIX0_POM1PCILAH = %#010x\n", in32r(PCIX0_POM1PCIAH));
|
||||
printf("PCIX0_POM2SA = %#010x\n", in32r(PCIX0_POM2SA));
|
||||
|
||||
printf("PCIX0_PIM0SA = %#010x\n", in32r(PCIX0_PIM0SA));
|
||||
printf("PCIX0_PIM0LAL = %#010x\n", in32r(PCIX0_PIM0LAL));
|
||||
printf("PCIX0_PIM0LAH = %#010x\n", in32r(PCIX0_PIM0LAH));
|
||||
printf("PCIX0_PIM1SA = %#010x\n", in32r(PCIX0_PIM1SA));
|
||||
printf("PCIX0_PIM1LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
|
||||
printf("PCIX0_PIM1LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
|
||||
printf("PCIX0_PIM2SA = %#010x\n", in32r(PCIX0_PIM1SA));
|
||||
printf("PCIX0_PIM2LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
|
||||
printf("PCIX0_PIM2LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
|
||||
|
||||
printf("PCIX0_XSTS = %#010x\n", in32r(PCIX0_STS));
|
||||
}
|
||||
|
||||
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
show_xbridge_info();
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
|
||||
"xbriinfo - Show PCIX bridge info\n", NULL);
|
||||
|
||||
#define TAISHAN_PCI_DEV_ID0 0x800
|
||||
#define TAISHAN_PCI_DEV_ID1 0x1000
|
||||
|
||||
void show_pcix_device_info(void)
|
||||
{
|
||||
int ii;
|
||||
int dev;
|
||||
u8 capp;
|
||||
u8 xcapid;
|
||||
u16 status;
|
||||
u16 xcommand;
|
||||
u32 xstatus;
|
||||
|
||||
for (ii = 0; ii < 2; ii++) {
|
||||
if (ii == 0)
|
||||
dev = TAISHAN_PCI_DEV_ID0;
|
||||
else
|
||||
dev = TAISHAN_PCI_DEV_ID1;
|
||||
|
||||
pci_read_config_word(dev, PCI_STATUS, &status);
|
||||
if (status & PCI_STATUS_CAP_LIST) {
|
||||
pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
|
||||
|
||||
pci_read_config_byte(dev, (int)(capp), &xcapid);
|
||||
if (xcapid == 0x07) {
|
||||
pci_read_config_word(dev, (int)(capp + 2),
|
||||
&xcommand);
|
||||
pci_read_config_dword(dev, (int)(capp + 4),
|
||||
&xstatus);
|
||||
printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
|
||||
(ii + 1), xcommand, xstatus);
|
||||
} else {
|
||||
printf("BUS0 dev%d PCI-X CAP ID error,"
|
||||
"CAP=%#04x,XCAPID=%#04x\n",
|
||||
(ii + 1), capp, xcapid);
|
||||
}
|
||||
} else {
|
||||
printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
|
||||
ii + 1);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
|
||||
char *argv[])
|
||||
{
|
||||
show_pcix_device_info();
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
|
||||
"xdevinfo - Show PCIX Device info\n", NULL);
|
||||
|
||||
extern void show_reset_reg(void);
|
||||
|
||||
int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
show_reset_reg();
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
|
||||
"resetinfo - Show Reset REG info\n", NULL);
|
||||
331
board/amcc/taishan/taishan.c
Normal file
331
board/amcc/taishan/taishan.c
Normal file
|
|
@ -0,0 +1,331 @@
|
|||
/*
|
||||
* Copyright (C) 2004 PaulReynolds@lhsolutions.com
|
||||
*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <ppc4xx_enet.h>
|
||||
|
||||
#ifdef CFG_INIT_SHOW_RESET_REG
|
||||
void show_reset_reg(void);
|
||||
#endif
|
||||
|
||||
int lcd_init(void);
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
unsigned long reg;
|
||||
volatile unsigned int *GpioOdr;
|
||||
volatile unsigned int *GpioTcr;
|
||||
volatile unsigned int *GpioOr;
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Initialize EBC CONFIG
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
|
||||
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
|
||||
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
|
||||
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
|
||||
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| 64MB FLASH. Initialize bank 0 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
|
||||
EBC_BXAP_BCE_DISABLE |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
|
||||
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
|
||||
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
|
||||
EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
|
||||
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| FPGA. Initialize bank 1 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
|
||||
EBC_BXAP_BCE_DISABLE |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
|
||||
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
|
||||
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
|
||||
EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| LCM. Initialize bank 2 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
|
||||
EBC_BXAP_BCE_DISABLE |
|
||||
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
|
||||
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
|
||||
EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| TMP. Initialize bank 3 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
|
||||
EBC_BXAP_BCE_DISABLE |
|
||||
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
|
||||
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
|
||||
EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
|
||||
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Connector 4~7. Initialize bank 3~ 7 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(pb4ap,0);
|
||||
mtebc(pb4cr,0);
|
||||
mtebc(pb5ap,0);
|
||||
mtebc(pb5cr,0);
|
||||
mtebc(pb6ap,0);
|
||||
mtebc(pb6cr,0);
|
||||
mtebc(pb7ap,0);
|
||||
mtebc(pb7cr,0);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic0er, 0x00000000); /* disable all */
|
||||
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
|
||||
mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
|
||||
mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
|
||||
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic1er, 0x00000000); /* disable all */
|
||||
mtdcr (uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
|
||||
mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
|
||||
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */
|
||||
mtdcr (uic2er, 0x00000000); /* disable all */
|
||||
mtdcr (uic2cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
|
||||
mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
|
||||
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (uicb0sr, 0xfc000000); /* clear all */
|
||||
mtdcr (uicb0er, 0x00000000); /* disable all */
|
||||
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
|
||||
mtdcr (uicb0pr, 0xfc000000); /* */
|
||||
mtdcr (uicb0tr, 0x00000000); /* */
|
||||
mtdcr (uicb0vr, 0x00000001); /* */
|
||||
|
||||
/* Enable two GPIO 10~11 and TraceA signal */
|
||||
mfsdr(sdr_pfc0,reg);
|
||||
reg |= 0x00300000;
|
||||
mtsdr(sdr_pfc0,reg);
|
||||
|
||||
mfsdr(sdr_pfc1,reg);
|
||||
reg |= 0x00100000;
|
||||
mtsdr(sdr_pfc1,reg);
|
||||
|
||||
/* Set GPIO 10 and 11 as output */
|
||||
GpioOdr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
|
||||
GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
|
||||
GpioOr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
|
||||
|
||||
*GpioOdr &= ~(0x00300000);
|
||||
*GpioTcr |= 0x00300000;
|
||||
*GpioOr |= 0x00300000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
lcd_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char *s = getenv ("serial#");
|
||||
|
||||
printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
|
||||
if (s != NULL) {
|
||||
puts (", serial# ");
|
||||
puts (s);
|
||||
}
|
||||
putc ('\n');
|
||||
|
||||
#ifdef CFG_INIT_SHOW_RESET_REG
|
||||
show_reset_reg();
|
||||
#endif
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) 0x04000000;
|
||||
uint *pend = (uint *) 0x0fc00000;
|
||||
uint *p;
|
||||
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
|
||||
int pci_pre_init(struct pci_controller * hose )
|
||||
{
|
||||
unsigned long strap;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* The ocotea board is always configured as the host & requires the
|
||||
* PCI arbiter to be enabled.
|
||||
*--------------------------------------------------------------------------*/
|
||||
mfsdr(sdr_sdstp1, strap);
|
||||
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
|
||||
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller * hose )
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Disable everything
|
||||
*--------------------------------------------------------------------------*/
|
||||
out32r( PCIX0_PIM0SA, 0 ); /* disable */
|
||||
out32r( PCIX0_PIM1SA, 0 ); /* disable */
|
||||
out32r( PCIX0_PIM2SA, 0 ); /* disable */
|
||||
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
|
||||
* options to not support sizes such as 128/256 MB.
|
||||
*--------------------------------------------------------------------------*/
|
||||
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
|
||||
out32r( PCIX0_PIM0LAH, 0 );
|
||||
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
|
||||
|
||||
out32r( PCIX0_BAR0, 0 );
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id
|
||||
*--------------------------------------------------------------------------*/
|
||||
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
|
||||
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
|
||||
|
||||
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
/* The ocotea board is always configured as host. */
|
||||
return(1);
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
return (ctrlc());
|
||||
}
|
||||
#endif
|
||||
157
board/amcc/taishan/u-boot.lds
Normal file
157
board/amcc/taishan/u-boot.lds
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/amcc/taishan/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
78
board/amcc/taishan/update.c
Normal file
78
board/amcc/taishan/update.c
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#if defined(CONFIG_TAISHAN)
|
||||
|
||||
const uchar bootstrap_buf[16] = {
|
||||
0x86,
|
||||
0x78,
|
||||
0xc1,
|
||||
0xa6,
|
||||
0x09,
|
||||
0x67,
|
||||
0x04,
|
||||
0x63,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
|
||||
static int update_boot_eeprom(void)
|
||||
{
|
||||
ulong len = 0x10;
|
||||
uchar chip = CFG_BOOTSTRAP_IIC_ADDR;
|
||||
uchar *pbuf = (uchar *)bootstrap_buf;
|
||||
int ii, jj;
|
||||
|
||||
for (ii = 0; ii < len; ii++) {
|
||||
if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) {
|
||||
printf("i2c_write failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* wait 10ms */
|
||||
for (jj = 0; jj < 10; jj++)
|
||||
udelay(1000);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
return update_boot_eeprom();
|
||||
}
|
||||
|
||||
U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
|
||||
"update_boot_eeprom - update bootstrap eeprom content\n", NULL);
|
||||
#endif
|
||||
|
|
@ -26,10 +26,9 @@
|
|||
#include <common.h>
|
||||
#include <pci.h>
|
||||
|
||||
#include "440spe_pcie.h"
|
||||
#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
|
||||
|
||||
#if defined(CONFIG_440SPE)
|
||||
#if defined(CONFIG_PCI)
|
||||
#include "440spe_pcie.h"
|
||||
|
||||
enum {
|
||||
PTYPE_ENDPOINT = 0x0,
|
||||
|
|
@ -958,5 +957,4 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
#endif /* CONFIG_440SPE */
|
||||
#endif /* CONFIG_440SPE && CONFIG_PCI */
|
||||
|
|
|
|||
|
|
@ -166,6 +166,11 @@ struct eth_device *emac0_dev = NULL;
|
|||
#define LAST_EMAC_NUM 1
|
||||
#endif
|
||||
|
||||
/* normal boards start with EMAC0 */
|
||||
#if !defined(CONFIG_EMAC_NR_START)
|
||||
#define CONFIG_EMAC_NR_START 0
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* Prototypes and externals.
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
|
@ -601,6 +606,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
|
|||
/* end Vitesse/Cicada errata */
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ET1011C_PHY)
|
||||
/*
|
||||
* Agere ET1011c PHY needs to have an extended register whacked
|
||||
* for RGMII mode.
|
||||
*/
|
||||
if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
|
||||
miiphy_read (dev->name, reg, 0x16, ®_short);
|
||||
reg_short &= ~(0x7);
|
||||
reg_short |= 0x6; /* RGMII DLL Delay*/
|
||||
miiphy_write (dev->name, reg, 0x16, reg_short);
|
||||
|
||||
miiphy_read (dev->name, reg, 0x17, ®_short);
|
||||
reg_short &= ~(0x40);
|
||||
miiphy_write (dev->name, reg, 0x17, reg_short);
|
||||
|
||||
miiphy_write(dev->name, reg, 0x1c, 0x74f0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* Start/Restart autonegotiation */
|
||||
phy_setup_aneg (dev->name, reg);
|
||||
|
|
@ -643,8 +668,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
|
|||
|
||||
if (hw_p->print_speed) {
|
||||
hw_p->print_speed = 0;
|
||||
printf ("ENET Speed is %d Mbps - %s duplex connection\n",
|
||||
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
|
||||
printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
|
||||
(int) speed, (duplex == HALF) ? "HALF" : "FULL",
|
||||
hw_p->devnum);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
|
||||
|
|
@ -1493,6 +1519,8 @@ int ppc_4xx_eth_initialize (bd_t * bis)
|
|||
struct eth_device *dev;
|
||||
int eth_num = 0;
|
||||
EMAC_4XX_HW_PST hw = NULL;
|
||||
u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
|
||||
u32 hw_addr[4];
|
||||
|
||||
#if defined(CONFIG_440GX)
|
||||
unsigned long pfc1;
|
||||
|
|
@ -1502,6 +1530,43 @@ int ppc_4xx_eth_initialize (bd_t * bis)
|
|||
pfc1 |= 0x01200000;
|
||||
mtsdr (sdr_pfc1, pfc1);
|
||||
#endif
|
||||
|
||||
/* first clear all mac-addresses */
|
||||
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
|
||||
memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
|
||||
|
||||
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
|
||||
switch (eth_num) {
|
||||
default: /* fall through */
|
||||
case 0:
|
||||
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
|
||||
bis->bi_enetaddr, 6);
|
||||
hw_addr[eth_num] = 0x0;
|
||||
break;
|
||||
#ifdef CONFIG_HAS_ETH1
|
||||
case 1:
|
||||
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
|
||||
bis->bi_enet1addr, 6);
|
||||
hw_addr[eth_num] = 0x100;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH2
|
||||
case 2:
|
||||
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
|
||||
bis->bi_enet2addr, 6);
|
||||
hw_addr[eth_num] = 0x400;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH3
|
||||
case 3:
|
||||
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
|
||||
bis->bi_enet3addr, 6);
|
||||
hw_addr[eth_num] = 0x600;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/* set phy num and mode */
|
||||
bis->bi_phynum[0] = CONFIG_PHY_ADDR;
|
||||
bis->bi_phymode[0] = 0;
|
||||
|
|
@ -1520,40 +1585,13 @@ int ppc_4xx_eth_initialize (bd_t * bis)
|
|||
#endif
|
||||
|
||||
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
|
||||
|
||||
/* See if we can actually bring up the interface, otherwise, skip it */
|
||||
switch (eth_num) {
|
||||
default: /* fall through */
|
||||
case 0:
|
||||
if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
|
||||
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
#ifdef CONFIG_HAS_ETH1
|
||||
case 1:
|
||||
if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
|
||||
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH2
|
||||
case 2:
|
||||
if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
|
||||
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH3
|
||||
case 3:
|
||||
if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
|
||||
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
/*
|
||||
* See if we can actually bring up the interface,
|
||||
* otherwise, skip it
|
||||
*/
|
||||
if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
|
||||
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Allocate device structure */
|
||||
|
|
@ -1576,36 +1614,12 @@ int ppc_4xx_eth_initialize (bd_t * bis)
|
|||
}
|
||||
memset(hw, 0, sizeof(*hw));
|
||||
|
||||
switch (eth_num) {
|
||||
default: /* fall through */
|
||||
case 0:
|
||||
hw->hw_addr = 0;
|
||||
memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
|
||||
break;
|
||||
#ifdef CONFIG_HAS_ETH1
|
||||
case 1:
|
||||
hw->hw_addr = 0x100;
|
||||
memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH2
|
||||
case 2:
|
||||
hw->hw_addr = 0x400;
|
||||
memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH3
|
||||
case 3:
|
||||
hw->hw_addr = 0x600;
|
||||
memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
hw->hw_addr = hw_addr[eth_num];
|
||||
memcpy (dev->enetaddr, ethaddr[eth_num], 6);
|
||||
hw->devnum = eth_num;
|
||||
hw->print_speed = 1;
|
||||
|
||||
sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
|
||||
sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
|
||||
dev->priv = (void *) hw;
|
||||
dev->init = ppc_4xx_eth_init;
|
||||
dev->halt = ppc_4xx_eth_halt;
|
||||
|
|
@ -1663,7 +1677,6 @@ int ppc_4xx_eth_initialize (bd_t * bis)
|
|||
return (1);
|
||||
}
|
||||
|
||||
|
||||
#if !defined(CONFIG_NET_MULTI)
|
||||
void eth_halt (void) {
|
||||
if (emac0_dev) {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2005-2006
|
||||
* (C) Copyright 2005-2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
|
|
@ -32,9 +32,9 @@
|
|||
#include <asm/processor.h>
|
||||
#include "sdram.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_SDRAM_BANK0
|
||||
|
||||
#ifndef CONFIG_440
|
||||
|
||||
#ifndef CFG_SDRAM_TABLE
|
||||
sdram_conf_t mb0cf[] = {
|
||||
|
|
@ -50,9 +50,6 @@ sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
|
|||
|
||||
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
|
||||
|
||||
|
||||
#ifndef CONFIG_440
|
||||
|
||||
#ifdef CFG_SDRAM_CASL
|
||||
static ulong ns2clks(ulong ns)
|
||||
{
|
||||
|
|
@ -221,6 +218,26 @@ void sdram_init(void)
|
|||
|
||||
#else /* CONFIG_440 */
|
||||
|
||||
/*
|
||||
* Define some default values. Those can be overwritten in the
|
||||
* board config file.
|
||||
*/
|
||||
|
||||
#ifndef CFG_SDRAM_TABLE
|
||||
sdram_conf_t mb0cf[] = {
|
||||
{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
|
||||
{(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
|
||||
};
|
||||
#else
|
||||
sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
|
||||
#endif
|
||||
|
||||
#ifndef CFG_SDRAM0_TR0
|
||||
#define CFG_SDRAM0_TR0 0x41094012
|
||||
#endif
|
||||
|
||||
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
|
||||
|
||||
#define NUM_TRIES 64
|
||||
#define NUM_READS 10
|
||||
|
||||
|
|
@ -295,7 +312,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
|
|||
*tr1_value = (first_good + last_bad) / 2;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_SDRAM_ECC
|
||||
static void ecc_init(ulong start, ulong size)
|
||||
{
|
||||
|
|
@ -351,7 +367,8 @@ long int initdram(int board_type)
|
|||
int i;
|
||||
int tr1_bank1;
|
||||
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
|
||||
defined(CONFIG_440GR) || defined(CONFIG_440SP)
|
||||
/*
|
||||
* Soft-reset SDRAM controller.
|
||||
*/
|
||||
|
|
@ -378,7 +395,7 @@ long int initdram(int board_type)
|
|||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
||||
*/
|
||||
mtsdram(mem_b0cr, mb0cf[i].reg);
|
||||
mtsdram(mem_tr0, 0x41094012);
|
||||
mtsdram(mem_tr0, CFG_SDRAM0_TR0);
|
||||
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
|
||||
mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
|
||||
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue