mirror of
https://github.com/AsahiLinux/u-boot
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Add support for PCS440EP board
Patch by Stefan Roese, 02 Jun 2006
This commit is contained in:
Stefan Roese
parent
392c252efd
commit
a4c8d1389f
14 changed files with 1986 additions and 49 deletions
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@ -7,6 +7,9 @@ Changes since U-Boot 1.1.4:
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MPC8272 boards. Eventually this should be used on all boards?]
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Patch by Wolfgang Grandegger, 17 Jan 2006
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* Add support for PCS440EP board
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Patch by Stefan Roese, 02 Jun 2006
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* Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
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Patch by Stefan Roese, 29 May 2006
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@ -283,6 +283,7 @@ Stefan Roese <sr@denx.de>
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ebony PPC440GP
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ocotea PPC440GX
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p3p440 PPC440GP
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pcs440ep PPC440EP
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sycamore PPC405GPr
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walnut PPC405GP
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yellowstone PPC440GR
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10
MAKEALL
10
MAKEALL
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@ -71,11 +71,11 @@ LIST_4xx=" \
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HH405 HUB405 JSE KAREF \
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luan METROBOX MIP405 MIP405T \
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ML2 ml300 ocotea OCRTC \
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ORSG p3p440 PCI405 PIP405 \
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PLU405 PMC405 PPChameleonEVB sbc405 \
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VOH405 VOM405 W7OLMC W7OLMG \
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walnut WUH405 XPEDITE1K yellowstone \
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yosemite \
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ORSG p3p440 PCI405 pcs440ep \
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PIP405 PLU405 PMC405 PPChameleonEVB \
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sbc405 VOH405 VOM405 W7OLMC \
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W7OLMG walnut WUH405 XPEDITE1K \
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yellowstone yosemite \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -919,6 +919,9 @@ p3p440_config: unconfig
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PCI405_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
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pcs440ep_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx pcs440ep
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PIP405_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
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47
board/pcs440ep/Makefile
Normal file
47
board/pcs440ep/Makefile
Normal file
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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44
board/pcs440ep/config.mk
Normal file
44
board/pcs440ep/config.mk
Normal file
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# PCS440EP board
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#
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#TEXT_BASE = 0x00001000
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ifeq ($(ramsym),1)
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TEXT_BASE = 0xFBD00000
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else
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TEXT_BASE = 0xFFF80000
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endif
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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endif
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ifeq ($(dbcr),1)
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif
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602
board/pcs440ep/flash.c
Normal file
602
board/pcs440ep/flash.c
Normal file
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@ -0,0 +1,602 @@
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#ifndef CFG_FLASH_READ0
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#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
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#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
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#endif
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*
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* Functions
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*/
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static int write_word(flash_info_t *info, ulong dest, ulong data);
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static ulong flash_get_size(vu_long *addr, flash_info_t *info);
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unsigned long flash_init(void)
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{
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unsigned long size_b0, size_b1;
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int i;
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unsigned long base_b0, base_b1;
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/* Init: no FLASHes known */
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for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here - FIXME XXX */
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base_b0 = FLASH_BASE0_PRELIM;
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size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0 << 20);
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}
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base_b1 = FLASH_BASE1_PRELIM;
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size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
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return (size_b0 + size_b1);
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}
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void flash_print_info(flash_info_t *info)
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{
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int i;
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int k;
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int size;
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int erased;
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volatile unsigned long *flash;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
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case FLASH_MAN_SST: printf ("SST "); break;
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case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
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break;
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case FLASH_AM040: printf ("AM29LV040B (4 Mbit, uniform sector size)\n");
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break;
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case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
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break;
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case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
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break;
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case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
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break;
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case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
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break;
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case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
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break;
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case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
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break;
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case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
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break;
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case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
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break;
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case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
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break;
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case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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#ifdef CFG_FLASH_EMPTY_INFO
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/*
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* Check if whole sector is erased
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*/
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if (i != (info->sector_count-1))
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size = info->start[i+1] - info->start[i];
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else
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size = info->start[0] + info->size - info->start[i];
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erased = 1;
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flash = (volatile unsigned long *)info->start[i];
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size = size >> 2; /* divide by 4 for longword access */
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for (k=0; k<size; k++) {
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if (*flash++ != 0xffffffff) {
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erased = 0;
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break;
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}
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}
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if ((i % 5) == 0)
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printf ("\n ");
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/* print empty and read-only info */
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printf (" %08lX%s%s",
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info->start[i],
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erased ? " E" : " ",
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info->protect[i] ? "RO " : " ");
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#else
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " ");
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#endif
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}
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printf ("\n");
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return;
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size(vu_long *addr, flash_info_t *info)
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{
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short i;
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short n;
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volatile CFG_FLASH_WORD_SIZE value;
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ulong base = (ulong)addr;
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volatile CFG_FLASH_WORD_SIZE *addr2 = (volatile CFG_FLASH_WORD_SIZE *)addr;
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/* Write auto select command: read Manufacturer ID */
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addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
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addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
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addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
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value = addr2[CFG_FLASH_READ0];
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switch (value) {
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case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
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info->flash_id = FLASH_MAN_AMD;
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break;
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case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
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info->flash_id = FLASH_MAN_FUJ;
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break;
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case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
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info->flash_id = FLASH_MAN_SST;
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break;
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case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
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info->flash_id = FLASH_MAN_EXCEL;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* no or unknown flash */
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}
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value = addr2[CFG_FLASH_READ1]; /* device ID */
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switch (value) {
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
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info->flash_id += FLASH_AM400T;
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info->sector_count = 11;
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info->size = 0x00080000;
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break; /* => 0.5 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
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info->flash_id += FLASH_AM400B;
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info->sector_count = 11;
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info->size = 0x00080000;
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break; /* => 0.5 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV040B:
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info->flash_id += FLASH_AM040;
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info->sector_count = 8;
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info->size = 0x0080000; /* => 512 ko */
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break;
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
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info->flash_id += FLASH_AM800T;
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info->sector_count = 19;
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info->size = 0x00100000;
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break; /* => 1 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
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info->flash_id += FLASH_AM800B;
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info->sector_count = 19;
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info->size = 0x00100000;
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break; /* => 1 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
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info->flash_id += FLASH_AM160T;
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info->sector_count = 35;
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info->size = 0x00200000;
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break; /* => 2 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
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info->flash_id += FLASH_AM160B;
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info->sector_count = 35;
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info->size = 0x00200000;
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break; /* => 2 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
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info->flash_id += FLASH_AM320T;
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info->sector_count = 71;
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info->size = 0x00400000; break; /* => 4 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
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info->flash_id += FLASH_AM320B;
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info->sector_count = 71;
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info->size = 0x00400000; break; /* => 4 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
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info->flash_id += FLASH_AMDL322T;
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info->sector_count = 71;
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info->size = 0x00400000; break; /* => 4 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
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info->flash_id += FLASH_AMDL322B;
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info->sector_count = 71;
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info->size = 0x00400000; break; /* => 4 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
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info->flash_id += FLASH_AMDL323T;
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info->sector_count = 71;
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info->size = 0x00400000; break; /* => 4 MB */
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case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
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info->flash_id += FLASH_AMDL323B;
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info->sector_count = 71;
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info->size = 0x00400000; break; /* => 4 MB */
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case (CFG_FLASH_WORD_SIZE)SST_ID_xF020:
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info->flash_id += FLASH_SST020;
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info->sector_count = 64;
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info->size = 0x00040000;
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break; /* => 256 kB */
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case (CFG_FLASH_WORD_SIZE)SST_ID_xF040:
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info->flash_id += FLASH_SST040;
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info->sector_count = 128;
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info->size = 0x00080000;
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break; /* => 512 kB */
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default:
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info->flash_id = FLASH_UNKNOWN;
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return (0); /* => no or unknown flash */
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}
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/* set up sector start address table */
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if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
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((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
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for (i = 0; i < info->sector_count; i++)
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||||
info->start[i] = base + (i * 0x00001000);
|
||||
} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * 0x00010000);
|
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
|
||||
info->start[i] = base;
|
||||
base += 8 << 10;
|
||||
}
|
||||
while (i < info->sector_count) { /* 64k regular sectors */
|
||||
info->start[i] = base;
|
||||
base += 64 << 10;
|
||||
++i;
|
||||
}
|
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
|
||||
/* set sector offsets for top boot block type */
|
||||
base += info->size;
|
||||
i = info->sector_count;
|
||||
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
|
||||
base -= 8 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
while (i > 0) { /* 64k regular sectors */
|
||||
base -= 64 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
} else {
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00004000;
|
||||
info->start[2] = base + 0x00006000;
|
||||
info->start[3] = base + 0x00008000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00004000;
|
||||
info->start[i--] = base + info->size - 0x00006000;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00010000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
|
||||
info->protect[i] = 0;
|
||||
else
|
||||
info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
|
||||
*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
int flash_erase(flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
printf ("- missing\n");
|
||||
else
|
||||
printf ("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect)
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
|
||||
if (prot)
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
|
||||
else
|
||||
printf ("\n");
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag) {
|
||||
enable_interrupts();
|
||||
flag = 0;
|
||||
}
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
|
||||
(CFG_FLASH_WORD_SIZE)0x00800080) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
|
||||
return (1);
|
||||
}
|
||||
} else {
|
||||
if (sect == s_first) {
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
|
||||
}
|
||||
addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
}
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
|
||||
while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
|
||||
addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i)
|
||||
data = (data << 8) | *src++;
|
||||
if ((rc = write_word(info, wp, data)) != 0)
|
||||
return (rc);
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp)
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word(flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
|
||||
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
|
||||
ulong start;
|
||||
int flag;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data)
|
||||
return (2);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) {
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
|
||||
(data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
113
board/pcs440ep/init.S
Normal file
113
board/pcs440ep/init.S
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_8M 0x00000060
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
|
||||
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
/* PCI */
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
/* USB 2.0 Device */
|
||||
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
tlbtab_end
|
||||
379
board/pcs440ep/pcs440ep.c
Normal file
379
board/pcs440ep/pcs440ep.c
Normal file
|
|
@ -0,0 +1,379 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <spd_sdram.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
static void set_leds(int val)
|
||||
{
|
||||
unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
|
||||
0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
|
||||
out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
register uint reg;
|
||||
|
||||
set_leds(0); /* display boot info counter */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the external bus controller/chip selects
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(ebccfga, xbcfg);
|
||||
reg = mfdcr(ebccfgd);
|
||||
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
|
||||
* via define from board config file.
|
||||
*-------------------------------------------------------------------*/
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic0er, 0x00000000); /* disable all */
|
||||
mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
|
||||
mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */
|
||||
mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */
|
||||
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic1er, 0x00000000); /* disable all */
|
||||
mtdcr(uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
|
||||
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
|
||||
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup other serial configuration
|
||||
*-------------------------------------------------------------------*/
|
||||
mfsdr(sdr_pci0, reg);
|
||||
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
|
||||
mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */
|
||||
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
uint pbcr;
|
||||
int size_val = 0;
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(ebccfga, pb0cr);
|
||||
pbcr = mfdcr(ebccfgd);
|
||||
switch (gd->bd->bi_flashsize) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
case 32 << 20:
|
||||
size_val = 5;
|
||||
break;
|
||||
case 64 << 20:
|
||||
size_val = 6;
|
||||
break;
|
||||
case 128 << 20:
|
||||
size_val = 7;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
|
||||
mtdcr(ebccfga, pb0cr);
|
||||
mtdcr(ebccfgd, pbcr);
|
||||
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[1]);
|
||||
|
||||
/* Env protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
printf("Board: PCS440EP");
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
|
||||
set_leds(1); /* display boot info counter */
|
||||
dram_size = spd_sdram();
|
||||
set_leds(2); /* display boot info counter */
|
||||
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram(void)
|
||||
{
|
||||
unsigned long *mem = (unsigned long *)0;
|
||||
const unsigned long kend = (1024 / sizeof(unsigned long));
|
||||
unsigned long k, n;
|
||||
|
||||
mtmsr(0);
|
||||
|
||||
for (k = 0; k < CFG_KBYTES_SDRAM;
|
||||
++k, mem += (1024 / sizeof(unsigned long))) {
|
||||
if ((k & 1023) == 0) {
|
||||
printf("%3d MB\r", k / 1024);
|
||||
}
|
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0xaaaaaaaa) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
memset(mem, 0x55555555, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0x55555555) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("SDRAM test passes\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned long addr;
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB3 devices to 0.
|
||||
| Set PLB3 arbiter to fair mode.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mfsdr(sdr_amp1, addr);
|
||||
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb3_acr);
|
||||
mtdcr(plb3_acr, addr | 0x80000000);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB4 devices to 0.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mfsdr(sdr_amp0, addr);
|
||||
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
|
||||
mtdcr(plb4_acr, addr);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set Nebula PLB4 arbiter to fair mode.
|
||||
+-------------------------------------------------------------------------*/
|
||||
/* Segment0 */
|
||||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
|
||||
mtdcr(plb0_acr, addr);
|
||||
|
||||
/* Segment1 */
|
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
||||
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
|
||||
mtdcr(plb1_acr, addr);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller *hose)
|
||||
{
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Direct MMIO registers
|
||||
*--------------------------------------------------------------------------*/
|
||||
/*--------------------------------------------------------------------------+
|
||||
| PowerPC440 EP PCI Master configuration.
|
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
|
||||
| Use byte reversed out routines to handle endianess.
|
||||
| Make this region non-prefetchable.
|
||||
+--------------------------------------------------------------------------*/
|
||||
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
||||
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
|
||||
|
||||
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
|
||||
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
|
||||
|
||||
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
|
||||
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Configuration registers
|
||||
*--------------------------------------------------------------------------*/
|
||||
|
||||
/* Program the board's subsystem id/vendor id */
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
CFG_PCI_SUBSYS_VENDORID);
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
|
||||
|
||||
/* Configure command register as bus master */
|
||||
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||
|
||||
/* 240nS PCI clock */
|
||||
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
||||
|
||||
/* No error reporting */
|
||||
pci_write_config_word(0, PCI_ERREN, 0);
|
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_master_init
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
|
||||
void pci_master_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned short temp_short;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs.
|
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||
+--------------------------------------------------------------------------*/
|
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
||||
pci_write_config_word(0, PCI_COMMAND,
|
||||
temp_short | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_MEMORY);
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
/* PCS440EP is always configured as host. */
|
||||
return (1);
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
/*************************************************************************
|
||||
* hw_watchdog_reset
|
||||
*
|
||||
* This routine is called to reset (keep alive) the watchdog timer
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
|
||||
}
|
||||
#endif
|
||||
157
board/pcs440ep/u-boot.lds
Normal file
157
board/pcs440ep/u-boot.lds
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/pcs440ep/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* (C) Copyright 2000-2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -101,6 +101,117 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
# endif
|
||||
#endif /* CFG_INIT_DCACHE_CS */
|
||||
|
||||
#if defined(CFG_440_GPIO_TABLE)
|
||||
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
|
||||
|
||||
void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
|
||||
{
|
||||
unsigned char i=0, j=0, reg_offset = 0, gpio_core;
|
||||
unsigned long gpio_reg, gpio_core_add;
|
||||
|
||||
for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
|
||||
j = 0;
|
||||
reg_offset = 0;
|
||||
/* GPIO config of the GPIOs 0 to 31 */
|
||||
for (i=0; i<GPIO_MAX; i++, j++) {
|
||||
if (i == GPIO_MAX/2) {
|
||||
reg_offset = 4;
|
||||
j = i-16;
|
||||
}
|
||||
|
||||
gpio_core_add = (*gpio_tab)[gpio_core][i].add;
|
||||
|
||||
if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
|
||||
((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
|
||||
|
||||
switch ((*gpio_tab)[gpio_core][i].alt_nb) {
|
||||
case GPIO_SEL:
|
||||
break;
|
||||
|
||||
case GPIO_ALT1:
|
||||
gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
|
||||
out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
|
||||
break;
|
||||
|
||||
case GPIO_ALT2:
|
||||
gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
|
||||
out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
|
||||
break;
|
||||
|
||||
case GPIO_ALT3:
|
||||
gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
|
||||
out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
|
||||
((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
|
||||
|
||||
switch ((*gpio_tab)[gpio_core][i].alt_nb) {
|
||||
case GPIO_SEL:
|
||||
if (gpio_core == GPIO0) {
|
||||
gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
|
||||
out32(GPIO0_TCR, gpio_reg);
|
||||
}
|
||||
|
||||
if (gpio_core == GPIO1) {
|
||||
gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
|
||||
out32(GPIO1_TCR, gpio_reg);
|
||||
}
|
||||
|
||||
gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
|
||||
gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
|
||||
break;
|
||||
|
||||
case GPIO_ALT1:
|
||||
gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
|
||||
out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
|
||||
gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
|
||||
out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
|
||||
break;
|
||||
|
||||
case GPIO_ALT2:
|
||||
gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
|
||||
out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
|
||||
gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
|
||||
out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
|
||||
break;
|
||||
|
||||
case GPIO_ALT3:
|
||||
gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
|
||||
out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
|
||||
gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
|
||||
out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* CFG_440_GPIO_TABLE */
|
||||
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
|
|
@ -129,10 +240,16 @@ cpu_init_f (void)
|
|||
mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
|
||||
#endif /* CONFIG_405EP */
|
||||
|
||||
#if defined(CFG_440_GPIO_TABLE)
|
||||
set_chip_gpio_configuration(&gpio_tab);
|
||||
#endif /* CFG_440_GPIO_TABLE */
|
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
|
||||
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
|
||||
defined(CONFIG_405EP) || defined(CONFIG_405))
|
||||
/*
|
||||
* Move the next instructions into icache, since these modify the flash
|
||||
* we are running from!
|
||||
|
|
@ -148,6 +265,7 @@ cpu_init_f (void)
|
|||
asm volatile(" ori 3, 3, 0xA000" ::: "r3");
|
||||
asm volatile(" mtctr 3" ::: "ctr");
|
||||
asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
|
||||
#endif
|
||||
|
||||
mtebc(pb0ap, CFG_EBC_PB0AP);
|
||||
mtebc(pb0cr, CFG_EBC_PB0CR);
|
||||
|
|
|
|||
|
|
@ -1198,12 +1198,19 @@ ppcSync:
|
|||
.globl relocate_code
|
||||
relocate_code:
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
dccci 0,0 /* Invalidate data cache, now no longer our stack */
|
||||
/*
|
||||
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
|
||||
* to speed up the boot process. Now this cache needs to be disabled.
|
||||
*/
|
||||
iccci 0,0 /* Invalidate inst cache */
|
||||
dccci 0,0 /* Invalidate data cache, now no longer our stack */
|
||||
sync
|
||||
isync
|
||||
addi r1,r0,0x0000 /* TLB entry #0 */
|
||||
tlbre r0,r1,0x0002 /* Read contents */
|
||||
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
|
||||
tlbwe r0,r1,0x0002 /* Save it out */
|
||||
sync
|
||||
isync
|
||||
#endif
|
||||
mr r1, r3 /* Set new stack pointer */
|
||||
|
|
|
|||
413
include/configs/pcs440ep.h
Normal file
413
include/configs/pcs440ep.h
Normal file
|
|
@ -0,0 +1,413 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* pcs440ep.h - configuration for PCS440EP board
|
||||
***********************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
|
||||
#define CONFIG_440EP 1 /* Specific PPC440EP support */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
|
||||
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
|
||||
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
|
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
|
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
|
||||
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
|
||||
|
||||
/*Don't change either of these*/
|
||||
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
|
||||
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
|
||||
/*Don't change either of these*/
|
||||
|
||||
#define CFG_USB_DEVICE 0x50000000
|
||||
#define CFG_BOOT_BASE_ADDR 0xf0000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in SDRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
|
||||
#define CFG_INIT_RAM_END (8 << 10)
|
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* no external clk used */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
/*define this if you want console on UART1*/
|
||||
#undef CONFIG_UART1_CONSOLE
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
|
||||
#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
|
||||
#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#endif /* CFG_ENV_IS_IN_FLASH */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
|
||||
#undef CONFIG_DDR_ECC /* don't use ECC */
|
||||
#define SPD_EEPROM_ADDRESS {0x50, 0x51}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CFG_I2C_MULTI_EEPROMS
|
||||
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=pcs440ep\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=/tftpboot/pcs440ep/uImage\0" \
|
||||
"kernel_addr=fff00000\0" \
|
||||
"ramdisk_addr=fff00000\0" \
|
||||
"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \
|
||||
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
|
||||
"cp.b 100000 fff80000 80000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_NET_MULTI 1 /* required for netconsole */
|
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
|
||||
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
|
||||
#define CONFIG_PHY1_ADDR 2
|
||||
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
|
||||
/* Partitions */
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
#ifdef CONFIG_440EP
|
||||
/* USB */
|
||||
#define CONFIG_USB_OHCI
|
||||
#define CONFIG_USB_STORAGE
|
||||
|
||||
/*Comment this out to enable USB 1.1 device*/
|
||||
#define USB_2_0_DEVICE
|
||||
#endif /*CONFIG_440EP*/
|
||||
|
||||
#ifdef DEBUG
|
||||
#define CONFIG_PANIC_HANG
|
||||
#else
|
||||
#define CONFIG_HW_WATCHDOG /* watchdog */
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SDRAM | \
|
||||
CFG_CMD_EXT2 | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_USB )
|
||||
|
||||
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
#define CONFIG_LYNXKDI 1 /* support kdi files */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
#define CFG_PCI_TARGET_INIT
|
||||
#define CFG_PCI_MASTER_INIT
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */
|
||||
|
||||
#define CFG_FLASH FLASH_BASE0_PRELIM
|
||||
#define CFG_SRAM 0xF1000000
|
||||
#define CFG_FPGA 0xF2000000
|
||||
#define CFG_CF1 0xF0000000
|
||||
#define CFG_CF2 0xF0100000
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */
|
||||
#define CFG_EBC_PB0CR (CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 1 (SRAM) initialization */
|
||||
#define CFG_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */
|
||||
#define CFG_EBC_PB1CR (CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 2 (FPGA) initialization */
|
||||
#define CFG_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */
|
||||
#define CFG_EBC_PB2CR (CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 3 (CompactFlash) initialization */
|
||||
#define CFG_EBC_PB3AP 0x080BD400
|
||||
#define CFG_EBC_PB3CR (CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 4 (CompactFlash) initialization */
|
||||
#define CFG_EBC_PB4AP 0x080BD400
|
||||
#define CFG_EBC_PB4CR (CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PPC440 GPIO Configuration
|
||||
*/
|
||||
#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
|
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \
|
||||
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
|
||||
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
|
||||
}, \
|
||||
{ \
|
||||
/* GPIO Core 1 */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \
|
||||
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
|
||||
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \
|
||||
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
|
||||
{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \
|
||||
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \
|
||||
} \
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
134
include/ppc440.h
134
include/ppc440.h
|
|
@ -1357,56 +1357,106 @@
|
|||
/******************************************************************************
|
||||
* GPIO macro register defines
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_440GP)
|
||||
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700)
|
||||
#define GPIO0 0
|
||||
#define GPIO1 1
|
||||
|
||||
#define GPIO0_OR (GPIO_BASE0+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE0+0x4)
|
||||
#define GPIO0_ODR (GPIO_BASE0+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE0+0x1C)
|
||||
#if defined(CONFIG_440GP)
|
||||
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
|
||||
|
||||
#define GPIO0_OR (GPIO0_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO0_BASE+0x4)
|
||||
#define GPIO0_ODR (GPIO0_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO0_BASE+0x1C)
|
||||
#endif /* CONFIG_440GP */
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
|
||||
#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)
|
||||
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
|
||||
#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
|
||||
|
||||
#define GPIO0_OR (GPIO_BASE0+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE0+0x4)
|
||||
#define GPIO0_OSRL (GPIO_BASE0+0x8)
|
||||
#define GPIO0_OSRH (GPIO_BASE0+0xC)
|
||||
#define GPIO0_TSRL (GPIO_BASE0+0x10)
|
||||
#define GPIO0_TSRH (GPIO_BASE0+0x14)
|
||||
#define GPIO0_ODR (GPIO_BASE0+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE0+0x1C)
|
||||
#define GPIO0_RR1 (GPIO_BASE0+0x20)
|
||||
#define GPIO0_RR2 (GPIO_BASE0+0x24)
|
||||
#define GPIO0_RR3 (GPIO_BASE0+0x28)
|
||||
#define GPIO0_ISR1L (GPIO_BASE0+0x30)
|
||||
#define GPIO0_ISR1H (GPIO_BASE0+0x34)
|
||||
#define GPIO0_ISR2L (GPIO_BASE0+0x38)
|
||||
#define GPIO0_ISR2H (GPIO_BASE0+0x3C)
|
||||
#define GPIO0_ISR3L (GPIO_BASE0+0x40)
|
||||
#define GPIO0_ISR3H (GPIO_BASE0+0x44)
|
||||
/* Offsets */
|
||||
#define GPIOx_OR 0x00 /* GPIO Output Register */
|
||||
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
|
||||
#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
|
||||
#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
|
||||
#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
|
||||
#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
|
||||
#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
|
||||
#define GPIOx_IR 0x1C /* GPIO Input Register */
|
||||
#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
|
||||
#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
|
||||
#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
|
||||
#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
|
||||
#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
|
||||
#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
|
||||
#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
|
||||
#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
|
||||
#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
|
||||
|
||||
#define GPIO1_OR (GPIO_BASE1+0x0)
|
||||
#define GPIO1_TCR (GPIO_BASE1+0x4)
|
||||
#define GPIO1_OSRL (GPIO_BASE1+0x8)
|
||||
#define GPIO1_OSRH (GPIO_BASE1+0xC)
|
||||
#define GPIO1_TSRL (GPIO_BASE1+0x10)
|
||||
#define GPIO1_TSRH (GPIO_BASE1+0x14)
|
||||
#define GPIO1_ODR (GPIO_BASE1+0x18)
|
||||
#define GPIO1_IR (GPIO_BASE1+0x1C)
|
||||
#define GPIO1_RR1 (GPIO_BASE1+0x20)
|
||||
#define GPIO1_RR2 (GPIO_BASE1+0x24)
|
||||
#define GPIO1_RR3 (GPIO_BASE1+0x28)
|
||||
#define GPIO1_ISR1L (GPIO_BASE1+0x30)
|
||||
#define GPIO1_ISR1H (GPIO_BASE1+0x34)
|
||||
#define GPIO1_ISR2L (GPIO_BASE1+0x38)
|
||||
#define GPIO1_ISR2H (GPIO_BASE1+0x3C)
|
||||
#define GPIO1_ISR3L (GPIO_BASE1+0x40)
|
||||
#define GPIO1_ISR3H (GPIO_BASE1+0x44)
|
||||
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
|
||||
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
|
||||
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
|
||||
#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
|
||||
#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
|
||||
|
||||
#define GPIO0_OR (GPIO0_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO0_BASE+0x4)
|
||||
#define GPIO0_OSRL (GPIO0_BASE+0x8)
|
||||
#define GPIO0_OSRH (GPIO0_BASE+0xC)
|
||||
#define GPIO0_TSRL (GPIO0_BASE+0x10)
|
||||
#define GPIO0_TSRH (GPIO0_BASE+0x14)
|
||||
#define GPIO0_ODR (GPIO0_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO0_BASE+0x1C)
|
||||
#define GPIO0_RR1 (GPIO0_BASE+0x20)
|
||||
#define GPIO0_RR2 (GPIO0_BASE+0x24)
|
||||
#define GPIO0_RR3 (GPIO0_BASE+0x28)
|
||||
#define GPIO0_ISR1L (GPIO0_BASE+0x30)
|
||||
#define GPIO0_ISR1H (GPIO0_BASE+0x34)
|
||||
#define GPIO0_ISR2L (GPIO0_BASE+0x38)
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||||
#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
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#define GPIO0_ISR3L (GPIO0_BASE+0x40)
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||||
#define GPIO0_ISR3H (GPIO0_BASE+0x44)
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||||
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||||
#define GPIO1_OR (GPIO1_BASE+0x0)
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||||
#define GPIO1_TCR (GPIO1_BASE+0x4)
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#define GPIO1_OSRL (GPIO1_BASE+0x8)
|
||||
#define GPIO1_OSRH (GPIO1_BASE+0xC)
|
||||
#define GPIO1_TSRL (GPIO1_BASE+0x10)
|
||||
#define GPIO1_TSRH (GPIO1_BASE+0x14)
|
||||
#define GPIO1_ODR (GPIO1_BASE+0x18)
|
||||
#define GPIO1_IR (GPIO1_BASE+0x1C)
|
||||
#define GPIO1_RR1 (GPIO1_BASE+0x20)
|
||||
#define GPIO1_RR2 (GPIO1_BASE+0x24)
|
||||
#define GPIO1_RR3 (GPIO1_BASE+0x28)
|
||||
#define GPIO1_ISR1L (GPIO1_BASE+0x30)
|
||||
#define GPIO1_ISR1H (GPIO1_BASE+0x34)
|
||||
#define GPIO1_ISR2L (GPIO1_BASE+0x38)
|
||||
#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
|
||||
#define GPIO1_ISR3L (GPIO1_BASE+0x40)
|
||||
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
|
||||
#endif
|
||||
|
||||
#define GPIO_GROUP_MAX 2
|
||||
#define GPIO_MAX 32
|
||||
#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
|
||||
#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
|
||||
#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
|
||||
#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
|
||||
#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
|
||||
/* For the other GPIO number, you must shift */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
|
||||
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
|
||||
|
||||
typedef struct { unsigned long add; /* gpio core base address */
|
||||
gpio_driver_t in_out; /* Driver Setting */
|
||||
gpio_select_t alt_nb; /* Selected Alternate */
|
||||
} gpio_param_s;
|
||||
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* Macros for accessing the indirect EBC registers
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue