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https://github.com/AsahiLinux/u-boot
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ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
4dbee8a90d
commit
97923770cb
4 changed files with 79 additions and 51 deletions
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@ -31,7 +31,8 @@
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#include <common.h>
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#include <pci.h>
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#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
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#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX)) && \
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defined(CONFIG_PCI)
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#include <asm/4xx_pcie.h>
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@ -55,8 +56,10 @@ static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
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base = (u8*)CFG_PCIE0_XCFGBASE;
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if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
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base = (u8*)CFG_PCIE1_XCFGBASE;
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#if CFG_PCIE_NR_PORTS > 2
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if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
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base = (u8*)CFG_PCIE2_XCFGBASE;
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#endif
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}
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return base;
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@ -68,8 +71,10 @@ static void pcie_dmer_disable(void)
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mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
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mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
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mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
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#if CFG_PCIE_NR_PORTS > 2
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mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
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mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
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#endif
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}
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static void pcie_dmer_enable(void)
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@ -78,8 +83,10 @@ static void pcie_dmer_enable(void)
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mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
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mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
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mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
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#if CFG_PCIE_NR_PORTS > 2
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mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
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mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
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#endif
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}
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static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
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@ -120,6 +127,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
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*/
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pcie_dmer_disable ();
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debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
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switch (len) {
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case 1:
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*val = in_8(hose->cfg_data + offset);
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@ -227,6 +235,7 @@ int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset
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return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
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}
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#if defined(CONFIG_440SPE)
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static void ppc4xx_setup_utl(u32 port) {
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volatile void *utl_base = NULL;
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@ -371,6 +380,15 @@ int ppc4xx_init_pcie(void)
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}
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return 0;
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}
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#else
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int ppc4xx_init_pcie(void)
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{
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/*
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* Nothing to do on 405EX
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*/
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return 0;
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}
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#endif
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/*
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* Board-specific pcie initialization
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@ -608,19 +626,21 @@ int ppc4xx_init_pcie_port(int port, int rootport)
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return -1;
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}
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#if defined(CONFIG_440SPE)
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/*
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* Setup UTL registers - but only on revA!
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* We use default settings for revB chip.
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*/
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if (!ppc440spe_revB())
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ppc4xx_setup_utl(port);
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#endif
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/*
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* We map PCI Express configuration access into the 512MB regions
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*/
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addr = ppc4xx_get_cfgaddr(port);
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low = (u32)(addr & 0x00000000ffffffff);
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high = (u32)(addr >> 32);
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low = U64_TO_U32_LOW(addr);
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high = U64_TO_U32_HIGH(addr);
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switch (port) {
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case 0:
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@ -633,11 +653,13 @@ int ppc4xx_init_pcie_port(int port, int rootport)
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
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mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
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break;
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#if CFG_PCIE_NR_PORTS > 2
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case 2:
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
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mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
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break;
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#endif
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}
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/*
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@ -692,11 +714,13 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
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rmbase = (u32 *)CFG_PCIE1_CFGBASE;
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hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
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break;
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#if CFG_PCIE_NR_PORTS > 2
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case 2:
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mbase = (u32 *)CFG_PCIE2_XCFGBASE;
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rmbase = (u32 *)CFG_PCIE2_CFGBASE;
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hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
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break;
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#endif
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}
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/*
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@ -720,8 +744,8 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
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switch (port) {
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case 0:
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
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port * CFG_PCIE_MEMSIZE);
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mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
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mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
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@ -733,8 +757,8 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
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mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
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break;
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case 1:
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
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port * CFG_PCIE_MEMSIZE);
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mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
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mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
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@ -745,9 +769,10 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
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mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
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mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
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break;
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#if CFG_PCIE_NR_PORTS > 2
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case 2:
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
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port * CFG_PCIE_MEMSIZE);
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mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
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mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
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@ -758,6 +783,7 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
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mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
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mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
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break;
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#endif
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}
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/* Set up 16GB inbound memory window at 0 */
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@ -770,8 +796,8 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
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out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
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out_le32(mbase + PECFG_PIM0LAL, 0);
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out_le32(mbase + PECFG_PIM0LAH, 0);
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out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
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out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
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out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
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out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
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out_le32(mbase + PECFG_PIMEN, 0x1);
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/* Enable I/O, Mem, and Busmaster cycles */
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@ -780,23 +806,8 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Set Device and Vendor Id */
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switch (port) {
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case 0:
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out_le16(mbase + 0x200, 0xaaa0);
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out_le16(mbase + 0x202, 0xbed0);
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break;
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case 1:
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out_le16(mbase + 0x200, 0xaaa1);
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out_le16(mbase + 0x202, 0xbed1);
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break;
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case 2:
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out_le16(mbase + 0x200, 0xaaa2);
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out_le16(mbase + 0x202, 0xbed2);
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break;
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default:
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out_le16(mbase + 0x200, 0xaaa3);
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out_le16(mbase + 0x202, 0xbed3);
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}
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out_le16(mbase + 0x200, 0xaaa0 + port);
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out_le16(mbase + 0x202, 0xbed0 + port);
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/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
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out_le32(mbase + 0x208, 0x06040001);
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@ -826,10 +837,12 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
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mbase = (u32 *)CFG_PCIE1_XCFGBASE;
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hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
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break;
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#if defined(CFG_PCIE2_CFGBASE)
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case 2:
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mbase = (u32 *)CFG_PCIE2_XCFGBASE;
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hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
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break;
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#endif
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}
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/*
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@ -843,29 +856,31 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
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switch (port) {
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case 0:
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
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port * CFG_PCIE_MEMSIZE);
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mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
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mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
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~(CFG_PCIE_MEMSIZE - 1) | 3);
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break;
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case 1:
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
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port * CFG_PCIE_MEMSIZE);
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mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
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mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
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~(CFG_PCIE_MEMSIZE - 1) | 3);
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break;
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#if CFG_PCIE_NR_PORTS > 2
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case 2:
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
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mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
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mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
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port * CFG_PCIE_MEMSIZE);
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mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
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mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
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~(CFG_PCIE_MEMSIZE - 1) | 3);
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break;
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#endif
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}
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/* Set up 16GB inbound memory window at 0 */
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@ -873,16 +888,16 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
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out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
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out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
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out_le32(mbase + PECFG_BAR0LMPA, 0);
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out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
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out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
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out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
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out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
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out_le32(mbase + PECFG_PIMEN, 0x1);
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/* Enable I/O, Mem, and Busmaster cycles */
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out_le16((u16 *)(mbase + PCI_COMMAND),
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in_le16((u16 *)(mbase + PCI_COMMAND)) |
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
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out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
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out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
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out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
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attempts = 10;
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while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
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@ -893,7 +908,7 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
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mdelay(1000);
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}
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printf("PCIE:%d successfully set as endpoint\n",port);
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printf("PCIE:%d successfully set as endpoint\n", port);
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return 0;
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}
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@ -16,14 +16,29 @@
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#define DCRN_SDR0_CFGDATA 0x00f
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#if defined(CONFIG_440SPE)
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#define CFG_PCIE_NR_PORTS 3
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#define CFG_PCIE_ADDR_HIGH 0x0000000d
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#define DCRN_PCIE0_BASE 0x100
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#define DCRN_PCIE1_BASE 0x120
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#define DCRN_PCIE2_BASE 0x140
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#define PCIE0_SDR 0x300
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#define PCIE1_SDR 0x340
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#define PCIE2_SDR 0x370
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#endif
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#if defined(CONFIG_405EX)
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#define CFG_PCIE_NR_PORTS 2
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#define CFG_PCIE_ADDR_HIGH 0x00000000
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#define DCRN_PCIE0_BASE 0x040
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#define DCRN_PCIE1_BASE 0x060
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#define PCIE0_SDR 0x400
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#define PCIE1_SDR 0x440
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#endif
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#define PCIE0 DCRN_PCIE0_BASE
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@ -53,17 +68,6 @@
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#define PESDR0_PLLLCT2 0x03a1
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#define PESDR0_PLLLCT3 0x03a2
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#if defined(CONFIG_440SPE)
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#define PCIE0_SDR 0x300
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#define PCIE1_SDR 0x340
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#define PCIE2_SDR 0x370
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#endif
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#if defined(CONFIG_405EX)
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#define PCIE0_SDR 0x400
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#define PCIE1_SDR 0x440
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#endif
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/* common regs, at least for 405EX and 440SPe */
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#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
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#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
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@ -237,6 +241,9 @@
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#define GPL_DMER_MASK_DISA 0x02000000
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#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
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#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
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int ppc4xx_init_pcie(void);
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int ppc4xx_init_pcie_rootport(int port);
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int ppc4xx_init_pcie_endport(int port);
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@ -260,7 +267,7 @@ static inline u32 sdr_base(int port)
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return PCIE0_SDR;
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case 1:
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return PCIE1_SDR;
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#if defined(PCIE2_SDR)
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#if CFG_PCIE_NR_PORTS > 2
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case 2:
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return PCIE2_SDR;
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#endif
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@ -72,6 +72,9 @@
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#define CFG_PCIE1_XCFGBASE 0xc3001000
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#define CFG_PCIE2_XCFGBASE 0xc3002000
|
||||
|
||||
/* base address of inbound PCIe window */
|
||||
#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL
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||||
|
||||
/* System RAM mapped to PCI space */
|
||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
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||||
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
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||||
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|
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|||
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|
@ -74,6 +74,9 @@
|
|||
#define CFG_PCIE1_XCFGBASE 0xc3001000
|
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#define CFG_PCIE2_XCFGBASE 0xc3002000
|
||||
|
||||
/* base address of inbound PCIe window */
|
||||
#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL
|
||||
|
||||
/* System RAM mapped to PCI space */
|
||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
|
||||
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
|
||||
|
|
|
|||
Loading…
Reference in a new issue