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[ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A

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This brings back separate settings for PCIe bus numbers depending on chip
revision, which got eliminated in 2b393b0f0a
commit. 440SPe rev. A does NOT work properly with the same settings as for
the rev. B (no devices are seen on the bus during enumeration).

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
This commit is contained in:
Rafal Jaworowski 2007-07-31 18:19:54 +02:00 • committed by Stefan Roese
parent d2f6800662
commit dec99558b9
1 changed files with 8 additions and 3 deletions
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11
cpu/ppc4xx/440spe_pcie.c
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@ -783,9 +783,14 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
/*
* Set bus numbers on our root port
*/
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
if (ppc440spe_revB()) {
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
} else {
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
}
/*
* Set up outbound translation to hose->mem_space from PLB