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https://github.com/AsahiLinux/u-boot
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Coding stylke cleanup; update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
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6 changed files with 87 additions and 26 deletions
65
CHANGELOG
65
CHANGELOG
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@ -1,9 +1,44 @@
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commit 885ec89b648a899a2f32393fd3ffd9f7234c4402
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Author: Wolfgang Denk <wd@denx.de>
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Date: Sat May 5 18:05:02 2007 +0200
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Add STX GP3 SSA board to MAKEALL script; update CHANGELOG.
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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commit 5499645b3fe17a548af9dfc479ca6e2455f179a2
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Author: Wolfgang Denk <wd@denx.de>
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Date: Sat May 5 17:15:50 2007 +0200
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Make "file" command happy with some config.mk files; update CHANGELOG
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commit e3b8c78bc2489c27ae020986ef0eaca684866cef
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Author: Jeffrey Mann <mannj@embeddedplanet.com>
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Date: Sat May 5 08:32:14 2007 +0200
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ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHz
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The AMCC Secquoia board has been changed in a new revision from using a
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33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD
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indicates the difference. This patch reads that bit and uses the correct
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clock speed for the board. This code is backward compatable will all
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prior boards. All prior boards will be read as 33.000.
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Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit f544ff6656fca263ed1ebe39899b6d95da67c8b8
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Author: Stefan Roese <sr@denx.de>
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Date: Sat May 5 08:29:01 2007 +0200
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ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting
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Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
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for the 4k NAND boot image so define bus_frequency to 133MHz here
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which is save for the refresh counter setup.
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit a79886590593ba1d667c840caa4940c61639f18f
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Author: Thomas Knobloch <knobloch@siemens.com>
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Date: Sat May 5 07:04:42 2007 +0200
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@ -124,6 +159,22 @@ Date: Fri Mar 16 13:02:53 2007 -0500
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Signed-off-by: James Yang <James.Yang@freescale.com>
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Signed-off-by: Jon Loeliger <jdl@freescale.com>
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commit 8b39501d28754e72726ce7fb02310e56dbdf116a
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Author: Stefan Roese <sr@denx.de>
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Date: Sun Apr 29 14:13:01 2007 +0200
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ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driver
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit 37ed6cdd4159195bfad68d8a237f6adda8f482cb
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Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Date: Tue Apr 24 14:03:45 2007 +0200
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ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.
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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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commit 66ed6cca3f340f7a8a06d9272ae2ef8e96f0273d
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Author: Andy Fleming <afleming@freescale.com>
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Date: Mon Apr 23 02:37:47 2007 -0500
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@ -429,6 +480,20 @@ Date: Thu Apr 19 23:14:39 2007 -0400
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Also moved the libfdt.a requirement into the main Makefile. That is
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The U-Boot Way.
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commit d21686263574e95cb3e9e9b0496f968b1b897fdb
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Author: Stefan Roese <sr@denx.de>
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Date: Thu Apr 19 09:53:52 2007 +0200
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ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai
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Previous versions used full wait states for the chip select #1 which
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is connected to the Xilinix SystemACE controller on the AMCC Katmai
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evaluation board. This leads to really slow access and therefore low
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performance. This patch now sets up the chip select a lot faster
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resulting in much better read/write performance of the Linux driver.
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit 37837828d89084879bee2f2b8c7c68d4695940df
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Author: Wolfgang Denk <wd@denx.de>
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Date: Wed Apr 18 17:49:29 2007 +0200
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@ -52,7 +52,7 @@ int checkboard (void)
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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if ((uint)&gur->porpllsr != 0xe00e0000) {
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if ((uint)&gur->porpllsr != 0xe00e0000) {
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printf("immap size error %x\n",&gur->porpllsr);
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}
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printf ("Board: MPC8544DS\n");
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@ -79,7 +79,6 @@ initdram(int board_type)
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return dram_size;
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}
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#if defined(CFG_DRAM_TEST)
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int
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testdram(void)
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@ -119,8 +118,6 @@ testdram(void)
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}
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#endif
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int last_stage_init(void)
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{
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return 0;
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@ -190,16 +187,15 @@ get_board_sys_clk(ulong dummy)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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u32 *p;
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int len;
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u32 *p;
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int len;
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ft_cpu_setup(blob, bd);
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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}
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#endif
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@ -71,14 +71,14 @@ int checkcpu (void)
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puts("8548_E");
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break;
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case SVR_8544:
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puts("8544");
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break;
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case SVR_8544_E:
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puts("8544_E");
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break;
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case SVR_8568_E:
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puts("8568_E");
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break;
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puts("8544");
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break;
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case SVR_8544_E:
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puts("8544_E");
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break;
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case SVR_8568_E:
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puts("8568_E");
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break;
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default:
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puts("Unknown");
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break;
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@ -157,7 +157,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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/* e500 v2 core has reset control register */
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volatile unsigned int * rstcr;
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rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
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*rstcr = 0x2; /* HRESET_REQ */
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*rstcr = 0x2; /* HRESET_REQ */
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}else{
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/*
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* Initiate hard reset in debug control register DBCR0
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@ -344,7 +344,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
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mfsdr(sdr_pfc1, pfc1);
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pfc1 &= SDR0_PFC1_SELECT_MASK;
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switch (pfc1) {
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switch (pfc1) {
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case SDR0_PFC1_SELECT_CONFIG_2:
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/* 1 x GMII port */
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out32 (ZMII_FER, 0x00);
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@ -361,7 +361,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
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break;
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case SDR0_PFC1_SELECT_CONFIG_6:
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/* 2 x SMII ports */
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out32 (ZMII_FER,
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out32 (ZMII_FER,
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((ZMII_FER_SMII) << ZMII_FER_V(0)) |
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((ZMII_FER_SMII) << ZMII_FER_V(1)));
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out32 (RGMII_FER, 0x00000000);
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@ -67,7 +67,7 @@ struct tsec_info_struct {
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static struct tsec_info_struct tsec_info[] = {
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#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
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#if defined(CONFIG_MPC8544DS)
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{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
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{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
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#else
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{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
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#endif
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@ -149,7 +149,7 @@ extern unsigned long get_clock_freq(void);
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#define CFG_BR1_PRELIM 0xf8000801
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#define CFG_OR1_PRELIM 0xffffe9f7
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//#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
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/*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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