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https://github.com/AsahiLinux/u-boot
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[PATCH] Add AMCC PPC405EZ support
This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
87ed3bfb42
commit
e01bd218b0
12 changed files with 979 additions and 151 deletions
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@ -1333,6 +1333,9 @@ int enetInt (struct eth_device *dev)
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}
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}
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mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
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#if defined(CONFIG_405EZ)
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mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
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#endif /* defined(CONFIG_405EZ) */
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}
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while (serviced);
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@ -47,6 +47,9 @@ void board_reset(void);
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#if defined(CONFIG_440)
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#define FREQ_EBC (sys_info.freqEPB)
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#elif defined(CONFIG_405EZ)
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#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
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sys_info.pllExtBusDiv)
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#else
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#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
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#endif
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@ -209,7 +212,8 @@ int checkcpu (void)
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puts("AMCC PowerPC 4");
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ)
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puts("05");
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#endif
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#if defined(CONFIG_440)
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@ -257,6 +261,10 @@ int checkcpu (void)
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puts("EP Rev. B");
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break;
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case PVR_405EZ_RA:
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puts("EZ Rev. A");
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break;
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#if defined(CONFIG_440)
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case PVR_440GP_RB:
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puts("GP Rev. B");
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@ -386,9 +394,9 @@ int checkcpu (void)
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}
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printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
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sys_info.freqPLB / 1000000,
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sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
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FREQ_EBC / 1000000);
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sys_info.freqPLB / 1000000,
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get_OPB_freq() / 1000000,
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FREQ_EBC / 1000000);
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if (addstr[0] != 0)
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printf(" %s\n", addstr);
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@ -418,7 +426,7 @@ int checkcpu (void)
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putc('\n');
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#endif
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#if defined(CONFIG_405EP)
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#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
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printf (" 16 kB I-Cache 16 kB D-Cache");
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#elif defined(CONFIG_440)
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printf (" 32 kB I-Cache 32 kB D-Cache");
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@ -256,7 +256,8 @@ cpu_init_f (void)
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*/
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#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
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#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405))
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_405))
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/*
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* Move the next instructions into icache, since these modify the flash
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* we are running from!
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@ -264,7 +264,8 @@ int serial_tstc ()
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#endif /* CONFIG_IOP480 */
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/*****************************************************************************/
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_440)
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#if defined(CONFIG_440)
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@ -309,7 +310,7 @@ int serial_tstc ()
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#define MFREG(a, d) mfsdr(a, d)
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#define MTREG(a, d) mtsdr(a, d)
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#endif /* #if defined(CONFIG_440GP) */
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#elif defined(CONFIG_405EP)
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#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define UCR0_MASK 0x0000007f
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@ -392,47 +393,95 @@ volatile static serial_buffer_t buf_info;
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#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
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static void serial_divs (int baudrate, unsigned long *pudiv,
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unsigned short *pbdiv )
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unsigned short *pbdiv)
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{
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sys_info_t sysinfo;
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sys_info_t sysinfo;
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unsigned long div; /* total divisor udiv * bdiv */
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unsigned long umin; /* minimum udiv */
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unsigned short diff; /* smallest diff */
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unsigned long udiv; /* best udiv */
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unsigned short idiff; /* current diff */
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unsigned short ibdiv; /* current bdiv */
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unsigned short diff; /* smallest diff */
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unsigned long udiv; /* best udiv */
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unsigned short idiff; /* current diff */
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unsigned short ibdiv; /* current bdiv */
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unsigned long i;
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unsigned long est; /* current estimate */
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unsigned long est; /* current estimate */
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get_sys_info( &sysinfo );
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get_sys_info(&sysinfo);
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udiv = 32; /* Assume lowest possible serial clk */
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div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
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umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
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diff = 32; /* highest possible */
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udiv = 32; /* Assume lowest possible serial clk */
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div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
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umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
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diff = 32; /* highest possible */
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/* i is the test udiv value -- start with the largest
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* possible (32) to minimize serial clock and constrain
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* search to umin.
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*/
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for( i = 32; i > umin; i-- ){
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ibdiv = div/i;
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for (i = 32; i > umin; i--) {
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ibdiv = div / i;
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est = i * ibdiv;
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idiff = (est > div) ? (est-div) : (div-est);
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if( idiff == 0 ){
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if (idiff == 0) {
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udiv = i;
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break; /* can't do better */
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}
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else if( idiff < diff ){
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} else if (idiff < diff) {
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udiv = i; /* best so far */
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diff = idiff; /* update lowest diff*/
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}
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}
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*pudiv = udiv;
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*pbdiv = div/udiv;
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*pbdiv = div / udiv;
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}
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#elif defined(CONFIG_405EZ)
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static void serial_divs (int baudrate, unsigned long *pudiv,
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unsigned short *pbdiv)
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{
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sys_info_t sysinfo;
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unsigned long div; /* total divisor udiv * bdiv */
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unsigned long umin; /* minimum udiv */
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unsigned short diff; /* smallest diff */
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unsigned long udiv; /* best udiv */
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unsigned short idiff; /* current diff */
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unsigned short ibdiv; /* current bdiv */
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unsigned long i;
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unsigned long est; /* current estimate */
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unsigned long plloutb;
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u32 reg;
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get_sys_info(&sysinfo);
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plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv)
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/ sysinfo.pllFwdDivB);
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udiv = 256; /* Assume lowest possible serial clk */
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div = plloutb / (16 * baudrate); /* total divisor */
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umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
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diff = 256; /* highest possible */
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/* i is the test udiv value -- start with the largest
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* possible (256) to minimize serial clock and constrain
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* search to umin.
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*/
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for (i = 256; i > umin; i--) {
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ibdiv = div / i;
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est = i * ibdiv;
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idiff = (est > div) ? (est-div) : (div-est);
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if (idiff == 0) {
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udiv = i;
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break; /* can't do better */
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} else if (idiff < diff) {
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udiv = i; /* best so far */
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diff = idiff; /* update lowest diff*/
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}
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}
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*pudiv = udiv;
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mfcpr(cprperd0, reg);
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reg &= ~0x0000ffff;
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reg |= ((udiv - 0) << 8) | (udiv - 0);
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mtcpr(cprperd0, reg);
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*pbdiv = div / udiv;
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}
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#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
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@ -518,6 +567,10 @@ int serial_init (void)
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unsigned short bdiv;
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volatile char val;
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#if defined(CONFIG_405EZ)
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serial_divs(gd->baudrate, &udiv, &bdiv);
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clk = tmp = reg = 0;
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#else
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#ifdef CONFIG_405EP
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reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
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clk = gd->cpu_clk;
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@ -548,9 +601,9 @@ int serial_init (void)
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reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
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mtdcr (cntrl0, reg);
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#endif /* CONFIG_405EP */
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tmp = gd->baudrate * udiv * 16;
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bdiv = (clk + tmp / 2) / tmp;
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#endif /* CONFIG_405EZ */
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out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
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out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
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@ -767,11 +767,119 @@ ulong get_PCI_freq (void)
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return val;
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}
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#elif defined(CONFIG_405EZ)
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void get_sys_info (PPC405_SYS_INFO * sysInfo)
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{
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unsigned long cpr_plld;
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unsigned long cpr_primad;
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unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
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unsigned long primad_cpudv;
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unsigned long m;
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/*
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* Read PLL Mode registers
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*/
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mfcpr(cprplld, cpr_plld);
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/*
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* Determine forward divider A
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*/
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sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
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/*
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* Determine forward divider B (should be equal to A)
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*/
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sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
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if (sysInfo->pllFwdDivB == 0) {
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sysInfo->pllFwdDivB = 8;
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}
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/*
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* Determine FBK_DIV.
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*/
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sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
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if (sysInfo->pllFbkDiv == 0) {
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sysInfo->pllFbkDiv = 256;
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}
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/*
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* Read CPR_PRIMAD register
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*/
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mfcpr(cprprimad, cpr_primad);
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/*
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* Determine PLB_DIV.
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*/
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sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
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if (sysInfo->pllPlbDiv == 0) {
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sysInfo->pllPlbDiv = 16;
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}
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/*
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* Determine EXTBUS_DIV.
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*/
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sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
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if (sysInfo->pllExtBusDiv == 0) {
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sysInfo->pllExtBusDiv = 16;
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}
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/*
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* Determine OPB_DIV.
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*/
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sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
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if (sysInfo->pllOpbDiv == 0) {
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sysInfo->pllOpbDiv = 16;
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}
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/*
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* Determine the M factor
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*/
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
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/*
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* Determine VCO clock frequency
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*/
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sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
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(unsigned long long)sysClkPeriodPs;
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/*
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* Determine CPU clock frequency
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*/
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primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
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if (primad_cpudv == 0) {
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primad_cpudv = 16;
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}
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sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv;
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/*
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* Determine PLB clock frequency
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*/
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sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv;
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}
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/********************************************
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* get_OPB_freq
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* return OPB bus freq in Hz
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*********************************************/
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ulong get_OPB_freq (void)
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{
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ulong val = 0;
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PPC405_SYS_INFO sys_info;
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get_sys_info (&sys_info);
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val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv;
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return val;
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}
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#endif
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int get_clocks (void)
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{
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_440) || defined(CONFIG_405)
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sys_info_t sys_info;
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get_sys_info (&sys_info);
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@ -796,7 +904,9 @@ ulong get_bus_freq (ulong dummy)
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{
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ulong val;
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_440) || defined(CONFIG_405)
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sys_info_t sys_info;
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get_sys_info (&sys_info);
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@ -699,7 +699,9 @@ _start:
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#endif /* CONFIG_IOP480 */
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/*****************************************************************************/
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_405)
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/*----------------------------------------------------------------------- */
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/* Clear and set up some registers. */
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/*----------------------------------------------------------------------- */
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@ -727,13 +729,13 @@ _start:
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/*----------------------------------------------------------------------- */
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/* Enable two 128MB cachable regions. */
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/*----------------------------------------------------------------------- */
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addis r4,r0,0x8000
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addi r4,r4,0x0001
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lis r4,0x8000
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ori r4,r4,0x0001
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mticcr r4 /* instruction cache */
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isync
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addis r4,r0,0x0000
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addi r4,r4,0x0000
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lis r4,0x0000
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ori r4,r4,0x0000
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mtdccr r4 /* data cache */
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#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
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@ -755,6 +757,70 @@ _start:
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#endif /* CONFIG_405EP */
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#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
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/* test-only... (clean up later when NAND booting is supported) */
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#if defined(CONFIG_405EZ)
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/********************************************************************
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* Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
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*******************************************************************/
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/*
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* We can map the OCM on the PLB3, so map it at
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* CFG_OCM_DATA_ADDR + 0x8000
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*/
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lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
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ori r3,r3,CFG_OCM_DATA_ADDR@l
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ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */
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mtdcr ocmplb3cr1,r3 /* Set PLB Access */
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ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
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mtdcr ocmplb3cr2,r3 /* Set PLB Access */
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isync
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lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
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ori r3,r3,CFG_OCM_DATA_ADDR@l
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ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
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mtdcr ocmdscr1, r3 /* Set Data Side */
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mtdcr ocmiscr1, r3 /* Set Instruction Side */
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ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
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mtdcr ocmdscr2, r3 /* Set Data Side */
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mtdcr ocmiscr2, r3 /* Set Instruction Side */
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addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
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mtdcr ocmdsisdpc,r4
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isync
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#if defined(CONFIG_NAND_SPL)
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/*
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* 405EZ can boot from NAND Flash.
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* If we are booting the SPL (Pre-loader), copy code from
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* the mapped 4K NAND Flash to the OCM
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*/
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||||
li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
|
||||
mtctr r4
|
||||
lis r2,CFG_NAND_BOOT_SPL_SRC@h
|
||||
ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
|
||||
lis r3,CFG_NAND_BOOT_SPL_DST@h
|
||||
ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
|
||||
spl_loop:
|
||||
lwzu r4,4(r2)
|
||||
stwu r4,4(r3)
|
||||
bdnz spl_loop
|
||||
|
||||
/*
|
||||
* Jump to code in OCM Ram
|
||||
*/
|
||||
bl 00f
|
||||
00: mflr r10
|
||||
lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
|
||||
ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
|
||||
sub r10,r10,r3
|
||||
addi r10,r10,28
|
||||
mtlr r10
|
||||
blr
|
||||
start_ram:
|
||||
sync
|
||||
isync
|
||||
#endif
|
||||
#else
|
||||
/* ...test-only */
|
||||
/********************************************************************
|
||||
* Setup OCM - On Chip Memory
|
||||
*******************************************************************/
|
||||
|
|
@ -774,6 +840,7 @@ _start:
|
|||
addis r4, 0, 0xC000 /* OCM data area enabled */
|
||||
mtdcr ocmdscntl, r4
|
||||
isync
|
||||
#endif /* CONFIG_405EZ */
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@
|
|||
#define m16_swap(x) swap_16(x)
|
||||
#define m32_swap(x) swap_32(x)
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
|
||||
#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX)
|
||||
#define ohci_cpu_to_le16(x) (x)
|
||||
#define ohci_cpu_to_le32(x) (x)
|
||||
#else
|
||||
|
|
@ -1601,7 +1601,7 @@ int usb_lowlevel_init(void)
|
|||
gohci.irq = -1;
|
||||
#if defined(CONFIG_440EP)
|
||||
gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
|
||||
#elif defined(CONFIG_440EPX)
|
||||
#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
|
||||
gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
|
||||
#endif
|
||||
|
||||
|
|
@ -1625,8 +1625,10 @@ int usb_lowlevel_init(void)
|
|||
ohci_inited = 1;
|
||||
urb_finished = 1;
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
|
||||
/* init the device driver */
|
||||
usb_dev_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -231,6 +231,47 @@
|
|||
|
||||
#else /* !defined(CONFIG_440) */
|
||||
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define VECNUM_D0 0 /* DMA channel 0 */
|
||||
#define VECNUM_D1 1 /* DMA channel 1 */
|
||||
#define VECNUM_D2 2 /* DMA channel 2 */
|
||||
#define VECNUM_D3 3 /* DMA channel 3 */
|
||||
#define VECNUM_1588 4 /* IEEE 1588 network synchronization */
|
||||
#define VECNUM_U0 5 /* UART0 */
|
||||
#define VECNUM_U1 6 /* UART1 */
|
||||
#define VECNUM_CAN0 7 /* CAN 0 */
|
||||
#define VECNUM_CAN1 8 /* CAN 1 */
|
||||
#define VECNUM_SPI 9 /* SPI */
|
||||
#define VECNUM_IIC0 10 /* I2C */
|
||||
#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
|
||||
#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
|
||||
#define VECNUM_USBH1 13 /* USB Host 1 */
|
||||
#define VECNUM_USBH2 14 /* USB Host 2 */
|
||||
#define VECNUM_USBDEV 15 /* USB Device */
|
||||
#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
|
||||
#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
|
||||
|
||||
#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
|
||||
#define VECNUM_MS 18 /* MAL_SERR_INT */
|
||||
#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
|
||||
#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
|
||||
|
||||
#define VECNUM_MTE 19 /* MAL TXEOB */
|
||||
#define VECNUM_MTE1 20 /* MAL TXEOB1 */
|
||||
#define VECNUM_MRE 21 /* MAL RXEOB */
|
||||
#define VECNUM_NAND 22 /* NAND Flash controller */
|
||||
#define VECNUM_ADC 23 /* ADC */
|
||||
#define VECNUM_DAC 24 /* DAC */
|
||||
#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
|
||||
#define VECNUM_RESERVED0 26 /* Reserved */
|
||||
#define VECNUM_EIR0 27 /* External interrupt 0 */
|
||||
#define VECNUM_EIR1 28 /* External interrupt 1 */
|
||||
#define VECNUM_EIR2 29 /* External interrupt 2 */
|
||||
#define VECNUM_EIR3 30 /* External interrupt 3 */
|
||||
#define VECNUM_EIR4 31 /* External interrupt 4 */
|
||||
|
||||
#else /* !CONFIG_405EZ */
|
||||
|
||||
#define VECNUM_U0 0 /* UART0 */
|
||||
#define VECNUM_U1 1 /* UART1 */
|
||||
#define VECNUM_D0 5 /* DMA channel 0 */
|
||||
|
|
@ -251,6 +292,7 @@
|
|||
#define VECNUM_EIR4 29 /* External interrupt 4 */
|
||||
#define VECNUM_EIR5 30 /* External interrupt 5 */
|
||||
#define VECNUM_EIR6 31 /* External interrupt 6 */
|
||||
#endif /* defined(CONFIG_405EZ) */
|
||||
|
||||
#endif /* defined(CONFIG_440) */
|
||||
|
||||
|
|
|
|||
|
|
@ -298,6 +298,10 @@
|
|||
#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
|
||||
#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
|
||||
#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
|
||||
#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
|
||||
#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
|
||||
#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
|
||||
#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
|
||||
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
|
||||
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
|
||||
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
|
||||
|
|
@ -529,6 +533,10 @@
|
|||
#define SPRG1 SPRN_SPRG1
|
||||
#define SPRG2 SPRN_SPRG2
|
||||
#define SPRG3 SPRN_SPRG3
|
||||
#define SPRG4 SPRN_SPRG4
|
||||
#define SPRG5 SPRN_SPRG5
|
||||
#define SPRG6 SPRN_SPRG6
|
||||
#define SPRG7 SPRN_SPRG7
|
||||
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
|
||||
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
|
||||
#define SVR SPRN_SVR /* System Version Register */
|
||||
|
|
@ -731,6 +739,7 @@
|
|||
#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
|
||||
#define PVR_405EP_RA 0x51210950
|
||||
#define PVR_405GPR_RB 0x50910951
|
||||
#define PVR_405EZ_RA 0x41511460
|
||||
#define PVR_440GP_RB 0x40120440
|
||||
#define PVR_440GP_RC 0x40120481
|
||||
#define PVR_440EP_RA 0x42221850
|
||||
|
|
|
|||
|
|
@ -83,6 +83,7 @@ typedef struct bd_info {
|
|||
defined(CONFIG_405GP) || \
|
||||
defined(CONFIG_405CR) || \
|
||||
defined(CONFIG_405EP) || \
|
||||
defined(CONFIG_405EZ) || \
|
||||
defined(CONFIG_440)
|
||||
unsigned char bi_s_version[4]; /* Version of this structure */
|
||||
unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
|
||||
|
|
@ -107,7 +108,8 @@ typedef struct bd_info {
|
|||
unsigned char bi_enet3addr[6];
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
|
||||
defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
|
||||
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
unsigned int bi_opbfreq; /* OPB clock in Hz */
|
||||
|
|
|
|||
540
include/ppc405.h
540
include/ppc405.h
|
|
@ -117,6 +117,48 @@
|
|||
/*-----------------------------------------------------------------------------+
|
||||
| Universal interrupt controller interrupts
|
||||
+-----------------------------------------------------------------------------*/
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define UIC_DMA0 0x80000000 /* DMA chan. 0 */
|
||||
#define UIC_DMA1 0x40000000 /* DMA chan. 1 */
|
||||
#define UIC_DMA2 0x20000000 /* DMA chan. 2 */
|
||||
#define UIC_DMA3 0x10000000 /* DMA chan. 3 */
|
||||
#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
|
||||
#define UIC_UART0 0x04000000 /* UART 0 */
|
||||
#define UIC_UART1 0x02000000 /* UART 1 */
|
||||
#define UIC_CAN0 0x01000000 /* CAN 0 */
|
||||
#define UIC_CAN1 0x00800000 /* CAN 1 */
|
||||
#define UIC_SPI 0x00400000 /* SPI */
|
||||
#define UIC_IIC 0x00200000 /* IIC */
|
||||
#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
|
||||
#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
|
||||
#define UIC_USBH1 0x00040000 /* USB Host 1 */
|
||||
#define UIC_USBH2 0x00020000 /* USB Host 2 */
|
||||
#define UIC_USBDEV 0x00010000 /* USB Device */
|
||||
#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
|
||||
#define UIC_ENET1 0x00008000 /* dummy define */
|
||||
#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
|
||||
|
||||
#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
|
||||
#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
|
||||
#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
|
||||
#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
|
||||
|
||||
#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
|
||||
#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
|
||||
#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
|
||||
#define UIC_NAND 0x00000200 /* NAND Flash controller */
|
||||
#define UIC_ADC 0x00000100 /* ADC */
|
||||
#define UIC_DAC 0x00000080 /* DAC */
|
||||
#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
|
||||
#define UIC_RESERVED0 0x00000020 /* Reserved */
|
||||
#define UIC_EXT0 0x00000010 /* External interrupt 0 */
|
||||
#define UIC_EXT1 0x00000008 /* External interrupt 1 */
|
||||
#define UIC_EXT2 0x00000004 /* External interrupt 2 */
|
||||
#define UIC_EXT3 0x00000002 /* External interrupt 3 */
|
||||
#define UIC_EXT4 0x00000001 /* External interrupt 4 */
|
||||
|
||||
#else /* !defined(CONFIG_405EZ) */
|
||||
|
||||
#define UIC_UART0 0x80000000 /* UART 0 */
|
||||
#define UIC_UART1 0x40000000 /* UART 1 */
|
||||
#define UIC_IIC 0x20000000 /* IIC */
|
||||
|
|
@ -144,6 +186,7 @@
|
|||
#define UIC_EXT4 0x00000004 /* External interrupt 4 */
|
||||
#define UIC_EXT5 0x00000002 /* External interrupt 5 */
|
||||
#define UIC_EXT6 0x00000001 /* External interrupt 6 */
|
||||
#endif /* defined(CONFIG_405EZ) */
|
||||
|
||||
/******************************************************************************
|
||||
* SDRAM Controller
|
||||
|
|
@ -496,6 +539,325 @@
|
|||
*/
|
||||
#define VCO_MIN 500
|
||||
#define VCO_MAX 1000
|
||||
#elif defined(CONFIG_405EZ)
|
||||
/******************************************************************************
|
||||
* SDR Registers
|
||||
******************************************************************************/
|
||||
#define SDR_DCR_BASE 0x0E
|
||||
#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
|
||||
#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
|
||||
|
||||
#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
|
||||
#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
|
||||
|
||||
#define sdrnand0 0x4000
|
||||
#define sdrultra0 0x4040
|
||||
#define sdrultra1 0x4050
|
||||
#define sdricintstat 0x4510
|
||||
|
||||
#define SDR_NAND0_NDEN 0x80000000
|
||||
|
||||
#define SDR_ULTRA0_NDGPIOBP 0x80000000
|
||||
#define SDR_ULTRA0_CSN_MASK 0x78000000
|
||||
#define SDR_ULTRA0_CSNSEL0 0x40000000
|
||||
#define SDR_ULTRA0_CSNSEL1 0x20000000
|
||||
#define SDR_ULTRA0_CSNSEL2 0x10000000
|
||||
#define SDR_ULTRA0_CSNSEL3 0x08000000
|
||||
|
||||
#define SDR_ULTRA1_LEDNENABLE 0x40000000
|
||||
|
||||
#define SDR_ICRX_STAT 0x80000000
|
||||
#define SDR_ICTX0_STAT 0x40000000
|
||||
#define SDR_ICTX1_STAT 0x20000000
|
||||
|
||||
/******************************************************************************
|
||||
* Control
|
||||
******************************************************************************/
|
||||
#define CNTRL_DCR_BASE 0x0C
|
||||
#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */
|
||||
#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */
|
||||
|
||||
/* CPR Registers */
|
||||
#define cprclkupd 0x020 /* CPR_CLKUPD */
|
||||
#define cprpllc 0x040 /* CPR_PLLC */
|
||||
#define cprplld 0x060 /* CPR_PLLD */
|
||||
#define cprprimad 0x080 /* CPR_PRIMAD */
|
||||
#define cprperd0 0x0e0 /* CPR_PERD0 */
|
||||
#define cprperd1 0x0e1 /* CPR_PERD1 */
|
||||
#define cprperc0 0x180 /* CPR_PERC0 */
|
||||
#define cprmisc0 0x181 /* CPR_MISC0 */
|
||||
#define cprmisc1 0x182 /* CPR_MISC1 */
|
||||
|
||||
/*
|
||||
* Macro for accessing the indirect CPR register
|
||||
*/
|
||||
#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data)
|
||||
#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd)
|
||||
|
||||
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
|
||||
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
|
||||
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
|
||||
|
||||
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
|
||||
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
|
||||
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
|
||||
|
||||
#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
|
||||
#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
|
||||
#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
|
||||
#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
|
||||
|
||||
#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
|
||||
#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
|
||||
#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
|
||||
#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
|
||||
|
||||
#if 0 /* Deprecated */
|
||||
#define CNTRL_DCR_BASE 0x0f0
|
||||
#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
|
||||
#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
|
||||
#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
|
||||
#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
|
||||
#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
|
||||
#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
|
||||
|
||||
#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
|
||||
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
|
||||
#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
|
||||
#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
|
||||
#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
|
||||
#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
|
||||
#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
|
||||
#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
|
||||
#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
|
||||
#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
|
||||
|
||||
/* Bit definitions */
|
||||
#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
|
||||
#define PLLMR0_CPU_DIV_BYPASS 0x00000000
|
||||
#define PLLMR0_CPU_DIV_2 0x00100000
|
||||
#define PLLMR0_CPU_DIV_3 0x00200000
|
||||
#define PLLMR0_CPU_DIV_4 0x00300000
|
||||
|
||||
#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
|
||||
#define PLLMR0_CPU_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_CPU_PLB_DIV_2 0x00010000
|
||||
#define PLLMR0_CPU_PLB_DIV_3 0x00020000
|
||||
#define PLLMR0_CPU_PLB_DIV_4 0x00030000
|
||||
|
||||
#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
|
||||
#define PLLMR0_OPB_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_OPB_PLB_DIV_2 0x00001000
|
||||
#define PLLMR0_OPB_PLB_DIV_3 0x00002000
|
||||
#define PLLMR0_OPB_PLB_DIV_4 0x00003000
|
||||
|
||||
#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
|
||||
#define PLLMR0_EXB_PLB_DIV_2 0x00000000
|
||||
#define PLLMR0_EXB_PLB_DIV_3 0x00000100
|
||||
#define PLLMR0_EXB_PLB_DIV_4 0x00000200
|
||||
#define PLLMR0_EXB_PLB_DIV_5 0x00000300
|
||||
|
||||
#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
|
||||
#define PLLMR0_MAL_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_MAL_PLB_DIV_2 0x00000010
|
||||
#define PLLMR0_MAL_PLB_DIV_3 0x00000020
|
||||
#define PLLMR0_MAL_PLB_DIV_4 0x00000030
|
||||
|
||||
#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
|
||||
#define PLLMR0_PCI_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_PCI_PLB_DIV_2 0x00000001
|
||||
#define PLLMR0_PCI_PLB_DIV_3 0x00000002
|
||||
#define PLLMR0_PCI_PLB_DIV_4 0x00000003
|
||||
|
||||
#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
|
||||
#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
|
||||
#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
|
||||
#define PLLMR1_FBMUL_DIV_16 0x00000000
|
||||
#define PLLMR1_FBMUL_DIV_1 0x00100000
|
||||
#define PLLMR1_FBMUL_DIV_2 0x00200000
|
||||
#define PLLMR1_FBMUL_DIV_3 0x00300000
|
||||
#define PLLMR1_FBMUL_DIV_4 0x00400000
|
||||
#define PLLMR1_FBMUL_DIV_5 0x00500000
|
||||
#define PLLMR1_FBMUL_DIV_6 0x00600000
|
||||
#define PLLMR1_FBMUL_DIV_7 0x00700000
|
||||
#define PLLMR1_FBMUL_DIV_8 0x00800000
|
||||
#define PLLMR1_FBMUL_DIV_9 0x00900000
|
||||
#define PLLMR1_FBMUL_DIV_10 0x00A00000
|
||||
#define PLLMR1_FBMUL_DIV_11 0x00B00000
|
||||
#define PLLMR1_FBMUL_DIV_12 0x00C00000
|
||||
#define PLLMR1_FBMUL_DIV_13 0x00D00000
|
||||
#define PLLMR1_FBMUL_DIV_14 0x00E00000
|
||||
#define PLLMR1_FBMUL_DIV_15 0x00F00000
|
||||
|
||||
#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
|
||||
#define PLLMR1_FWDVA_DIV_8 0x00000000
|
||||
#define PLLMR1_FWDVA_DIV_7 0x00010000
|
||||
#define PLLMR1_FWDVA_DIV_6 0x00020000
|
||||
#define PLLMR1_FWDVA_DIV_5 0x00030000
|
||||
#define PLLMR1_FWDVA_DIV_4 0x00040000
|
||||
#define PLLMR1_FWDVA_DIV_3 0x00050000
|
||||
#define PLLMR1_FWDVA_DIV_2 0x00060000
|
||||
#define PLLMR1_FWDVA_DIV_1 0x00070000
|
||||
#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
|
||||
#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
|
||||
|
||||
/* Defines for CPC0_EPRCSR register */
|
||||
#define CPC0_EPRCSR_E0NFE 0x80000000
|
||||
#define CPC0_EPRCSR_E1NFE 0x40000000
|
||||
#define CPC0_EPRCSR_E1RPP 0x00000080
|
||||
#define CPC0_EPRCSR_E0RPP 0x00000040
|
||||
#define CPC0_EPRCSR_E1ERP 0x00000020
|
||||
#define CPC0_EPRCSR_E0ERP 0x00000010
|
||||
#define CPC0_EPRCSR_E1PCI 0x00000002
|
||||
#define CPC0_EPRCSR_E0PCI 0x00000001
|
||||
|
||||
/* Defines for CPC0_BOOR Register */
|
||||
#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
|
||||
|
||||
/* Defines for CPC0_PLLMR1 Register fields */
|
||||
#define PLL_ACTIVE 0x80000000
|
||||
#define CPC0_PLLMR1_SSCS 0x80000000
|
||||
#define PLL_RESET 0x40000000
|
||||
#define CPC0_PLLMR1_PLLR 0x40000000
|
||||
/* Feedback multiplier */
|
||||
#define PLL_FBKDIV 0x00F00000
|
||||
#define CPC0_PLLMR1_FBDV 0x00F00000
|
||||
#define PLL_FBKDIV_16 0x00000000
|
||||
#define PLL_FBKDIV_1 0x00100000
|
||||
#define PLL_FBKDIV_2 0x00200000
|
||||
#define PLL_FBKDIV_3 0x00300000
|
||||
#define PLL_FBKDIV_4 0x00400000
|
||||
#define PLL_FBKDIV_5 0x00500000
|
||||
#define PLL_FBKDIV_6 0x00600000
|
||||
#define PLL_FBKDIV_7 0x00700000
|
||||
#define PLL_FBKDIV_8 0x00800000
|
||||
#define PLL_FBKDIV_9 0x00900000
|
||||
#define PLL_FBKDIV_10 0x00A00000
|
||||
#define PLL_FBKDIV_11 0x00B00000
|
||||
#define PLL_FBKDIV_12 0x00C00000
|
||||
#define PLL_FBKDIV_13 0x00D00000
|
||||
#define PLL_FBKDIV_14 0x00E00000
|
||||
#define PLL_FBKDIV_15 0x00F00000
|
||||
/* Forward A divisor */
|
||||
#define PLL_FWDDIVA 0x00070000
|
||||
#define CPC0_PLLMR1_FWDVA 0x00070000
|
||||
#define PLL_FWDDIVA_8 0x00000000
|
||||
#define PLL_FWDDIVA_7 0x00010000
|
||||
#define PLL_FWDDIVA_6 0x00020000
|
||||
#define PLL_FWDDIVA_5 0x00030000
|
||||
#define PLL_FWDDIVA_4 0x00040000
|
||||
#define PLL_FWDDIVA_3 0x00050000
|
||||
#define PLL_FWDDIVA_2 0x00060000
|
||||
#define PLL_FWDDIVA_1 0x00070000
|
||||
/* Forward B divisor */
|
||||
#define PLL_FWDDIVB 0x00007000
|
||||
#define CPC0_PLLMR1_FWDVB 0x00007000
|
||||
#define PLL_FWDDIVB_8 0x00000000
|
||||
#define PLL_FWDDIVB_7 0x00001000
|
||||
#define PLL_FWDDIVB_6 0x00002000
|
||||
#define PLL_FWDDIVB_5 0x00003000
|
||||
#define PLL_FWDDIVB_4 0x00004000
|
||||
#define PLL_FWDDIVB_3 0x00005000
|
||||
#define PLL_FWDDIVB_2 0x00006000
|
||||
#define PLL_FWDDIVB_1 0x00007000
|
||||
/* PLL tune bits */
|
||||
#define PLL_TUNE_MASK 0x000003FF
|
||||
#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
|
||||
#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
|
||||
#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
|
||||
#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
|
||||
#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
|
||||
#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
|
||||
#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
|
||||
|
||||
/* Defines for CPC0_PLLMR0 Register fields */
|
||||
/* CPU divisor */
|
||||
#define PLL_CPUDIV 0x00300000
|
||||
#define CPC0_PLLMR0_CCDV 0x00300000
|
||||
#define PLL_CPUDIV_1 0x00000000
|
||||
#define PLL_CPUDIV_2 0x00100000
|
||||
#define PLL_CPUDIV_3 0x00200000
|
||||
#define PLL_CPUDIV_4 0x00300000
|
||||
/* PLB divisor */
|
||||
#define PLL_PLBDIV 0x00030000
|
||||
#define CPC0_PLLMR0_CBDV 0x00030000
|
||||
#define PLL_PLBDIV_1 0x00000000
|
||||
#define PLL_PLBDIV_2 0x00010000
|
||||
#define PLL_PLBDIV_3 0x00020000
|
||||
#define PLL_PLBDIV_4 0x00030000
|
||||
/* OPB divisor */
|
||||
#define PLL_OPBDIV 0x00003000
|
||||
#define CPC0_PLLMR0_OPDV 0x00003000
|
||||
#define PLL_OPBDIV_1 0x00000000
|
||||
#define PLL_OPBDIV_2 0x00001000
|
||||
#define PLL_OPBDIV_3 0x00002000
|
||||
#define PLL_OPBDIV_4 0x00003000
|
||||
/* EBC divisor */
|
||||
#define PLL_EXTBUSDIV 0x00000300
|
||||
#define CPC0_PLLMR0_EPDV 0x00000300
|
||||
#define PLL_EXTBUSDIV_2 0x00000000
|
||||
#define PLL_EXTBUSDIV_3 0x00000100
|
||||
#define PLL_EXTBUSDIV_4 0x00000200
|
||||
#define PLL_EXTBUSDIV_5 0x00000300
|
||||
/* MAL divisor */
|
||||
#define PLL_MALDIV 0x00000030
|
||||
#define CPC0_PLLMR0_MPDV 0x00000030
|
||||
#define PLL_MALDIV_1 0x00000000
|
||||
#define PLL_MALDIV_2 0x00000010
|
||||
#define PLL_MALDIV_3 0x00000020
|
||||
#define PLL_MALDIV_4 0x00000030
|
||||
/* PCI divisor */
|
||||
#define PLL_PCIDIV 0x00000003
|
||||
#define CPC0_PLLMR0_PPFD 0x00000003
|
||||
#define PLL_PCIDIV_1 0x00000000
|
||||
#define PLL_PCIDIV_2 0x00000001
|
||||
#define PLL_PCIDIV_3 0x00000002
|
||||
#define PLL_PCIDIV_4 0x00000003
|
||||
|
||||
/*
|
||||
*-------------------------------------------------------------------------------
|
||||
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
|
||||
* assuming a 33.3MHz input clock to the 405EP.
|
||||
*-------------------------------------------------------------------------------
|
||||
*/
|
||||
#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
|
||||
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
|
||||
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
||||
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
|
||||
/*
|
||||
* PLL Voltage Controlled Oscillator (VCO) definitions
|
||||
* Maximum and minimum values (in MHz) for correct PLL operation.
|
||||
*/
|
||||
#define VCO_MIN 500
|
||||
#define VCO_MAX 1000
|
||||
#endif /* #if 0 */
|
||||
#else /* #ifdef CONFIG_405EP */
|
||||
/******************************************************************************
|
||||
* Control
|
||||
|
|
@ -578,6 +940,121 @@
|
|||
/******************************************************************************
|
||||
* Memory Access Layer
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define MAL_DCR_BASE 0x380
|
||||
#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
|
||||
#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
|
||||
#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
|
||||
#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
|
||||
#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
|
||||
#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
|
||||
#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
|
||||
#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
|
||||
/* 0x08-0x0F Reserved */
|
||||
#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
|
||||
#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
|
||||
#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
|
||||
#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
|
||||
/* 0x14-0x1F Reserved */
|
||||
#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
|
||||
#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
|
||||
#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
|
||||
#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
|
||||
#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
|
||||
#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
|
||||
#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
|
||||
#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
|
||||
#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
|
||||
#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
|
||||
#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
|
||||
#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
|
||||
#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
|
||||
#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
|
||||
#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
|
||||
#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
|
||||
#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
|
||||
#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
|
||||
#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
|
||||
#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
|
||||
#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
|
||||
#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
|
||||
#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
|
||||
#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
|
||||
#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
|
||||
#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
|
||||
#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
|
||||
#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
|
||||
#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
|
||||
#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
|
||||
#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
|
||||
#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
|
||||
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
|
||||
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
|
||||
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
|
||||
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
|
||||
#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
|
||||
#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
|
||||
#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
|
||||
#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
|
||||
#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
|
||||
#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
|
||||
#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
|
||||
#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
|
||||
#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
|
||||
#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
|
||||
#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
|
||||
#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
|
||||
#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
|
||||
#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
|
||||
#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
|
||||
#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
|
||||
#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
|
||||
#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
|
||||
#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
|
||||
#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
|
||||
#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
|
||||
#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
|
||||
#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
|
||||
#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
|
||||
#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
|
||||
#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
|
||||
#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
|
||||
#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
|
||||
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
|
||||
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
|
||||
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
|
||||
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
|
||||
#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
|
||||
#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
|
||||
#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
|
||||
#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
|
||||
#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
|
||||
#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
|
||||
#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
|
||||
#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
|
||||
#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
|
||||
#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
|
||||
#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
|
||||
#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
|
||||
#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
|
||||
#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
|
||||
#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
|
||||
#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
|
||||
#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
|
||||
#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
|
||||
#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
|
||||
#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
|
||||
#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
|
||||
#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
|
||||
#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
|
||||
#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
|
||||
#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
|
||||
#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
|
||||
#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
|
||||
#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
|
||||
|
||||
#else /* !defined(CONFIG_405EZ) */
|
||||
|
||||
#define MAL_DCR_BASE 0x180
|
||||
#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
|
||||
#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
|
||||
|
|
@ -598,6 +1075,7 @@
|
|||
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
|
||||
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
|
||||
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
|
||||
#endif /* defined(CONFIG_405EZ) */
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| IIC Register Offsets
|
||||
|
|
@ -635,15 +1113,76 @@
|
|||
/******************************************************************************
|
||||
* On Chip Memory
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define OCM_DCR_BASE 0x020
|
||||
#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
|
||||
#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
|
||||
#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
|
||||
#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
|
||||
#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
|
||||
#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
|
||||
#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
|
||||
#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
|
||||
#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
|
||||
#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
|
||||
#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
|
||||
#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
|
||||
#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
|
||||
#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
|
||||
#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
|
||||
#else
|
||||
#define OCM_DCR_BASE 0x018
|
||||
#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
|
||||
#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
|
||||
#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
|
||||
#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
|
||||
#endif /* CONFIG_405EZ */
|
||||
|
||||
/******************************************************************************
|
||||
* GPIO macro register defines
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
/* Only the 405EZ has 2 GPIOs */
|
||||
#define GPIO_BASE 0xEF600700
|
||||
#define GPIO0_OR (GPIO_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||||
#define GPIO0_OSRL (GPIO_BASE+0x8)
|
||||
#define GPIO0_OSRH (GPIO_BASE+0xC)
|
||||
#define GPIO0_TSRL (GPIO_BASE+0x10)
|
||||
#define GPIO0_TSRH (GPIO_BASE+0x14)
|
||||
#define GPIO0_ODR (GPIO_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE+0x1C)
|
||||
#define GPIO0_RR1 (GPIO_BASE+0x20)
|
||||
#define GPIO0_RR2 (GPIO_BASE+0x24)
|
||||
#define GPIO0_RR3 (GPIO_BASE+0x28)
|
||||
#define GPIO0_ISR1L (GPIO_BASE+0x30)
|
||||
#define GPIO0_ISR1H (GPIO_BASE+0x34)
|
||||
#define GPIO0_ISR2L (GPIO_BASE+0x38)
|
||||
#define GPIO0_ISR2H (GPIO_BASE+0x3C)
|
||||
#define GPIO0_ISR3L (GPIO_BASE+0x40)
|
||||
#define GPIO0_ISR3H (GPIO_BASE+0x44)
|
||||
|
||||
#define GPIO1_BASE 0xEF600800
|
||||
#define GPIO1_OR (GPIO1_BASE+0x0)
|
||||
#define GPIO1_TCR (GPIO1_BASE+0x4)
|
||||
#define GPIO1_OSRL (GPIO1_BASE+0x8)
|
||||
#define GPIO1_OSRH (GPIO1_BASE+0xC)
|
||||
#define GPIO1_TSRL (GPIO1_BASE+0x10)
|
||||
#define GPIO1_TSRH (GPIO1_BASE+0x14)
|
||||
#define GPIO1_ODR (GPIO1_BASE+0x18)
|
||||
#define GPIO1_IR (GPIO1_BASE+0x1C)
|
||||
#define GPIO1_RR1 (GPIO1_BASE+0x20)
|
||||
#define GPIO1_RR2 (GPIO1_BASE+0x24)
|
||||
#define GPIO1_RR3 (GPIO1_BASE+0x28)
|
||||
#define GPIO1_ISR1L (GPIO1_BASE+0x30)
|
||||
#define GPIO1_ISR1H (GPIO1_BASE+0x34)
|
||||
#define GPIO1_ISR2L (GPIO1_BASE+0x38)
|
||||
#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
|
||||
#define GPIO1_ISR3L (GPIO1_BASE+0x40)
|
||||
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
|
||||
|
||||
#else /* !405EZ */
|
||||
|
||||
#define GPIO_BASE 0xEF600700
|
||||
#define GPIO0_OR (GPIO_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||||
|
|
@ -660,6 +1199,7 @@
|
|||
#define GPIO0_ISR2H (GPIO_BASE+0x38)
|
||||
#define GPIO0_ISR2L (GPIO_BASE+0x3C)
|
||||
|
||||
#endif /* CONFIG_405EZ */
|
||||
|
||||
/*
|
||||
* Macro for accessing the indirect EBC register
|
||||
|
|
|
|||
|
|
@ -130,13 +130,13 @@ typedef struct emac_4xx_hw_st {
|
|||
|
||||
|
||||
#if defined(CONFIG_440GX)
|
||||
#define EMAC_NUM_DEV 4
|
||||
#define EMAC_NUM_DEV 4
|
||||
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
|
||||
defined(CONFIG_NET_MULTI) && \
|
||||
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
|
||||
#define EMAC_NUM_DEV 2
|
||||
#define EMAC_NUM_DEV 2
|
||||
#else
|
||||
#define EMAC_NUM_DEV 1
|
||||
#define EMAC_NUM_DEV 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
|
||||
|
|
@ -153,16 +153,16 @@ typedef struct emac_4xx_hw_st {
|
|||
/*ZMII Bridge Register addresses */
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
|
||||
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
|
||||
#else
|
||||
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
|
||||
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
|
||||
#endif
|
||||
#define ZMII_FER (ZMII_BASE)
|
||||
#define ZMII_SSR (ZMII_BASE + 4)
|
||||
#define ZMII_SMIISR (ZMII_BASE + 8)
|
||||
#define ZMII_FER (ZMII_BASE)
|
||||
#define ZMII_SSR (ZMII_BASE + 4)
|
||||
#define ZMII_SMIISR (ZMII_BASE + 8)
|
||||
|
||||
#define ZMII_RMII 0x22000000
|
||||
#define ZMII_MDI0 0x80000000
|
||||
#define ZMII_RMII 0x22000000
|
||||
#define ZMII_MDI0 0x80000000
|
||||
|
||||
/* ZMII FER Register Bit Definitions */
|
||||
#define ZMII_FER_DIS (0x0)
|
||||
|
|
@ -299,49 +299,41 @@ typedef struct emac_4xx_hw_st {
|
|||
#if defined(CONFIG_440)
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
|
||||
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
|
||||
#else
|
||||
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
|
||||
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
|
||||
#endif
|
||||
#else
|
||||
#define EMAC_BASE 0xEF600800
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define EMAC_BASE 0xEF600900
|
||||
#else
|
||||
#define EMAC_BASE 0xEF600800
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define EMAC_M0 (EMAC_BASE)
|
||||
#define EMAC_M1 (EMAC_BASE + 4)
|
||||
#define EMAC_TXM0 (EMAC_BASE + 8)
|
||||
#define EMAC_TXM1 (EMAC_BASE + 12)
|
||||
#define EMAC_RXM (EMAC_BASE + 16)
|
||||
#define EMAC_ISR (EMAC_BASE + 20)
|
||||
#define EMAC_IER (EMAC_BASE + 24)
|
||||
#define EMAC_IAH (EMAC_BASE + 28)
|
||||
#define EMAC_IAL (EMAC_BASE + 32)
|
||||
#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36)
|
||||
#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40)
|
||||
#define EMAC_M0 (EMAC_BASE)
|
||||
#define EMAC_M1 (EMAC_BASE + 4)
|
||||
#define EMAC_TXM0 (EMAC_BASE + 8)
|
||||
#define EMAC_TXM1 (EMAC_BASE + 12)
|
||||
#define EMAC_RXM (EMAC_BASE + 16)
|
||||
#define EMAC_ISR (EMAC_BASE + 20)
|
||||
#define EMAC_IER (EMAC_BASE + 24)
|
||||
#define EMAC_IAH (EMAC_BASE + 28)
|
||||
#define EMAC_IAL (EMAC_BASE + 32)
|
||||
#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
|
||||
#define EMAC_IND_HASH_1 (EMAC_BASE + 48)
|
||||
#define EMAC_IND_HASH_2 (EMAC_BASE + 52)
|
||||
#define EMAC_IND_HASH_3 (EMAC_BASE + 56)
|
||||
#define EMAC_IND_HASH_4 (EMAC_BASE + 60)
|
||||
#define EMAC_GRP_HASH_1 (EMAC_BASE + 64)
|
||||
#define EMAC_GRP_HASH_2 (EMAC_BASE + 68)
|
||||
#define EMAC_GRP_HASH_3 (EMAC_BASE + 72)
|
||||
#define EMAC_GRP_HASH_4 (EMAC_BASE + 76)
|
||||
#define EMAC_LST_SRC_LOW (EMAC_BASE + 80)
|
||||
#define EMAC_LST_SRC_HI (EMAC_BASE + 84)
|
||||
#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
|
||||
#define EMAC_STACR (EMAC_BASE + 92)
|
||||
#define EMAC_TRTR (EMAC_BASE + 96)
|
||||
#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
|
||||
#define EMAC_STACR (EMAC_BASE + 92)
|
||||
#define EMAC_TRTR (EMAC_BASE + 96)
|
||||
#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
|
||||
|
||||
/* bit definitions */
|
||||
/* MODE REG 0 */
|
||||
#define EMAC_M0_RXI (0x80000000)
|
||||
#define EMAC_M0_TXI (0x40000000)
|
||||
#define EMAC_M0_SRST (0x20000000)
|
||||
#define EMAC_M0_TXE (0x10000000)
|
||||
#define EMAC_M0_RXE (0x08000000)
|
||||
#define EMAC_M0_WKE (0x04000000)
|
||||
#define EMAC_M0_RXI (0x80000000)
|
||||
#define EMAC_M0_TXI (0x40000000)
|
||||
#define EMAC_M0_SRST (0x20000000)
|
||||
#define EMAC_M0_TXE (0x10000000)
|
||||
#define EMAC_M0_RXE (0x08000000)
|
||||
#define EMAC_M0_WKE (0x04000000)
|
||||
|
||||
/* on 440GX EMAC_MR1 has a different layout! */
|
||||
#if defined(CONFIG_440GX) || \
|
||||
|
|
@ -351,23 +343,23 @@ typedef struct emac_4xx_hw_st {
|
|||
#define EMAC_M1_FDE (0x80000000)
|
||||
#define EMAC_M1_ILE (0x40000000)
|
||||
#define EMAC_M1_VLE (0x20000000)
|
||||
#define EMAC_M1_EIFC (0x10000000)
|
||||
#define EMAC_M1_APP (0x08000000)
|
||||
#define EMAC_M1_RSVD (0x06000000)
|
||||
#define EMAC_M1_IST (0x01000000)
|
||||
#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
|
||||
#define EMAC_M1_MF_100MBPS (0x00400000)
|
||||
#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
|
||||
#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
|
||||
#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
|
||||
#define EMAC_M1_RFS_2K (0x00100000)
|
||||
#define EMAC_M1_RFS_1K (0x00080000)
|
||||
#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
|
||||
#define EMAC_M1_TX_FIFO_8K (0x00040000)
|
||||
#define EMAC_M1_TX_FIFO_4K (0x00030000)
|
||||
#define EMAC_M1_EIFC (0x10000000)
|
||||
#define EMAC_M1_APP (0x08000000)
|
||||
#define EMAC_M1_RSVD (0x06000000)
|
||||
#define EMAC_M1_IST (0x01000000)
|
||||
#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
|
||||
#define EMAC_M1_MF_100MBPS (0x00400000)
|
||||
#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
|
||||
#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
|
||||
#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
|
||||
#define EMAC_M1_RFS_2K (0x00100000)
|
||||
#define EMAC_M1_RFS_1K (0x00080000)
|
||||
#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
|
||||
#define EMAC_M1_TX_FIFO_8K (0x00040000)
|
||||
#define EMAC_M1_TX_FIFO_4K (0x00030000)
|
||||
#define EMAC_M1_TX_FIFO_2K (0x00020000)
|
||||
#define EMAC_M1_TX_FIFO_1K (0x00010000)
|
||||
#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
|
||||
#define EMAC_M1_TX_FIFO_1K (0x00010000)
|
||||
#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
|
||||
#define EMAC_M1_MWSW (0x00007000)
|
||||
#define EMAC_M1_JUMBO_ENABLE (0x00000800)
|
||||
#define EMAC_M1_IPPA (0x000007c0)
|
||||
|
|
@ -378,34 +370,34 @@ typedef struct emac_4xx_hw_st {
|
|||
#define EMAC_M1_RSVD1 (0x00000007)
|
||||
#else /* defined(CONFIG_440GX) */
|
||||
/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
|
||||
#define EMAC_M1_FDE 0x80000000
|
||||
#define EMAC_M1_ILE 0x40000000
|
||||
#define EMAC_M1_VLE 0x20000000
|
||||
#define EMAC_M1_EIFC 0x10000000
|
||||
#define EMAC_M1_APP 0x08000000
|
||||
#define EMAC_M1_AEMI 0x02000000
|
||||
#define EMAC_M1_IST 0x01000000
|
||||
#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
|
||||
#define EMAC_M1_MF_100MBPS 0x00400000
|
||||
#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
|
||||
#define EMAC_M1_RFS_2K 0x00200000
|
||||
#define EMAC_M1_RFS_1K 0x00100000
|
||||
#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
|
||||
#define EMAC_M1_TX_FIFO_1K 0x00040000
|
||||
#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
|
||||
#define EMAC_M1_TR0_MULTI 0x00008000
|
||||
#define EMAC_M1_TR1_DEPEND 0x00004000
|
||||
#define EMAC_M1_TR1_MULTI 0x00002000
|
||||
#define EMAC_M1_FDE 0x80000000
|
||||
#define EMAC_M1_ILE 0x40000000
|
||||
#define EMAC_M1_VLE 0x20000000
|
||||
#define EMAC_M1_EIFC 0x10000000
|
||||
#define EMAC_M1_APP 0x08000000
|
||||
#define EMAC_M1_AEMI 0x02000000
|
||||
#define EMAC_M1_IST 0x01000000
|
||||
#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
|
||||
#define EMAC_M1_MF_100MBPS 0x00400000
|
||||
#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
|
||||
#define EMAC_M1_RFS_2K 0x00200000
|
||||
#define EMAC_M1_RFS_1K 0x00100000
|
||||
#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
|
||||
#define EMAC_M1_TX_FIFO_1K 0x00040000
|
||||
#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
|
||||
#define EMAC_M1_TR0_MULTI 0x00008000
|
||||
#define EMAC_M1_TR1_DEPEND 0x00004000
|
||||
#define EMAC_M1_TR1_MULTI 0x00002000
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#define EMAC_M1_JUMBO_ENABLE 0x00001000
|
||||
#define EMAC_M1_JUMBO_ENABLE 0x00001000
|
||||
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
|
||||
#endif /* defined(CONFIG_440GX) */
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/* Transmit Mode Register 0 */
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#define EMAC_TXM0_GNP0 (0x80000000)
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#define EMAC_TXM0_GNP1 (0x40000000)
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#define EMAC_TXM0_GNPD (0x20000000)
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#define EMAC_TXM0_FC (0x10000000)
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#define EMAC_TXM0_GNP0 (0x80000000)
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#define EMAC_TXM0_GNP1 (0x40000000)
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#define EMAC_TXM0_GNPD (0x20000000)
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#define EMAC_TXM0_FC (0x10000000)
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/* Receive Mode Register */
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#define EMAC_RMR_SP (0x80000000)
|
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|
|
@ -427,39 +419,38 @@ typedef struct emac_4xx_hw_st {
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#define EMAC_ISR_PP (0x01000000)
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#define EMAC_ISR_BP (0x00800000)
|
||||
#define EMAC_ISR_RP (0x00400000)
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#define EMAC_ISR_SE (0x00200000)
|
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#define EMAC_ISR_SYE (0x00100000)
|
||||
#define EMAC_ISR_BFCS (0x00080000)
|
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#define EMAC_ISR_PTLE (0x00040000)
|
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#define EMAC_ISR_ORE (0x00020000)
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#define EMAC_ISR_IRE (0x00010000)
|
||||
#define EMAC_ISR_DBDM (0x00000200)
|
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#define EMAC_ISR_DB0 (0x00000100)
|
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#define EMAC_ISR_SE0 (0x00000080)
|
||||
#define EMAC_ISR_TE0 (0x00000040)
|
||||
#define EMAC_ISR_DB1 (0x00000020)
|
||||
#define EMAC_ISR_SE1 (0x00000010)
|
||||
#define EMAC_ISR_TE1 (0x00000008)
|
||||
#define EMAC_ISR_MOS (0x00000002)
|
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#define EMAC_ISR_MOF (0x00000001)
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||||
|
||||
#define EMAC_ISR_SE (0x00200000)
|
||||
#define EMAC_ISR_SYE (0x00100000)
|
||||
#define EMAC_ISR_BFCS (0x00080000)
|
||||
#define EMAC_ISR_PTLE (0x00040000)
|
||||
#define EMAC_ISR_ORE (0x00020000)
|
||||
#define EMAC_ISR_IRE (0x00010000)
|
||||
#define EMAC_ISR_DBDM (0x00000200)
|
||||
#define EMAC_ISR_DB0 (0x00000100)
|
||||
#define EMAC_ISR_SE0 (0x00000080)
|
||||
#define EMAC_ISR_TE0 (0x00000040)
|
||||
#define EMAC_ISR_DB1 (0x00000020)
|
||||
#define EMAC_ISR_SE1 (0x00000010)
|
||||
#define EMAC_ISR_TE1 (0x00000008)
|
||||
#define EMAC_ISR_MOS (0x00000002)
|
||||
#define EMAC_ISR_MOF (0x00000001)
|
||||
|
||||
/* STA CONTROL REG */
|
||||
#define EMAC_STACR_OC (0x00008000)
|
||||
#define EMAC_STACR_PHYE (0x00004000)
|
||||
#define EMAC_STACR_OC (0x00008000)
|
||||
#define EMAC_STACR_PHYE (0x00004000)
|
||||
|
||||
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
|
||||
#define EMAC_STACR_INDIRECT_MODE (0x00002000)
|
||||
#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
|
||||
#define EMAC_STACR_READ (0x00001000) /* $BUC */
|
||||
#define EMAC_STACR_OP_MASK (0x00001800)
|
||||
#define EMAC_STACR_MDIO_ADDR (0x00000000)
|
||||
#define EMAC_STACR_MDIO_WRITE (0x00000800)
|
||||
#define EMAC_STACR_MDIO_READ (0x00001800)
|
||||
#define EMAC_STACR_MDIO_READ_INC (0x00001000)
|
||||
#define EMAC_STACR_INDIRECT_MODE (0x00002000)
|
||||
#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
|
||||
#define EMAC_STACR_READ (0x00001000) /* $BUC */
|
||||
#define EMAC_STACR_OP_MASK (0x00001800)
|
||||
#define EMAC_STACR_MDIO_ADDR (0x00000000)
|
||||
#define EMAC_STACR_MDIO_WRITE (0x00000800)
|
||||
#define EMAC_STACR_MDIO_READ (0x00001800)
|
||||
#define EMAC_STACR_MDIO_READ_INC (0x00001000)
|
||||
#else
|
||||
#define EMAC_STACR_WRITE (0x00002000)
|
||||
#define EMAC_STACR_READ (0x00001000)
|
||||
#define EMAC_STACR_WRITE (0x00002000)
|
||||
#define EMAC_STACR_READ (0x00001000)
|
||||
#endif
|
||||
|
||||
#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
|
||||
|
|
@ -467,9 +458,9 @@ typedef struct emac_4xx_hw_st {
|
|||
#define EMAC_STACR_CLK_100MHZ (0x00000C00)
|
||||
|
||||
/* Transmit Request Threshold Register */
|
||||
#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
|
||||
#define EMAC_TRTR_192 (0x10000000)
|
||||
#define EMAC_TRTR_128 (0x01000000)
|
||||
#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
|
||||
#define EMAC_TRTR_192 (0x10000000)
|
||||
#define EMAC_TRTR_128 (0x01000000)
|
||||
|
||||
/* the follwing defines are for the MadMAL status and control registers. */
|
||||
/* For bits 0..5 look at the mal.h file */
|
||||
|
|
|
|||
Loading…
Reference in a new issue