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2218 commits

Author SHA1 Message Date
Lokesh Vutla
9239f5b625 ARM: OMAP4+: Cleanup header files
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lubomir Popov
e0a8c99e61 OMAP5: Fix bug in omap5_es1_prcm struct
The newly introduced function setup_warmreset_time(), called
from within prcm_init(), tries to write to the prm_rsttime
OMAP5 register. The struct member holding this register's
address is however initialized for OMAP5 ES2.0 only. On ES1.0
devices this uninitialized value causes a second (warm) reset
at startup.

Add .prm_rsttime address init to the ES1.0 struct.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Tom Rini <trini@ti.com>
2013-06-10 08:43:09 -04:00
Andrii Tseglytskyi
e69c585d76 OMAP5: add ABB setup for MPU voltage domain
Patch adds a call of abb_setup() function, and proper registers
definitions needed for ABB setup sequence. ABB is initialized
for MPU voltage domain.

Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
2013-06-10 08:43:09 -04:00
Andrii Tseglytskyi
4d0df9c1e9 OMAP3+: introduce generic ABB support
Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains
starting with OMAP3630. There are three modes of operation:

* Bypass - the default, it just follows the vdd voltage
* Foward Body-Bias - applies voltage bias to increase transistor
  performance at the cost of power.  Used to operate safely at high
  OPPs.
* Reverse Body-Bias - applies voltage bias to decrease leakage and
  save power.  Used to save power at lower OPPs.

Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
2013-06-10 08:43:09 -04:00
Albert ARIBAUD
10e167329b Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/serial/Makefile
2013-06-08 14:35:10 +02:00
Tom Warren
dbc000bfb5 ARM: tegra: only enable SCU on Tegra20
The non-SPL build of U-Boot on Tegra only runs on a single CPU, and
hence there is no need to enable the SCU when running U-Boot. If an
SMP OS is booted, and it needs the SCU enabled, it will enable the SCU
itself. U-Boot doing so is redundant.

The one exception is Tegra20, where an enabled SCU is required for some
aspects of PCIe to work correctly.

Some Tegra SoCs contain CPUs without a software-controlled SCU. In this
case, attempting to turn it on actively causes problems. This is the case
for Tegra114. For example, when running Linux, the first (or at least
some very early) user-space process will trigger the following kernel
message:

Unhandled fault: imprecise external abort (0x406) at 0x00000000

This is typically accompanied by that process receving a fatal signal,
and exiting. Since this process is usually pid 1, this causes total
system boot failure.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, fleshed out description, ported to upstream chipid APIs]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-06-06 09:12:32 -07:00
Tom Rini
edfcf85a0a am33xx/omap4+: Move SRAM_SCRATCH_SPACE_ADDR to <asm/arch/omap.h>
The location of valid scratch space is dependent on SoC, so move that
there.  On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR.  On
am33xx/ti814x we want to use what the ROM defines as "public stack"
which is the area after our defined download image space.  Correct the
comment about and location of CONFIG_SPL_TEXT_BASE.

Signed-off-by: Tom Rini <trini@ti.com>
2013-06-06 08:57:45 -04:00
Tom Rini
4596dcc1d4 am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c
We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common.  Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx.  Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.

Reviewed-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-06-05 08:46:49 -04:00
Tom Rini
320d9746d3 am33xx: Correct NON_SECURE_SRAM_START/END
Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being
used.  As part of correcting these tests, make use of the fact that
we've always been placing our stack outside of the download image area
(which is fine, once the downloaded image is run, ROM is gone) so
correct the max size test to be the ROM defined top of the download area
to where we link/load at.

Signed-off-by: Tom Rini <trini@ti.com>

---
Changes in v2:
- Fix typo noted by Peter Korsgaard
2013-06-04 16:32:31 -04:00
Tom Rini
0ac6db2631 omap-common/hwinit-common.c: Mark omap_rev_string as static
Only called in this file, mark as static.

Signed-off-by: Tom Rini <trini@ti.com>
2013-06-04 16:32:31 -04:00
Inderpal Singh
b5f9756f7f exynos: update tzpc to make it common for exynos4 and exynos5
This requires that cpu_is_exynos4/5 should be made available before tzpc_init.
Hence this patch also makes necessary changes to have cpu_info in spl and
invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-04 15:23:17 +09:00
Inderpal Singh
72af2fc850 exynos: move tzpc_init to armv7/exynos
tzpc_init is common for all exynos5 boards, hence move it to
armv7/exynos so that all other boards can use it.

Also update the smdk5250 Makefile and config file.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-04 15:22:10 +09:00
Marek Vasut
86fb7b3d5b arm: mxs: Fix vectoring table crafting
The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28
starts from RAM, so the vectoring table at 0x0 is not present. Craft
code that will be placed at 0x0 and will redirect interrupt vectoring
to proper location of the U-Boot in RAM.

Signed-off-by: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-06-03 12:49:50 +02:00
Alison Wang
24e8bee508 arm: vf610: Add Vybrid VF610 CPU support
This patch adds generic codes to support Freescale's Vybrid VF610 CPU.

It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.

Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-03 10:56:53 +02:00
Alison Wang
cfd701b5f3 arm: vf610: Add IOMUX support for Vybrid VF610
This patch adds the IOMUX support for Vybrid VF610 platform.

There is a little difference for IOMUXC module between VF610 and i.MX
platform, the muxmode and pad configuration share one 32bit register on
VF610, but they are two independent registers on I.MX platform. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.

Signed-off-by: Alison Wang <b18965@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-03 10:56:53 +02:00
Albert ARIBAUD
3da0e5750b arm: factorize relocate_code routine
Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
2013-05-30 20:24:38 +02:00
Albert ARIBAUD
fa6c7413d1 arm: do not compile relocate_code() for SPL builds
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
2013-05-30 20:24:07 +02:00
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00
Axel Lin
60985bba58 tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL build
Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:44 -07:00
Axel Lin
578e63782b ARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_crit
cpu_init_crit() can be skipped, but the code is still enabled requiring a
platform to supply lowlevel_init().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:43 -07:00
Stephen Warren
20583d04fb ARM: tegra: support SKU 7 of Tegra20
Make U-Boot aware of the Tegra20 SKU 7, and treat it identically
to any other Tegra20.

My Whistler board has a SoC with this SKU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:43 -07:00
Stephen Warren
840167c2c2 ARM: tegra: support SKU 1 of Tegra114
Make U-Boot aware of the Tegra114 SKU 1, and treat it identically
to any other Tegra114.

This value is used on (at least some) Dalmore boards with a production
rather than engineering chip. Such boards are in the hands of some
partners who want to use upstream U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:43 -07:00
Allen Martin
a51f7de161 Tegra: clk: always use find_best_divider() for periph clocks
When adjusting peripheral clocks always use find_best_divider()
instead of clk_get_divider() even when a secondary divider is not
available.  In the case where is requested clock is too slow to be
derived from the parent clock this allows a best effort to get close
to the requested clock.

This comes up for commands like "sf" where the user can pass a clock
speed on the command line or "sspi" where the clock is hardcoded to
1MHz, but the Tegra114 SPI controller can't go that low.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:42 -07:00
Tom Rini
fd72569179 arm: Enable -ffunction-sections / -fdata-sections / --gc-sections
While other architectures have enabled these gcc / ld options for some
time on U-Boot itself, ARM has only been doing this on SPL.  Enable this
on full U-Boot as well now.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-23 12:09:56 +02:00
Akshay Saraswat
234370cab4 Exynos5: clock: Update the equation to calculate PLL output frequency
According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-05-21 20:17:30 +09:00
Bo Shen
3225f34e5c ARM: atmel: add sama5d3xek support
Add sama5d3xek support with following feature
  - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector
  - boot from SPI flash support
  - boot from SD card support
  - LCD support
  - EMAC support
  - USB OHCI support

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-21 11:54:16 +02:00
Bo Shen
284403aadf ARM: at91: add Atmel sama5d3 SoC new pmc register
Add Atmel sama5d3 SoC new pmc register

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-21 11:54:10 +02:00
Simon Glass
6caa195614 arm: Use image_setup_linux() instead of local code
Use the common FDT setup function that is now available in image. Move
the FDT-specific code to a new bootm-fdt.c and remove unused headers
from bootm.c.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-14 15:37:25 -04:00
Simon Glass
c19d13b030 arm: Refactor bootm to reduce #ifdefs
With fewer #ifdefs the code is more readable and more of the code is
compiled for all boards. Add defines in the header file to control
what features are enabled, and then use if() instead of #ifdef.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-14 15:37:25 -04:00
Wu, Josh
a73267a7ce arm: at91: enable mci support for at91sam9g20ek.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-12 16:42:24 +02:00
Wu, Josh
9e33690389 arm: at91: add at91sam9n12ek board support
Add support for following features:
  - nand boot, with PMECC 2bit ECC for 512 bytes sector
  - SPI flash boot
  - SD card boot
  - LCD support

Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix -Wimplicit-function-declaration for at91_lcd_hw_init()]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-12 16:40:42 +02:00
Wu, Josh
e542377a59 arm: at91: add at91sam9n12 register definition
Since at91sam9n12 is a subset of at91sam9x5, so put all at91sam9n12
definitions in at91sam9x5 head file.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-12 16:38:52 +02:00
Albert ARIBAUD
cac423a730 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-05-11 22:24:28 +02:00
Albert ARIBAUD
ec7023db8d Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/mtd/nand/mxc_nand_spl.c
	include/configs/m28evk.h
2013-05-11 09:25:36 +02:00
Albert ARIBAUD
e825b100d2 Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2013-05-11 00:06:03 +02:00
SRICHARAN R
47c6ea076e ARM: OMAP: Add arch_cpu_init function
The boot parameters passed from SPL to UBOOT
must be saved as a part of uboot's gd data
as early as possible, before we will inadvertently
overwrite it. So adding a arch_cpu_init for the required
Socs to save it.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:56 -04:00
SRICHARAN R
4a0eb75752 ARM: OMAP: Cleanup boot parameters usage
The boot parameters are read from individual variables
assigned for each of them. This been corrected and now
they are stored as a part of the global data 'gd'
structure. So read them from 'gd' instead.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:56 -04:00
SRICHARAN R
fda06812a0 ARM: OMAP: Correct save_boot_params and replace with 'C' function
Currently save_boot_params saves the boot parameters passed
from romcode. But this is not stored in a writable location
consistently. So the current code would not work for a
'XIP' boot. Change this by saving the boot parameters in
'gd' which is always writable. Also add a 'C' function
instead of an assembly code that is more readable.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-05-10 08:25:56 -04:00
SRICHARAN R
f92f2277a6 ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
These defines are same across OMAP4/5. So move them to
omap_common.h. This is required for the patches that
follow.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-05-10 08:25:56 -04:00
SRICHARAN R
76db5b8f59 ARM: OMAP: Make omap_boot_parameters common across socs
omap_boot_parameters is same and defined for each
soc. So move this to a common place to reuse it
across socs.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-05-10 08:25:56 -04:00
Tom Rini
30bba01751 am33xx: Fix warning with CONFIG_DISPLAY_CPUINFO
The arm_freq and ddr_freq variables are unused, so remove.  Fixup
whitespace slightly while in here.

Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:56 -04:00
Eric Benard
34fa07063a davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK
these variables are curently defined in several config files but the
driver doesn't use them and defaults to hardcoded values in
nand_defs.h

It's interesting to be able to change this hardcoded valude when the
hardware is not using the default adress signals to drive ALE and CLE
and two configuration defines already exist for this purpose so use
them.

Signed-off-by: Eric Bénard <eric@eukrea.com>
2013-05-10 08:25:56 -04:00
Eric Benard
81ac7e51cc da850: provide davinci_enable_uart0
this is needed to bring UART0 out of reset but this function
currently only exists for dm644x/355/365/646x when da850 (at
least am1808 also need it).

Signed-off-by: Eric Bénard <eric@eukrea.com>
2013-05-10 08:25:56 -04:00
Lokesh Vutla
0b1b60c779 ARM: OMAP5: Fix warm reset with USB cable connected
Warm reset on OMAP5 freezes when USB cable is connected.
Fix requires PRM_RSTTIME.RSTTIME1 to be programmed
with the time for which reset should be held low for the
voltages and the oscillator to reach stable state.

There are 3 parameters to be considered for calculating
the time, which are mostly board and PMIC dependent.
-1- Time taken by the Oscillator to shut + restart
-2- PMIC OTP times
-3- Voltage rail ramp times, which inturn depends on the
PMIC slew rate and value of the voltage ramp needed.

In order to keep the code in u-boot simple, have a way
for boards to specify a pre computed time directly using
the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'
option. If boards fail to specify the time, use a default
as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead.
Using the default value translates into some ~22ms and should work in
all cases.
However in order to avoid this large delay hiding other bugs,
its recommended that all boards look at their respective data
sheets and specify a pre computed and optimal value using
'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'

In order to help future board additions to compute this
config option value, add a README at doc/README.omap-reset-time
which explains how to compute the value. Also update the toplevel
README with the additional option and pointers to
doc/README.omap-reset-time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[rnayak@ti.com: Updated changelog and added the README]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-05-10 08:25:55 -04:00
Lubomir Popov
2bcc785a1e OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work
USB TLL clocks do not support 'explicit_en', only 'hw_auto'
control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be
moved to the clk_modules_hw_auto_essential[] array in order
to make the clock work.

This fix is needed (but not sufficient) for USB EHCI operation
in U-Boot.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-05-10 08:25:55 -04:00
Enric Balletbo i Serra
cc175e6353 Add DDR3 support for IGEP COM AQUILA/CYGNUS.
These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-05-10 08:25:55 -04:00
Lokesh Vutla
166e5cc627 arm: omap: emif: Fix DDR3 init after warm reset
EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.

Tested on OMAP5432 ES2.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-05-10 08:25:55 -04:00
Lubomir Popov
2335b653d1 OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
In order to be able to select one of these buses however, I2C_BUS_MAX
has to be set to 5; do this here.

Please note that for working bus selection, a fix to the i2c driver
is required as well (subject of a separate patch).

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-05-10 08:25:55 -04:00
Lubomir Popov
aebe7ff2b2 OMAP5: I2C: Add I2C4 and I2C5 bases
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The I2C4 and I2C5 base addresses were however not defined; do this
here.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-05-10 08:25:55 -04:00
Lubomir Popov
3935277dbf OMAP5: I2C: Enable i2c5 clocks
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The i2c5 clock was however not enabled; do this here.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-05-10 08:25:55 -04:00
Matt Porter
035d563937 am33xx: add pll and clock support for TI814x CPSW
Enables required PLLs and clocks for CPSW on TI814x.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:54 -04:00
Marek Vasut
38e8ce4189 arm: mxs: Add LCDIF registers for i.MX233
Extend the regs-lcdif.h with registers for i.MX233.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-05-06 17:40:22 +02:00
Marek Vasut
7411cdf0e2 arm: mxs: Add LCDIF clock configuration function
This function turns on the LCDIF clock and configures it's frequency. The
dividers settings are calculated within the function and the current
implementation should be fast and accurate.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-05-06 17:40:22 +02:00
Michal Simek
d5dae85f23 fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.

The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:24 +02:00
Marek Vasut
714dc001fc arm: mxs: Preprocess u-boot.bd so they contain full path
The u-boot-imx23.bd and u-boot-imx28.bd need to be preprocessed, otherwise
they have issues with out-of-tree build where elftosb tool couldn't sometimes
find the u-boot.bin and spl/u-boot-spl.bin .

Preprocess these .bd files with sed and insert full path to u-boot.bin and
spl/u-boot-spl.bin to prevent this issue. Moreover, to avoid adding more
churn into main Makefile, move all this preprocessing and u-boot.sb generation
into CPU directory instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-05-06 10:37:36 +02:00
Marek Vasut
dd3ecf020e arm: mx23: Fix VDDMEM misconfiguration
The VDDMEM ramped up in very weird way as it was horribly misconfigured.
Instead of setting up VDDMEM in one swipe, let it rise slowly the same
way as VDDD and VDDA in spl_power_init.c and then only clear ILIMIT before
memory gets inited. This makes sure the VDDMEM rises sanely, not jumps up
and down as it did till now.

The VDDMEM prior to this change did this:
     2V0____   .--------2V5
       |    `--'
 0V____|

The VDDMEM now does this:
    2V0_____,-----------2V5
      /
 0V__|

Moreover, VDDIO on MX23 uses 25mV steps while MX28 uses 50mV steps,
fix this difference too.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-05-06 10:20:33 +02:00
Fabio Estevam
286a88cf34 mxs: Explain why some mx23 DDR registers are not configured
Put an explanation in the source code as to why some DDR registers do not
need to be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-06 09:55:52 +02:00
Fabio Estevam
26be20fac0 mx23: Operate DDR voltage supply at 2.5V
After the recent fixes in the mx23 DDR setup, it is safe to operate DDR voltage
at the recommended 2.5V voltage level again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-06 09:55:51 +02:00
Łukasz Dałek
2ac2bb7ad2 pxa: Add weak attribute to reset_cpu() function
This commit allows pxa2xx based boards to reimplement reset_cpu()
function with board specific reset sequence.

Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
2013-05-05 23:47:05 +02:00
Mike Dunn
e0e89e236f pxa27x_udc: remove call to unimplemented set_GPIO_mode()
If CONFIG_USB_DEV_PULLUP_GPIO is defined, a link error occurs because the
set_GPIO_mode() helper function is not implemented.  This function doesn't do
much except make the code a little more readable, so I just manually coded its
equivalent and removed the prototype from the header file.  It is invoked no
where else in the code.

While I was at it, I noticed that two other function prototypes in the same
header file are also neither implemented nor invoked anywhere, so I removed them
as well.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-05-05 23:47:05 +02:00
Benoît Thébaudeau
ba5dfc11ba imx: mx5: Remove legacy iomux support
Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2013-05-05 17:55:05 +02:00
Benoît Thébaudeau
3d53fc9450 imx: iomux-v3: Add iomux-mx53.h
Allow usage of the imx-common/iomux-v3.h framework by including pad settings for
the i.MX53. The content of the file is taken from Freescale's Linux kernel at
commit 4ab3715, plus the required changes to make it work in U-Boot.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:04 +02:00
Benoît Thébaudeau
f54326d17d imx: iomux-v3: Add missing definitions to iomux-mx51.h
Add missing definitions that are required by future changes.

By the way, make some cosmetic cleanup.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:04 +02:00
Benoît Thébaudeau
f49d92a35b imx: iomux-mx51: Fix MX51_PAD_EIM_CS2__GPIO2_27
In ALT1 mode, EIM_CS2 is GPIO2[27], not ESDHC1.CD. Hence, rename
MX51_PAD_EIM_CS2__SD1_CD to MX51_PAD_EIM_CS2__GPIO2_27.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:04 +02:00
Benoît Thébaudeau
e2003c16c0 imx: mx35: Remove legacy iomux support
Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:04 +02:00
Benoît Thébaudeau
52b9d3cfd3 imx: iomux-v3: Add iomux-mx35.h
Allow usage of the imx-common/iomux-v3.h framework by including pad settings for
the i.MX35. The content of the file is taken from Linux kernel at commit
267dd34, plus the required changes to make it work in U-Boot.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:03 +02:00
Benoît Thébaudeau
9e933b43f3 imx: mx25: Remove legacy iomux support
Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:03 +02:00
Benoît Thébaudeau
ab3a990b4d imx: iomux-v3: Add iomux-mx25.h
Allow usage of the imx-common/iomux-v3.h framework by including pad settings for
the i.MX25. The content of the file is taken from Linux kernel at commit
267dd34, plus the required changes to make it work in U-Boot.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:02 +02:00
Marek Vasut
f399f63647 arm: mx5: Add NAND clock handling
Augment the MX5 clock code with function to enable and configure
NFC clock. This is necessary to get NFC working on MX5.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-05-05 17:45:05 +02:00
Marek Vasut
cfb8e87a8e arm: mx5: Add SPL support code to MX5
Fix minor adjustments needed to get SPL framework building on MX5.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-05-05 17:45:05 +02:00
Marek Vasut
ae3509dc32 arm: imx: Pack u-boot.bin into uImage for SPL
The U-Boot SPL can parse the uImage format and gather information from
it about the payload. Make use of this and wrap u-boot.bin into uImage
format. The benefit is the SPL will know the size of the payload
instead of using fixed size of the payload defined at compile time.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-05-05 17:45:05 +02:00
Fabio Estevam
fb7383a7a2 mxs: spl_mem_init: Change EMI port priority
FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL
as 0x2, which means:

PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:47 +02:00
Fabio Estevam
39a538d992 mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registers
HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per
FSL bootlets code.

mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved".

HW_DRAM_CTL8 is setup as the last element.

So skip the initialization of these DRAM_CTL registers.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:46 +02:00
Fabio Estevam
b0d4bf9f0c mxs: spl_mem_init: Remove erroneous DDR setting
On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18.

Remove this erroneous setting.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:46 +02:00
Fabio Estevam
8a47c997c5 mxs: spl_mem_init: Fix comment about start bit
Start bit is part of HW_DRAM_CTL8 register, so  fix the comment.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:46 +02:00
Fabio Estevam
9aee34ecab mx23: Fix pad voltage selection bit
On mx23 the pad voltage selection bit needs to be always '0', since '1' is a
reserved value.

For example:

Pin 108, EMI_A06 pin voltage selection:
0= 1.8V (mDDR) or 2.5V (DDR1);
1= reserved.

Fix the pad voltage definitions for the mx23 case.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-05-05 17:08:46 +02:00
Andreas Bießmann
d2eae43ba8 lib: consolidate hang()
Delete all occurrences of hang() and provide a generic function.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01 16:41:08 -04:00
Michal Simek
8934f78465 i2c: zynq: Add support for Xilinx Zynq
Support Xilinx Zynq i2c controller.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:28 +02:00
Michal Simek
293eb33fcb mmc: Add support for Xilinx Zynq sdhci controller
Add support for SD, MMC and eMMC card on Xilinx Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:27 +02:00
Michal Simek
7193653e8d zynq: Move macros to hardware.h
Add all fixed addresses to hardware.h and change petalinux
configuration to support this.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:21 +02:00
Michal Simek
80243528ef net: gem: Fix gem driver on 1Gbps LAN
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:19 +02:00
Michal Simek
4b21284b8c zynq: Move scutimer baseaddr to hardware.h
Move baseaddr to hardware.h to be shared between
configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:12 +02:00
Michal Simek
e072b5f5dc arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addresses
XPSS prefix was used in past and it is obsolete for quite
some time. Let's use correct SoC name which is Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:11 +02:00
David Andrey
d54cc00787 arm: zynq: U-Boot udelay < 1000 FIX
Rework the __udelay function of U-Boot Zynq Arch to handle
delay < 1000 usec

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:10 +02:00
Marek Vasut
6cb83829a0 tools: arm: imx: Implement BOOT_OFFSET command for imximage
Implement BOOT_OFFSET command for imximage. This command is parallel
to current BOOT_FROM command, but allows more flexibility in configuring
arbitrary image header offset. Also add an imximage.cfg with default
offset values into arm/arch/imx-common/ so the board-specific imximage.cfg
can include this file to avoid magic constants.

The syntax of BOOT_OFFSET command is "BOOT_OFFSET <u32 offset>".

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2013-04-28 11:18:03 +02:00
Benoît Thébaudeau
7e2173cf82 imx: iomux-v3: Include PKE and PUE to pad control pull definitions
PUE requires PKE to mean something, as do pull values with PUE, so do not
compell users to explicitly use PKE and PUE everywhere. This is also what is
done on Linux and what has already been done for i.MX51.

By the way, remove some unused pad control definitions.

There is no change of behavior.

Note that SPI_PAD_CTRL was defined by several boards with a pull value, but
without PKE or PUE, which means that no pull was actually enabled in the pad.
This might be a bug in those boards, but this patch does not change the
behavior, so it just removes the meaningless pull value from those definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:07 +02:00
Benoît Thébaudeau
246952083a imx: iomux-v3: Restore Linux's NEW_PAD_CTRL() macro
This macro will be useful for future changes.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:07 +02:00
Benoît Thébaudeau
79a34d3ccc imx: iomux-v3: cosmetic: Reorganize definitions
Keep pad control definitions together, and organize definitions in a more
legible way.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:06 +02:00
Benoît Thébaudeau
d73b97604b imx: iomux-v3: Fix common pad control definitions
Commit dc88403 "iomux-v3: Place pad control definitions into common file" broke
mx51_efikamx because it made i.MX6's pad control definitions conflict with
i.MX51's.

i.MX51's pad control definitions are actually common to some other i.MX
(25/35/53), so move them to the common iomux-v3.h (just like what is done in
Linux's), and select the correct definitions depending on whether CONFIG_MX6 is
defined or not.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:06 +02:00
Benoît Thébaudeau
112fd2ec6c Add mxc_ocotp driver
Add an mxc_ocotp driver for i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:43 +02:00
Benoît Thébaudeau
0f67e09e9e Add fsl_iim driver
Add a fsl_iim driver common to i.MX and MPC.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:41 +02:00
Benoît Thébaudeau
6adbd30203 imx: Add useful fuse definitions
Define the UID (SoC unique ID) fuses, and the fuses available for the user.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:40 +02:00
Benoît Thébaudeau
8f3ff11c1f imx: Homogenize and fix fuse register definitions
IIM:
 - Homogenize prg_p naming (the reference manuals are not always self-consistent
   for that).
 - Add missing SCSx and bank registers.
 - Fix the number of banks on i.MX53.

OCOTP:
 - Rename iim to ocotp in order to avoid confusion.
 - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
   reference manual.
 - Merge the existing spinoff gp1 fuse definition on i.MX6.
 - Fix the number of banks on i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-28 11:07:40 +02:00
Fabio Estevam
cdc203682f mx23: Put back RAM voltage level to its original value
commit 5c2f444c9 (mxs: Reset the EMI block on mx23) changed the DDR voltage
level, which causes mx23evk to fail to load a kernel.

Put back the original values, so that mx23evk can boot a kernel again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
2013-04-28 11:06:27 +02:00
Fabio Estevam
1155d555d6 mx53ard: Move register masks into imx-regs.h
imx-regs.h is more appropriate location for containing register masks.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-04-25 21:48:21 +02:00
Fabio Estevam
11c08d4ec5 mx5: Define a common get_board_rev()
When booting a FSL kernel based on 2.6.35 it is necessary to pass the revision
tag to the kernel.

Place a common weak function into soc.c for such purpose.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-04-25 21:48:21 +02:00
Otavio Salvador
5ed15738d9 wandboard: Add support for Carrier Board MicroSD card
Allow use of the carrier board MicroSD card available in the
Wandboard; this allow for loading alternative system from the other
card for testing or upgrade proposes.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-25 21:34:28 +02:00
Otavio Salvador
08f32f7d25 wandboard: Add card detection for SOM MicroSD card
This add support to identify if the card is connected or not; so it
does not try to communicate with the controller if no card is
available.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-25 21:34:02 +02:00
Fabio Estevam
492938a334 nitrogen6x: Setup CCM_CCOSR register
CKO1 drives sgtl5000 codec clock on nitrogen boards and wandboard.

Doing this setup in the bootloader will allow us to remove a lot of code in
arch/arm/mach-imx/mach-imx6q.c from the mainline kernel.

Also, according to Eric Nelson: "enabling the clock <in the bootloader> will
remove squeal after an ungraceful reboot (watchdog) if hooked up to speakers."

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-25 21:15:49 +02:00
Philip Paeps
3f21501114 mx35 iomux: correct input select register index
Prior to this fix, calls to mxc_iomux_set_input() for registers
after MUX_IN_GPIO2_IN_19 would write to the wrong registers,
possibly resulting in unexpected behaviour.

Signed-off-by: Philip Paeps <philip@paeps.cx>
2013-04-25 21:10:00 +02:00
Stefan Roese
51f329a774 arm: imx: Codingstyle enhancement of include/asm/arch-mx6/crm_regs.h
Add spaces before and after "<<".

Please note that I intentionally didn't wrap the > 80 lines for
the sake of better readability.

Signed-off-by: Stefan Roese <sr@denx.de>
2013-04-25 21:06:56 +02:00
Stefan Roese
b29ca4a158 imx: Add titanium board support (i.MX6 based)
Titanium is a i.MX6 based board from ProjectionDesign / Barco. This
patch adds support for this board with the newly introduced NAND
support for i.MX6.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:40 +02:00
Stefan Roese
ae695b18df mtd: mxs_nand: Add support for i.MX6
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:36 +02:00
Stefan Roese
99193e30b4 dma: Add i.MX6 support to drivers/dma/apbh_dma.c
This will be used by the i.MX6 NAND support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:13 +02:00
Stefan Roese
8870e45996 imx: Move some i.MX common functions into the imx-common directory
This patch moves the following functions into the imx-common
directory:

- mxs_wait_mask_set()
- mxs_wait_mask_clr()
- mxs_reset_block()

These are currently used by i.MX28. But the upcoming GPMI NAND port
for i.MX6 will also use these functions. So lets move them to a
common location to re-use them.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:23:42 +02:00
Stefan Roese
0499218dbc imx: Move some header files from arch-mxs to imx-common
The following headers are moved to a i.MX common location:

- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.h

This way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:22:22 +02:00
Fabio Estevam
25b4aa146a mx6: Add solo-lite variant support
mx6 solo-lite is another member of the mx6 series.

For more information about mx6 solo-lite, please visit:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 09:57:44 +02:00
Fabio Estevam
dc88403e6c iomux-v3: Place pad control definitions into common file
Instead of having the same PAD control definition in each MX6 variant pin file,
place it into a common location.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 09:56:20 +02:00
Stefano Babic
cd53034613 Merge branch 'next' 2013-04-21 11:32:19 +02:00
Simon Glass
dc47e2bc7d exynos: Correct use of 64-bit division
The current code is causing errors like this on my toolchains:

/usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/
ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/
armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o)

Use do_div() to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-17 10:00:40 +09:00
Stefan Roese
59efa051cd arm: imx: Change iomux functions to void type
They never return anything also than 0, so lets change the function
to void instead.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2013-04-16 18:58:47 +02:00
Philip Paeps
04f79536c3 mx35 iomux: correct offsets of IOMUX registers
This makes mxc_iomux_set_input() work correctly.  Previously, the
incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input()
to write to the wrong register, possibly resulting in unexpected
behaviour.

Signed-off-by: Philip Paeps <philip@paeps.cx>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-16 18:58:47 +02:00
Tom Warren
49493cb714 Tegra: Split tegra_get_chip_type() into soc & sku funcs
As suggested by Stephen Warren, use tegra_get_chip() to return
the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for
Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true
function, i.e. tegra_get_chip_sku(), which returns an ID like
TEGRA_SOC_T25, TEGRA_SOC_T33, etc.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
d94c2dbd0a Tegra: Fix MSELECT clock divisors for T30/T114.
A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
b40f734af9 Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
d0edce4fa3 Tegra: Configure L2 cache control reg properly.
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
3ebbbfe4c7 Tegra: Restore cp15 VBAR _start vector write for ARMv7
A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53),
and caused the old monilithic Tegra builds to hang due to an undefined
instruction trap. Previously, the code needed to run on both the
AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register.
I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but
now that we use SPL, and boot the AVP w/o any ARMv7 code, I can
revert my change, and make Aneesh's change apply to Tegra.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-04-15 11:01:37 -07:00
Stephen Warren
eb222d1d7d ARM: tegra: support T33 SKU of Tegra30
Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically
to any other Tegra30.

An alternative would be to simply remove the SKU checking from
tegra_get_chip_type(); most use of the value most likely simply wants
to know the current chip, not the specific SKU. Or, the function could
be split into separate tegra_get_chip() and tegra_get_sku() for the
cases where differentiation really is required.

I wonder whether tegra_get_chip_type() should printf() whenever any
unkown chip/SKU is found, although perhaps the function is called so
early that the printf() wouldn't actually make it to the UART anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-04-15 11:01:37 -07:00
Andre Przywara
c4a4e2e20c ARMv7: start.S: stay in HYP mode if u-boot is entered in it
The KVM and Xen hypervisors for the Cortex-A15 virtualization
implementation need to be entered in HYP mode. Should the primary
board firmware already enter HYP mode (Calxeda firmware does that),
we should not deliberately drop back to SVC mode.
Since U-boot does not use the MMU, running in HYP mode is just fine.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-04-15 18:30:59 +02:00
Albert ARIBAUD
6ebc346111 ARM: fix CONFIG_SPL_MAX_SIZE semantics
Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds
as this file is never used for SPL builds.

Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds
to separately test image (text,data,rodata...) size,
BSS size, and full footprint each against its own max,
and make Tegra boards check full footprint.

Also, output section mmutable is not used in SPL builds.
Remove it.

Finally, update README regarding the (now homogeneous)
semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new
CONFIG_SPL_MAX_FOOTPRINT macro.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-14 16:07:14 +02:00
Albert ARIBAUD
8dc16cf9dd Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-04-14 10:38:37 +02:00
Albert ARIBAUD
f84a7b8f54 ARM: Fix __bss_start and __bss_end in linker scripts
Commit 3ebd1cbc introduced compiler-generated __bss_start
and __bss_end__ and commit c23561e7 rewrote all __bss_end__
as __bss_end. Their merge caused silent and harmless but
potentially bug-inducing clashes between compiler- and linker-
generated __bss_end symbols.

Make __bss_end and __bss_start compiler-only, and create
__bss_base and __bss_limit for linker-only use.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-13 22:37:20 +02:00
Fabio Estevam
0f1411bc8d spi: mxc_spi: Set master mode for all channels
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).

Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.

Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-13 17:46:42 +02:00
Tetsuyuki Kobayashi
4411b2aea7 BUGFIX: arm: data abort in get_bad_stack_swi
When swi instruction is executed, it is expected to get message
"software interrupt" in console and dump registers and reboot, as
do_software_interrupt() in arch/arm/lib/interrupts.c.
But, actually it causes data abort accessing wrong address in get_bad_stack_swi
macro in arch/arm/cpu/v7/start.S.
This patch fixes this problem.

The same mistake in arch/arm/cpu/{arm1136,arm1176,pxa}/start.S.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
2013-04-13 11:12:46 +02:00
Albert ARIBAUD
0c669fd17a Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-04-13 09:39:29 +02:00
Albert ARIBAUD
1812201997 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/video/exynos_fb.c
2013-04-12 22:07:57 +02:00
man.huber@arcor.de
9d0fd10ca1 omap3: Display MHz instead of mHz on the console
The processor is hopefully running with M(ega)Hz and not with m(illi)Hz.

Signed-off-by: Manfred Huber <man.huber@arcor.de>
2013-04-12 15:29:23 -04:00
Tom Rini
86fdb1619a am335x: Really correct DDR timings on new BeagleBone part
The previous timings were done on the internal-only A1 board which has
different DDR part than all later revs.  The timings need a slight
adjustment to be correct in all cases with later revs.

Signed-off-by: Tom Rini <trini@ti.com>
2013-04-12 12:38:16 -04:00
Albert ARIBAUD
c97b6df1ae Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-04-12 08:51:41 +02:00
Benoît Thébaudeau
1a9a91dcfa arm: Make all linker scripts compatible with per-symbol sections
Let all ARM linker scripts handle properly -ffunction-sections
and -fdata-sections. This will be useful for future changes in order to create
symbol-specific sections in common .S files.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:09 +02:00
Benoît Thébaudeau
9ce8e2386c arm1176: Remove unused MMU setup from start.S
Following the removal of the smdk6400 board, the MMU setup code in
arm1176/start.S becomes unused, so remove it. It will still be possible to
restore it later from the Git history if necessary, in which case it should be
moved out of the relocate_code() function.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:09 +02:00
Benoît Thébaudeau
66f30bf983 arm: Remove deprecated and now unused NAND SPL
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
e53232250b arm: Remove support for unused s3c64xx
Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so
remove associated code. It will still be possible to restore it later from the
Git history if necessary.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
52587f1ef8 arm: Remove support for smdk6400
The migration of boards from Makefile to boards.cfg was due for v2012.03, but
smdk6400 did not follow, and it does not build, so move it to scrapyard. It will
still be possible to restore it from the Git history before fixing it.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
7d5a5c79ca imx: Add u-boot-with-nand-spl.imx make target
This image combines the SPL with the i.MX header, the FCB and U-Boot.

For i.MX25/35/51, the FCB is ignored by the boot ROM, so this image is just
useful because it can be programmed on a NAND Flash page boundary.

For i.MX53, the FCB is required by the boot ROM.

This does not support i.MX6 so far because its FCB is more complicated.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
ba5976092f imx: Add u-boot-with-spl.imx make target
This image combines the SPL with the i.MX header and U-Boot. This is a
convenient way of having a single image to program on some boot devices.

The i.MX header has to be added to the SPL before appending U-Boot, so that the
boot ROM loads only the SPL.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
5c6db120fc arm: Remove unused relocate_code() parameters
Commit e05e5de7fa made the 2 1st parameters of
ARM's relocate_code() useless since it moved the code handling them to crt0.S.
So, drop these parameters.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
ac415a5720 arm926ejs: Remove deprecated and now unused NAND SPL
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
da962b7175 nand: mxc: Switch NAND SPL to generic SPL
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fa.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
8b7cd098dd imx: Fix automatic make targets for imx images
Automatically build the 'u-boot.imx' (i.e. imx header + u-boot.bin) and 'SPL'
(i.e. imx header + u-boot-spl.bin) make targets for all imx processors
supporting this header, so for arm926ejs, arm1136 and armv7. Some combinations
were missing.

At the same time, fix the build of SPL targets not supporting the imx header on
arm1136. For arm1136, the 'SPL' make target was forced to build in all cases if
CONFIG_SPL_BUILD was defined, even for non-imx platforms or imx setups without
an imx header.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:06 +02:00
Benoît Thébaudeau
9c5feab76f arm: crt0.S: Remove bogus .globl
The purpose of .globl is to export symbols for ld, not to declare external
symbols.

By the way, use the ENTRY() and ENDPROC() macros to define functions rather than
using .global directly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:06 +02:00
Benoît Thébaudeau
7086e91b0e arm: relocate_code(): Use __image_copy_end for end of relocation
Use __image_copy_end instead of __bss_start for the end of the image to
relocate. This is the same as commit 033ca72, but applied to all ARM start.S.

This is a more appropriate symbol naming for an image copy & relocate feature,
and this also saves a useless copy of data put between __image_copy_end and
__bss_start in linker scripts (e.g. relocation information, or MMU
initialization tables used only before jumping to the relocated image).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
4b3db1cd31 arm: relocate_code(): Remove useless relocation offset computation
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
1dd1276fd8 arm1136: Remove redundant relocate_code() return
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
959eaa74b8 arm: relocate_code() is no longer noreturn
Commit e05e5de7fa made ARM's relocate_code()
return to its caller, but it did not update its declaration accordingly.

Fixing this function declaration fixes dropped C code following calls to
relocate_code().

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
508611bcb7 arm: start.S: Fix _TEXT_BASE for SPL
_TEXT_BASE must be set to CONFIG_SPL_TEXT_BASE for generic SPL, and to
CONFIG_SYS_TEXT_BASE for non-SPL builds.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
e78b140801 imx: mx5: lowlevel_init: Simplify code
Don't use several instructions to build constant values.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-12 07:55:04 +02:00
Jon Hunter
eef6da0326 omap5912-osk: Fix get_timer() and CONFIG_SYS_HZ
The function get_timer() should return time in ms and CONFIG_SYS_HZ
should be set to 1000 by default. Fix both of these items.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
2013-04-10 16:03:02 -04:00
Lubomir Popov
a1c8fb9132 OMAP4: Fix bug in omap4460_volts struct
The omap4460_volts struct was incorrectly referencing tps62361
instead of twl6030 as PMIC for the core and mm voltages (the
tps is used for mpu supply only). This shall lead to bad OPP
settings while booting kernel. Fixing it.

Fix some comments as well.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-04-10 13:05:32 -04:00
Tom Rini
b996a3e9a8 am335x: Update timings for the beaglebone again
After further testing we can run DDR at 400MHz so update the timings
again.

Tested-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Tom Rini <trini@ti.com>
2013-04-10 10:04:40 -04:00
Tom Rini
74f40ea1bc am335x/ti814x: Correct MMC_BOOT_DEVICES_START/END
Given that on TI814x we have MMC1/2 swapped, we also need to swap them
in MMC_BOOT_DEVICES_START/END

Reported-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
2013-04-09 11:40:40 -04:00
Tom Rini
c3d2c24f6c OMAP3/4/5/AM33xx: Correct logic for checking FAT or RAW MMC
In the case of booting from certain peripherals, such as UART, we must
not see what the device descriptor says for RAW or FAT mode because in
addition to being nonsensical, it leads to a hang.  This is why we have
a test currently for the boot mode being within range.  The problem
however is that on some platforms we get MMC2_2 as the boot mode and not
the defined value for MMC2, and in others we get the value for MMC2_2.
This is required to fix eMMC booting on omap5_uevm.

Tested on am335x_evm (UART, NAND, SD), omap3_beagle (NAND, SD on
classic, SD only on xM rev C5) and omap5_uevm (SD, eMMC).

Signed-off-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:34 -04:00
Lokesh Vutla
d3d82e9fc6 arm: omap4: Fix SDRAM AUTO DETECTION
Commit "8602114 omap: emif: configure emif only when required"
breaks SDRAM_AUTO_DETECTION.
The issue is dmm_init() depends on emif_sizes[](SDRAM Auto detection)
done in do_sdram_init(). The above commit moves dmm_init() above
do_sdram_init() because of which dmm_init() uses uninitialized
emif_sizes[].
So instead of using global emif_sizes[], get sdram details locally
and calculate emif sizes.

Reported-by: Michael Cashwell <mboards@prograde.net>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-04-08 11:29:34 -04:00
Lubomir Popov
a8f408a8c4 OMAP: Fix copy-paste bug that did not enable UART4 clock
V2 fixes line wrap issue of the patch itself.

UART3 was enabled twice instead of UART4.

One more cosmetic change in a comment on EMIF clock.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Reviewed-by: R Sricharan <r.sricharan@ti.com>
2013-04-08 11:29:05 -04:00
Hunter, Jon
d1da76e9f8 omap2420-h4: Fix get_timer() and CONFIG_SYS_HZ
The function get_timer() should return time in ms and CONFIG_SYS_HZ
should be set to 1000 by default. Fix both of these items.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
2013-04-08 11:29:05 -04:00
Hunter, Jon
47f58a7357 omap2420-h4: Fix booting from NOR flash
The omap2420-h4 board is using a RAM based address as the linker
location for code. This is causing several problems when attempting
to run the latest u-boot code base on this board from flash. Update
the default linker location for code to be in NOR flash. Please note
that OMAP maps the NOR flash to address 0x08000000 by default and so
use this as the default address for the NOR flash.

Also remove legacy code that attempts to calculate where in flash the
sdata structure, that holds the memory interface configuration data,
is located. By changing the default linker location for code to flash
this is no longer necessary.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
da634ae356 omap_gpmc: change nandecc command
With uppcoming BCH support on OMAP devices we need to decide between differnt
algorithms when switching the ECC engine.  Currently we support 1-bit hammign
and 8-bit BCH on HW backend.

In order to switch between differnet ECC algorithms we need to change the
interface of omap_nand_switch_ecc() also.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
c0ed9179b8 omap3/omap_gpmc.h: add ooblayout for BCH8 as in kernel
This patch adds BCH8 ooblayout for NAND as provided by
0e618ef0a6a33cf7ef96c2c824402088dd8ef48c in linux kernel. This Layout is
currently only provided for 64 byte OOB.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Scott Wood <scottwood@freescale.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
5bf299bc4f asm/omap_gpmc.h: consolidate common defines
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and
arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate
the common parts into a new header.

Introduce a new asm/omap_gpmc.h which defines the command part and pulls in
the architecture specific one.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
86b128d6f7 omap3/cpu.h: add BCH support
This patch adds the BCH result registers to register mapping for OMAP3 gpmc.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Scott Wood <scottwood@freescale.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:05 -04:00
Tom Rini
5aa014d613 am335x: Enable MMC1 clock
We must not assume ROM has enabled the clock for MMC1.

Reported-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-04-08 11:29:05 -04:00
Albert ARIBAUD
fed029f3c3 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-04-04 15:44:57 +02:00
Minkyu Kang
4fdebefa45 exynos: change indentation of defines in cpu.h
Fix the indentation of some defines by tab.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-04 20:17:50 +09:00
Albert ARIBAUD
be08abc242 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-04-04 11:49:32 +02:00
Stephen Warren
5eaa215607 ARM: bcm2835: fix get_timer() to return ms
Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer
driver to conform to this.

Have the timer implementation export a custom API get_timer_us() for use
by the BCM2835 MMC API, which needs us resolution for a HW workaround.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-04-04 08:14:54 +02:00
Fabio Estevam
38e7007725 mx6: Fix get_board_rev() for the mx6 solo case
When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev()
returns 0x62xxx, which is not a value understood by the VPU
(Video Processing Unit) library in the kernel and causes the video playback to
fail.

The expected values for get_board_rev are:
0x63xxx: For mx6quad/dual
0x61xxx: For mx6dual-lite/solo

So adjust get_board_rev() accordingly and make it as weak function, so that we
do not need to define it in every mx6 board file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-04-03 11:36:34 +02:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Akshay Saraswat
07cd5c7495 Exynos: pwm: Remove dead code of function exynos5_get_pwm_clk
As we shall now be using clock_get_periph_rate function.
We find no reason for keeping code in function exynos5_get_pwm_clk.
Hence, removing it.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Padmavathi Venna
e2338704c0 Exynos: pwm: Use generic api to get pwm clk freq
Use generic api to get the pwm clock frequency

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Padmavathi Venna
12a46a384d Exynos: clock: Add generic api to get the clk freq
Add generic api to get the frequency of the required peripherial. This
API gets the source clock frequency and returns the required frequency
by dividing with first and second dividers based on the requirement.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Padmavathi Venna
394d64e45b Exynos: Add peripherial id for pwm
Add peripherial id for pwm inorder to support
generic api to get the clk frequency

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Gabe Black
92809eeed2 Exynos: Tidy up the pwm_config function in the exynos pwm driver
Some small fixes in the exynos pwm driver:

1. NS_IN_HZ is non-sensical since these are not compatible units. This
constant actually describes the number of nanoseconds in a second. Renamed it
to NS_IN_SEC. Also dropped the unnecessary parenthesis.
2. The variable "period" is not used to hold a period, it's used to hold a
frequency. Renamed it to "frequency".
3. tcmp is an unsigned value, so (tcmp < 0) will never be true and the if
which checks that condition will never execute. Also, there should be no
problem if the pwm never switches, so there's no reason to subtract one from
tcmp and therefore no reason to compare it against zero. Removed both ifs. If
they weren't removed, tcmp should be a signed value.
4. Add a check for a 0 period.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Gabe Black
34b5ee1f6a Exynos: Avoid a divide by zero by specifying a non-zero period for pwm 4
The pwm_config function in the exynos pwm driver divides by its period
period parameter. A function was calling pwm_config with a 0ns period and a
0ns duty cycle. That doesn't actually make any sense physically, and results
in a divide by zero in the driver. This change changes the parameters to be a
100000ns period and duty cycle.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Gabe Black
c059f274ad Exynos: pwm: Fix two bugs in the exynos pwm configuration code
First, the "div" value was being used incorrectly to compute the frequency of
the PWM timer. The value passed in is a constant which reflects the value
that would be found in a configuration register, 0 to 4. That should
correspond to a scaling factor of 1, 2, 4, 8, or 16, 1 << div, but div + 1 was
being used instead.

Second, the reset value of the timers were being calculated to give an overall
frequency, thrown out, and set to a maximum value. This was done so that PWM 4
could be used as the system clock by counting down from a high value, but it
was applied indiscriminantly. It should at most be applied only to PWM 4.

This change also takes the opportunity to tidy up the pwm_init function.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Che-Liang Chiou
f24869d3a8 Exynos: Add timer_get_us function
timer_get_us returns the time in microseconds since a certain reference
point of history.  However, it does not guarantee to return an accurate
time after a long period; instead, it wraps around (that is, the
reference point is reset to some other point of history) after some
periods. The frequency of wrapping around is about an hour (or 2^32
microseconds).

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Simon Glass
3d00c0cb96 Exynos: Change get_timer() to work correctly
At present get_timer() does not return sane values. It should count up
smoothly in milliscond intervals.

We can change the PWM to count down at 1MHz, providing a resolution
of 1us and a range of about an hour between required get_timer() calls.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Anatolij Gustschin
d0f34f10f1 Merge branch 'for-v2013.04'
Conflicts:
	drivers/video/Makefile

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-29 13:54:10 +01:00
Akshay Saraswat
acbb1eb772 Exynos: Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using ACE hardware.

Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-03-29 20:10:42 +09:00
Vincent Stehlé
d53e340edf armv7: do not relocate _start twice
The _start symbol is already relocated, so do not add the relocation the second
time in c_runtime_cpu_setup.

This fixes e.g. the abort exception handling path, which ended in double fault
due to bad address in VBAR.

Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
Reported-by: Lubomir Popov <lpopov@mm-sol.com>
2013-03-28 10:15:06 +01:00
R Sricharan
de63ac278c ARM: mmu: Set domain permissions to client access
The 'XN' execute never bit is set in the pagetables. This will
 prevent speculative prefetches to non executable regions. But the
 domain permissions are set as master in the DACR register.
 So the pagetable attribute for 'XN' is not effective. Change the
 permissions to client.

 This fixes lot of speculative prefetch aborts seen on OMAP5
 secure devices.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Tested-by: Vincent Stehle <v-stehle@ti.com>
Cc: Vincent Stehle <v-stehle@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-28 09:10:58 +01:00
R Sricharan
96fdbec2f9 ARM: mmu: Introduce weak dram_bank_setup function
Introduce a weak version of dram_bank_setup function
to allow a platform specific function.

This is used in the subsequent patch to setup dram region
without 'XN' attribute in order to enable the region
under client permissions.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Vincent Stehle <v-stehle@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-28 09:06:49 +01:00
Vincent Stehlé
dfa4138715 ARM: cache: declare set_section_dcache
We declare the set_section_dcache function globally in the cache header, for
later use by e.g. machine specific code.

Signed-off-by: Vincent Stehlé <v-stehle <at> ti.com>
Cc: Tom Rini <trini <at> ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-28 09:06:43 +01:00
Ajay Kumar
71e6ba4655 EXYNOS5: Add device node for DP
Add DT node and bindings documentaion for DP.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 21:23:18 +09:00
Ajay Kumar
9a1313e1c1 EXYNOS5: Add device node for FIMD
Add DT node and bindings documentation for FIMD.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 21:19:09 +09:00
Ajay Kumar
c18222bee8 video: exynos_dp: Remove callbacks from the driver
Replaced the functionality of callbacks by using a standard set of functions.
Instead of implementing and hooking up a callback, put the same code in one of
the standard set of functions by overriding it.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 21:17:15 +09:00
Rajeshwari Shinde
7ee68fe85f EXYNOS5: Add L2 Cache Support.
This patch set adds L2 Cache Support to EXYNOS.

Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 16:53:37 +09:00
Albert ARIBAUD
ebd749da69 Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2013-03-26 10:40:13 +01:00
Albert ARIBAUD
412665b461 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-03-26 09:51:09 +01:00
Tom Warren
2a04a31791 Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config table
SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup
before the MMC driver is added.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:07 -07:00
Tom Warren
e9cd20654c Tegra114: fdt: Add SDMMC (sdhci) nodes for T114 boards (Dalmore for now)
Took these values directly from the kernel dts files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:07 -07:00
Allen Martin
77c42e80b9 tegra114: add SPI driver
Add driver for tegra114 SPI controller.  This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:07 -07:00
Allen Martin
9a38fb4d94 tegra114: fdt: add SPI blocks
Add nodes for t114 SPI controller hardware

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Allen Martin
6a3742fe7a tegra114: fdt: add apbdma block
Add node for apbdma controller hardware.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Allen Martin
78f47b7353 spi: add common fdt SPI driver interface
Add a common interface to fdt based SPI drivers.  Each driver is
represented by a table entry in fdt_spi_drivers[].  If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Allen Martin
7a49ba6e5b tegra: spi: pull register structs out of headers
Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Allen Martin
ff1da6fb5f tegra: spi: rename tegra SPI drivers
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Allen Martin
9000652da0 tegra: remove support for UART SPI switch
This feature was only used for tegra20 seaboard that had a pinmux
conflict on the SPI pins.  These boards were never manufactured, so
remove this support to clean up SPI driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Albert ARIBAUD
b6379e15a7 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-03-24 17:52:22 +01:00
Tom Rini
bd380cf4cf arm: Correct CONFIG_STANDALONE_LOAD_ADDR for AM33XX/OMAP* platforms
All of these platforms have memory starting at 0x80000000, so this is
the correct CONFIG_STANDALONE_LOAD_ADDR for all of them.

Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:12 -04:00
Tom Rini
c7ba18ad4b am335x_evm: Add better timings for the new BeagleBoard DDR3 part
Tested-by: Rao Bodapati <rao@circuitco.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:12 -04:00
Matt Porter
ea7b96b6aa ti814x_evm: add ti814x evm board support
Add TI814X EVM board directory, config file, and MAINTAINERS
entry. Enable build.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Adapt to recent omap_hsmmc requirements, Matt re-tested]
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:12 -04:00
Matt Porter
26fa57842b am33xx: support ti814x mmc reference clock
TI814x has a 192MHz hsmmc reference clock. Select that clock rate
when building for TI814x.

Signed-off-by: Matt Porter <mporter@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
4fab8d7bbd am33xx: add dmm support to emif4 library
Adds a config_dmm() routine to support TI814X DMM configuration.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
8b029f22a6 am33xx: add ti814x specific register definitions
Support the ti814x specific register definitions within
arch-am33xx.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
b2e682f7a0 am33xx: refactor am33xx mux support and add ti814x support
AM33XX and TI814X have a similar mux though the pinmux register
layout and address space differ. Add a separate ti814x mux include
to support the TI814X-specific differences.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-24 12:49:11 -04:00
Matt Porter
b43c17cba6 am33xx: refactor am33xx clocks and add ti814x support
Split clock.c for am335x and ti814x and add ti814x specific
clock support.

Signed-off-by: Matt Porter <mporter@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
3ba65f97cb am33xx: refactor emif4/ddr to support multiple EMIF instances
The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
81df2bab46 am33xx: convert defines from am33xx-specific to generic names
Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Tom Rini
98f92001b3 am33xx: Add required includes to some omap/am33xx code
- In arch/arm/cpu/armv7/omap-common/timer.c,
  drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
  that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
  <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
  as that is the only include which defines things the config uses.

Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Enric Balletbo i Serra
244044e151 ARM: AM33XX: Fix typo that causes an AM duplication in CPU name.
Just fix a typo displaying the CPU info. With CONFIG_DISPLAY_INFO we see
something like AMAM335X-GP rev 0 instead of AM335X-GP rev 0.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
2013-03-24 12:49:10 -04:00
Vaibhav Hiremath
59dcf970d1 am335x: Enable DDR PHY dynamic power down bit for DDR3 boards
Enable DDR PHY dynamic power down bit, which enables
powering down the IO receiver when not performing read.

This also helps in reducing overall power consumption in
low power states (suspend/standby).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:05 -04:00
Stephen Warren
c5d4752c05 ARM: implement erratum 716044 workaround
Add common code to enable the workaround for ARM erratum 716044. This
will be enabled for Tegra.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-22 16:45:22 +01:00
Steve Kipisz
1e7e374b35 am33xx:ddr:Fix config_sdram to work for all DDR
The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.

Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
           Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
2013-03-22 11:12:53 -04:00
Mark Jackson
296de3bbec Initialise correct GPMC WAITx irq for AM33xx
Currently WAIT0 irq is reset and then WAIT1 irq is enabled.
Fix it such that WAIT0 irq is enabled instead.

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-22 10:57:00 -04:00
Mark Jackson
fc33705e66 Allow AM335x MPU core clock speed to be specified in the board config file
Allow AM335x MPU core clock speed to be specified in the board config file.
To use, add the following to the board's config file:-

#define CONFIG_SYS_MPUCLK	<desired clock freq in MHz>

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-22 10:57:00 -04:00
Jeroen Hofstee
0698095af6 lcd, pxafb: move the pxafb to drivers/video
Since the lcd code was compiled unconditionally for pxa also add
CONFIG_PXA_LCD to the boards using this framebuffer. Since
driver/video contains video and lcd drivers, add lcd to the name
to make clear it belongs to common/lcd.c.

cc: Anatolij Gustschin <agust@denx.de>
cc: Cliff Brake <cliff.brake@gmail.com>
cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2013-03-21 09:38:21 +01:00
Wolfgang Denk
46d1d5dd43 common/lcd.c: cleanup use of global variables
lcd_color_fg and lcd_color_bg had to be declared in board specific
code, but were not actually used there; in addition, we have getter /
setter functions for these, which were not used either.

Get rid of the global variables, and use the getter function where
needed (so far no setter calls are needed).

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Alessandro Rubini <rubini@unipv.it>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
[agust: also fixed cm_t35 board while rebasing]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-21 09:05:08 +01:00
Stephen Warren
131a1e603b ARM: rpi_b: enable SD controller, add related env/cmds
Enable the SD controller driver for the Raspberry Pi. Enable a number
of useful MMC, partition, and filesystem-related commands. Set up the
environment to provide standard locations for loading a kernel, DTB,
etc. Provide a boot command that loads and executes boot.scr.uimg from
the SD card; this is written considering future extensibilty to USB
storage.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-03-20 15:32:16 +01:00
Stephen Warren
9a4fbe4fbd mmc: add bcm2835 driver
This adds a simple driver for the BCM2835's SD controller.

Workarounds are implemented for:
* Register writes can't be too close to each-other in time, or they will
  be lost.
* Register accesses must all be 32-bit, so implement custom accessors.

This code was extracted from:
git://github.com/gonzoua/u-boot-pi.git master
which was created by Oleksandr Tymoshenko.

Portions of the code there were obviously based on the Linux kernel at:
git://github.com/raspberrypi/linux.git rpi-3.6.y
commit f5b930b "Main bcm2708 linux port" signed-off-by Dom Cobley.

swarren changed the following for upstream:
* Removed hack udelay()s in bcm2835_sdhci_raw_writel(); setting
  SDHCI_QUIRK_WAIT_SEND_CMD appears to solve the issues.
* Remove register logging from read*/write* functions.
* Sort out confusion with min/max_freq values passed to add_sdhci().
* Use more descriptive variable names and calculations in IO accessors.
* Simplified and commented twoticks_delay calculation.
* checkpatch fixes.

Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Andy Fleming <afleming@gmail.com>
2013-03-20 15:31:25 +01:00
Stephen Warren
88077280c4 ARM: bcm2835: add mailbox driver
The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
and the ARM CPU. The ARM CPU is often thought of as the main CPU.
However, the VideoCore actually controls the initial SoC boot, and hides
much of the hardware behind a protocol. This protocol is transported
using the SoC's mailbox hardware module.

Here, we add a very simplistic driver for the mailbox module, and define
a few structures for the property messages.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-03-20 15:29:20 +01:00
Fabio Estevam
e2d282a1b4 Add initial support for Wandboard dual lite and solo.
Wandboard is a development board that has two variants: one version based
on mx6 dual lite and another one based on mx6 solo.

For more details about Wandboard, please refer to: http://www.wandboard.org/

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-03-20 11:47:37 +01:00
Eric Nelson
99e2dc59cb i.MX6: Add hdmidet command to detect attached HDMI monitor
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-03-20 11:43:19 +01:00
Knut Wohlrab
982a3c410e imx-common: timer: fix 32-bit overflow
The i.MX6 common timer uses the 32-bit variable tbl (time base lower)
to record the overflow of the 32-bit counter. I.e. if the counter
overflows, the variable tbl does overflow, too.

To capture this overflow, use the variable tbu (time base upper), too.
Return the combined value of tbl and tbu.

lastinc is unused then, remove it.

Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-03-20 11:36:11 +01:00
Fabio Estevam
b33426caf6 mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
Currently the following kernel hang happens when loading a 2.6.35 kernel from
Freeescale on a mx28evk board:

RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Bus freq driver module loaded
IMX usb wakeup probe
usb h1 wakeup device is registered
mxs_cpu_init: cpufreq init finished
...

Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01
package, the hang does not occur.

Comparing the DDR2 initialization from the bootlets code against the U-boot
one, we can notice some mismatches, and after applying the same initialization
into U-boot the 2.6.35 kernel can boot normally.

Also tested with 'mtest' command, which runs succesfully.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Marek Vasut <marex@denx.de>
2013-03-20 11:05:32 +01:00
Tom Rini
0ce033d258 Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-18 14:37:18 -04:00
Simon Glass
959daa21d4 arm: Enable generic board support
This enables generic board support so that ARM boards can define
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
e103b7ae90 arm: Use sections header to obtain link symbols
Include this header to get access to link symbols, which are otherwise
removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Simon Glass
1865286466 Introduce generic link section.h symbol files
We create a separate header file for link symbols defined by the link
scripts. It is helpful to have these all in one place and try to
make them common across architectures. Since Linux already has a similar
file, we bring this in even though many of the symbols there are not
relevant to us.

Each architecture has its own asm/sections.h where symbols specifc to
that architecture can be added. For now everything except AVR32 just
includes the generic header.

One change is needed in arch/avr32/lib/board.c to make this conversion
work.

Reviewed-by: Tom Rini <trini@ti.com> (version 5)
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Simon Glass
3929fb0a14 Replace __bss_end__ with __bss_end
Note this is a tree-wide change affecting multiple architectures.

At present we use __bss_start, but mostly __bss_end__. This seems
inconsistent and in a number of places __bss_end is used instead.

Change to use __bss_end for the BSS end symbol throughout U-Boot. This
makes it possible to use the asm-generic/sections.h file on all
archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:54 -04:00
Albert ARIBAUD
b27673ccbd Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2013-03-15 20:50:43 +01:00
Albert ARIBAUD
6579d15c58 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-03-15 15:18:31 +01:00
Tom Warren
477393e787 Tegra114: Dalmore: Add pad config tables/code based on pinmux code
Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, no padcfg entries exist. SDIO3CFG will be added when the
MMC driver is added as per the TRM to work with the SD-card slot on
Dalmore E1611.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:49:14 -07:00
Tom Warren
5647c03431 Tegra114: fdt: Move aliases from dtsi to dts file as per other Tegras
All other Tegra boards have their alias nodes in the .dts file

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:49:07 -07:00
Tom Warren
36c48be110 Tegra114: Fix/update GP padcfg register struct
Differences in padcfg registers (some removed, some added) between
Tegra30 and Tegra114 weren't picked up when I first ported this file.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:48:05 -07:00
Tom Warren
b3b6ddff0b Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entry
This caused CAM_MCLK's pinmux reg to be locked out, since the
table parsing code couldn't find a matching entry for VI_ALT3
and wrote garbage to the register.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:08:57 -07:00
Tom Warren
38797bcb1f Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30
Removed SDMMC base addresses from tegra.h since they're no longer used.
Added additional vendor-specific SD/MMC registers and bus power defines.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:44 -07:00
Tom Warren
1baa4e72c6 Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)
Took these values directly from the kernel dts files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:44 -07:00
Tom Warren
8ca79b2ff4 Tegra30: Cardhu: Add pad config tables/code based on pinmux code
Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, only SDIO1CFG is changed as per the TRM to work with
the SD-card slot on Cardhu.

Thanks to StephenW for the suggestion/original idea.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Tom Warren
8b7776b9f9 Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 init
Use the latest tables & code from our internal U-Boot repo.
The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup
table were off by a few indices, causing the pinmux init code to
write bad data to the PINMUX_AUX_ regs. This also enabled the lock
bit, which made it impossible to reconfig the pads correctly for
SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N,
USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Tom Warren
19a970af28 Tegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car)
Minor edit to tegra_car node, add gpio node.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Stephen Warren
16bb08d19a ARM: tegra: implement WAR for Tegra114 CPU reset vector
A Tegra114 HW bug prevents the main CPU vector from being modified under
certain circumstances. Tegra114 A01P and later with a patched boot ROM
set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing
an arbitrary jump instruction at that location, in order to redirect to
the desired reset vector location. Modify Tegra114's start_cpu() to make
use of this feature. This allows CPUs with the patched boot ROM to boot.

Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Tom Warren
527519ae69 Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)
Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Tom Warren
c9aa831ee2 Tegra: MMC: Add DT support to MMC driver for all T20 boards
tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:42 -07:00
Tom Warren
126685ad44 Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files
Linux dts files were used for those boards that didn't already
have sdhci info populated. Tamonten has their own dtsi file with
common sdhci nodes (sourced from Linux).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:42 -07:00
Tom Warren
6c5be646b4 Tegra: fdt: Change /include/ to #include for C preprocessor
dts Makefile has the arch & board include paths added to DTS_CPPFLAGS.
This allows the use of '#include "xyz"' in the dts/dtsi file which
helps the C preprocessor find common dtsi include files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:42 -07:00
Tom Warren
b77c3547e8 Tegra114: fdt: Update DT files with I2C info for T114/Dalmore
T114, like T30, does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Tom Warren
e32624ef82 Tegra: I2C: Add T114 clock support to tegra_i2c driver
T114 has a slightly different I2C clock, with a new (extra) divisor
in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C
clock is 100KHz +/- 3Hz on my Saleae Logic analyzer.

Added a new entry in compat_names for T114 I2C since it differs
from the previous Tegra SoCs. A flag is set when T114 I2C HW is
found so new features like the extra clock divisor can be used.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-03-14 11:06:41 -07:00
Tom Warren
702b872894 Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to work
I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives).
This is needed so that the SDIO slot power can be brought up for
the MMC driver, so it has to precede those commits.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
d7a55e1a4b tegra: usb: move [start|stop]_port into ehci_hcd_[init|stop]
The ehci_hcd entry points were just calling into the Tegra USB
functions. Now that they are in the same file we can just move over the
implementation.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
7ae18f3725 tegra: usb: move implementation into right directory
This moves the Tegra USB implementation into the drivers/usb/host
directory. Note that this merges the old
/arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code
changes, just moving stuff around.

v2: While at it also move some defines and the usb.h header file to make
usb driver usable for Tegra30.
NOTE: A lot more work is required to properly init the PHYs and PLL_U on
Tegra30, this is just to make porting easier and it does no harm here.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
a63eb6bbcc tegra: usb: various small cleanups
Remove unneeded headers, function prototype and stale comment, that
doesn't match the actual codebase anymore.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
fdb4b9a71c tegra: usb: move controller init into start_port
There is no need to init a USB controller before the upper layers indicate
that they are actually going to use it.

board_usb_init now only parses the device tree and sets up the common pll.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
a4bdcc38c9 tegra: usb: remove unneeded function parameter
Just a dead parameter, never actually used.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:40 -07:00
Lucas Stach
b0bbab8a14 tegra: usb: make controller init functions more self contained
There is no need to pass around all those parameters. The init functions
are able to easily extract all the needed setup info on their own.

This allows to move out the controller init into ehci_hcd_init later
on, without having to save away global state for later use  and thus
bloating the file global state.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:40 -07:00
Lucas Stach
2f3ec34027 tegra: usb: set USB_PORTS_MAX to correct value
Both Tegra20 and Tegra30 have a max of 3 USB controllers.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:40 -07:00
Stephen Warren
0678587fb6 ARM: implement some Cortex-A9 errata workarounds
Various errata exist in the Cortex-A9 CPU, and may be worked around by
setting some bits in a CP15 diagnostic register. Add code to implement
the workarounds, enabled by new CONFIG_ options.

This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
and modified to remove the logic to conditionally apply the WAR (since we
know exactly which CPU we're running on given the U-Boot configuration),
and use r0 instead of r10 for consistency with the rest of U-Boot's
cpu_init_cp15().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-03-13 22:24:11 +01:00
Albert ARIBAUD
ef123c5253 Refactor linker-generated arrays
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.

Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
	arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
	arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
	board/ait/cam_enc_4xx/u-boot-spl.lds
	board/davinci/da8xxevm/u-boot-spl-da850evm.lds
	board/davinci/da8xxevm/u-boot-spl-hawk.lds
	board/vpac270/u-boot-spl.lds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:40 +01:00
Albert ARIBAUD
3ebd1cbc49 arm: make __bss_start and __bss_end__ compiler-generated
Turn __bss_start and __bss_end__ from linker-generated
to compiler-generated symbols, causing relocations for
these symbols to change type, from R_ARM_ABS32 to
R_ARM_RELATIVE.

This should have no functional impact, as it affects
references to __bss_start and __bss_end__ only before
relocation, and no such references are done.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:32 +01:00
Albert ARIBAUD
65cdd6430e Remove linker lists (LGAs) from SPL linker scripts
Many SPL linker scripts needlessly include linker lists (aka LGAs).
Remove them whenever possible; keep it only in the seven am335x_evm
variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot),
where there is actual content in output section .u_boot_list.

This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets
byte-identical.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:29 +01:00
Albert ARIBAUD
2fd34f2636 arm: omap: map u_boot_lists section to .sram
Output section .u_boot_list was left unmapped in
u-boot-spl.lds for omap-common, causing the location
counter to roll back to bteween .rodata and .data,
making __image_copy_end and _end symbols wrong.

Mapping output section .u_boot_list to memory .sram
fixes these symbols' mapping.

This modifies the SPL binary but has no functional
impact, as __image_copy_end and _end are never used
in SPLs and u_boot_list is empty for all 29 boards
affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3
omap3_beagle am3517_crane igep0032 mt_ventoux pcm051
am3517_evm omap3_evm_quick_mmc am335x_evm_uart2
am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand
omap3_overo igep0020 am335x_evm omap4_panda omap5_evm
am335x_evm_uart4 devkit8000 tricorder mcx twister
omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand).

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:26 +01:00
Albert ARIBAUD
1acba3345c Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-03-12 17:27:44 +01:00
Jesse Gilles
08f0533a14 ARM: sam9x5: fix ethernet pins in MII mode
Fix pin setting in MII mode

Signed-off-by: Jesse Gilles <jgilles@multitech.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-03-12 13:02:20 +01:00
Bo Shen
fc14fbace4 ARM: at91sam9x5: Using CPU string directly
As the CPU name is not configurable, using CPU string directly

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-03-12 13:02:13 +01:00
Akshay Saraswat
3a0b1dae5b Exynos5: TMU: Add hardware tripping
This adds hardware tripping at 110 degrees celsius which must enable
forced system shutdown in case TMU fails to power off.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 17:07:31 +09:00
Akshay Saraswat
618766c098 Exynos5: FDT: Add TMU device node values
Fdt entry for Exynos TMU driver specific pre-defined values used for
calibration of current temperature and defining threshold values.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 17:06:06 +09:00
Akshay Saraswat
39d182d3de Exynos5: TMU: Add driver for Thermal Management Unit
Adding Exynos Thermal Management Unit driver to monitor SOC
temperature and take actions corresponding to states of TMU.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 17:06:03 +09:00
Simon Glass
c42ffff02a EXYNOS: Correct ordering of SPL machine_params
The mem_manuf is not in the correct order according to the string table.
This causes cros_bundle_firmware to get the BL2 settings in the wrong
order. This patch fixes the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 10:35:09 +09:00
Tom Rini
76b40ab41e Merge u-boot/master into u-boot-ti/master
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
	arch/arm/include/asm/arch-davinci/gpio.h
	drivers/gpio/da8xx_gpio.c

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-11 12:16:13 -04:00
Lokesh Vutla
de62688bb6 arm: dra7xx: Add silicon id support for DRA752 soc
Adding CPU detection support for the DRA752 ES1.0 soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:39:57 -04:00
Lokesh Vutla
687054a7e0 arm: dra7xx: Add board files for DRA7XX socs
Adding new board files for DRA7XX socs.
The pad registers layout is changed completely from OMAP5
So introducing the new structure here and also adding the
minimal data.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishant Kamat <nskamat@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Adapt omap_mmc_init call for last 2 params]
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-11 11:39:30 -04:00
Lokesh Vutla
7831419d7b arm: dra7xx: Add DDR related data for DRA752 ES1.0
DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
8b12f1779e arm: dra7xx: Add control module changes
Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
ea8eff1fe0 arm: dra7xx: clock: Add the dplls data
A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
d4e4129c31 arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
d4d986ee27 ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
	 The 1 in wkup domain is not enabled because smart i/os
	 of wkup domain work with default compensation code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
9100edecf8 ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for
OMAP543X SOCs here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
47abc3df70 ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum
Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.

While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x

Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
afc2f9dcf1 ARM: OMAP5: clock: Add the prcm register changes required for ES2.0
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
eed7c0f727 ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
ef1697e99f ARM: OMAP5: Clean up iosettings code
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids unnessecary code addition for future socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
c43c8339fe ARM: OMAP4+: Make control module register structure generic
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
e05a4f1f54 ARM: OMAP4+: Cleanup emif specific files
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.

These change reduces code addition for future Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
3fcdd4a5f8 ARM: OMAP4+: Clean up the pmic code
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
ee9447bfe3 ARM: OMAP4+: Cleanup the clocks layer
Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.

This helps in addition of a new Soc with minimal
changes.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:09 -04:00
SRICHARAN R
01b753ff7b ARM: OMAP4+: Change the PRCM structure prototype common for all Socs
The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.

Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-03-11 11:06:09 -04:00
Lokesh Vutla
9ca8bfea80 ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:09 -04:00
Mark Jackson
6b3dcc45c4 Allow AM33xx boards to setup GPMC chipselects.
Expose the enable_gpmc_cs_config() function so AM33xx based boards can register GPMC chip selects.

Changes in V4:
- Fix checkpatch errors (TAB -> space mangling)

Changes in V3:
- Fix line wrapping

Changes in V2:
- Indicate this is for AM33xx (not OMAP2)

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-11 11:06:08 -04:00
Enric Balletbo i Serra
b51a5e3a0a OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.
In order to use SPL boot from OneNAND we should initialize the gpmc.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-03-11 11:06:08 -04:00
Enric Balletbo i Serra
66c7f39923 SPL: ONENAND: Fix some ONENAND related defines.
Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-03-08 16:41:14 -05:00
Nikita Kiryanov
bcc6cc9b37 omap3: allow dynamic selection of gfx_format
Currently, omap3_dss_panel_config() sets gfx_format to a value that is hardcoded
in the code. This forces anyone who wants to use a different gfx_format to make
adjustments after calling omap3_dss_panel_config(). This could be avoided if the
value of gfx_format were parameterized as input for omap3_dss_panel_config().

Make gfx_format a field in struct panel_config, and update existing structs to
set this field to the value that was originally hard coded.

Cc: Wolfgang Denk <wd@denx.de>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
bc84b18f75 omap3: add useful dss defines
Add useful omap3 dss defines for: polarity, TFT data lines, lcd
display type, gfx burst size, and gfx format

Cc: Anatolij Gustschin <agust@denx.de>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
e3913f56a2 omap_hsmmc: add driver check for write protection
Add check for write protection in omap mmc driver.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
e874d5b001 omap_hsmmc: implement driver check for card detection
Implement driver check for card detection.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
fa3a69289f omap: consolidate common mmc definitions
The various mmc_host_def.h files are almost identical.
Reduce code duplication by moving the similar definitions to a common
header file.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:12 -05:00
Tom Rini
1c382ead7a am33xx: Update DDR3 EMIF configuration sequence
Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what
the TRM describes as the correct sequence.  In our current (incorrect)
sequence some edge cases may fail to initalize correctly.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-08 16:41:12 -05:00
Rajeshwari Shinde
a006076b15 EXYNOS5: Add function to enable XXTI clock source
This patch adds funtion to enable XXTI clock source
required by MAX98095 codec.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-08 22:34:18 +09:00
Stephen Warren
8f3937761b ARM: mx6: use common CPU errata config options
Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2013-03-07 18:20:37 +01:00
Fabio Estevam
1b097cff51 mx6: Provide a structure for accessing HDMI registers
Provide a structure for accessing HDMI registers, so that we can use proper
read/write accessors.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 18:03:44 +01:00
Fadil Berisha
3e9dc93051 mxs: timrot: Rename local macros
Local macros apply to both iMX23 and iMX28. This patch renames local
macros with attribute MX28 to MXS.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:50:55 +01:00
Fadil Berisha
6ecd05d2f5 mxs: timrot: Add support to i.MX23
This patch add timer support to i.MX23 and complete bit fields and values
on regs-timrot.h.
Testet on imx23-olinuxino board.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-03-07 17:22:58 +01:00