mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-17 15:27:00 +00:00
imx: mx25: Remove legacy iomux support
Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
parent
b597ff6be9
commit
9e933b43f3
3 changed files with 0 additions and 570 deletions
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@ -27,7 +27,6 @@
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx25-pinmux.h>
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#include <asm/arch/clock.h>
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#ifdef CONFIG_FSL_ESDHC
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@ -248,123 +247,7 @@ int cpu_mmc_init(bd_t *bis)
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}
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#endif
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#ifdef CONFIG_MXC_UART
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void mx25_uart1_init_pins(void)
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{
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struct iomuxc_mux_ctl *muxctl;
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struct iomuxc_pad_ctl *padctl;
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u32 inpadctl;
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u32 outpadctl;
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u32 muxmode0;
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
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muxmode0 = MX25_PIN_MUX_MODE(0);
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/*
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* set up input pins with hysteresis and 100K pull-ups
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*/
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inpadctl = MX25_PIN_PAD_CTL_HYS
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| MX25_PIN_PAD_CTL_PKE
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| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
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/*
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* set up output pins with 100K pull-downs
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* FIXME: need to revisit this
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* PUE is ignored if PKE is not set
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* so the right value here is likely
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* 0x0 for no pull up/down
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* or
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* 0xc0 for 100k pull down
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*/
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outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
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/* UART1 */
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/* rxd */
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writel(muxmode0, &muxctl->pad_uart1_rxd);
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writel(inpadctl, &padctl->pad_uart1_rxd);
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/* txd */
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writel(muxmode0, &muxctl->pad_uart1_txd);
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writel(outpadctl, &padctl->pad_uart1_txd);
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/* rts */
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writel(muxmode0, &muxctl->pad_uart1_rts);
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writel(outpadctl, &padctl->pad_uart1_rts);
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/* cts */
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writel(muxmode0, &muxctl->pad_uart1_cts);
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writel(inpadctl, &padctl->pad_uart1_cts);
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}
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#endif /* CONFIG_MXC_UART */
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#ifdef CONFIG_FEC_MXC
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void mx25_fec_init_pins(void)
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{
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struct iomuxc_mux_ctl *muxctl;
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struct iomuxc_pad_ctl *padctl;
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u32 inpadctl_100kpd;
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u32 inpadctl_22kpu;
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u32 outpadctl;
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u32 muxmode0;
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
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muxmode0 = MX25_PIN_MUX_MODE(0);
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inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
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| MX25_PIN_PAD_CTL_PKE
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| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
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inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
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| MX25_PIN_PAD_CTL_PKE
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| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
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/*
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* set up output pins with 100K pull-downs
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* FIXME: need to revisit this
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* PUE is ignored if PKE is not set
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* so the right value here is likely
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* 0x0 for no pull
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* or
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* 0xc0 for 100k pull down
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*/
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outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
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/* FEC_TX_CLK */
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writel(muxmode0, &muxctl->pad_fec_tx_clk);
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writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
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/* FEC_RX_DV */
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writel(muxmode0, &muxctl->pad_fec_rx_dv);
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writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
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/* FEC_RDATA0 */
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writel(muxmode0, &muxctl->pad_fec_rdata0);
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writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
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/* FEC_TDATA0 */
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writel(muxmode0, &muxctl->pad_fec_tdata0);
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writel(outpadctl, &padctl->pad_fec_tdata0);
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/* FEC_TX_EN */
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writel(muxmode0, &muxctl->pad_fec_tx_en);
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writel(outpadctl, &padctl->pad_fec_tx_en);
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/* FEC_MDC */
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writel(muxmode0, &muxctl->pad_fec_mdc);
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writel(outpadctl, &padctl->pad_fec_mdc);
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/* FEC_MDIO */
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writel(muxmode0, &muxctl->pad_fec_mdio);
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writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
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/* FEC_RDATA1 */
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writel(muxmode0, &muxctl->pad_fec_rdata1);
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writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
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/* FEC_TDATA1 */
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writel(muxmode0, &muxctl->pad_fec_tdata1);
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writel(outpadctl, &padctl->pad_fec_tdata1);
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}
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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int i;
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@ -1,421 +0,0 @@
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/*
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* iopin settings are controlled by four different sets of registers
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* iopad mux control
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* individual iopad setup (voltage select, pull/keep, drive strength ...)
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* group iopad setup (same as above but for groups of signals)
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* input select when multiple inputs are possible
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*/
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/*
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* software pad mux control
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*/
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/* SW Input On (Loopback) */
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#define MX25_PIN_MUX_SION (1 << 4)
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/* MUX Mode (0-7) */
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#define MX25_PIN_MUX_MODE(mode) ((mode & 0x7) << 0)
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struct iomuxc_mux_ctl {
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u32 gpr1;
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u32 observe_int_mux;
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u32 pad_a10;
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u32 pad_a13;
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u32 pad_a14;
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u32 pad_a15;
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u32 pad_a16;
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u32 pad_a17;
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u32 pad_a18;
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u32 pad_a19;
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u32 pad_a20;
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u32 pad_a21;
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u32 pad_a22;
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u32 pad_a23;
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u32 pad_a24;
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u32 pad_a25;
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u32 pad_eb0;
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u32 pad_eb1;
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u32 pad_oe;
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u32 pad_cs0;
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u32 pad_cs1;
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u32 pad_cs4;
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u32 pad_cs5;
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u32 pad_nf_ce0;
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u32 pad_ecb;
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u32 pad_lba;
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u32 pad_bclk;
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u32 pad_rw;
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u32 pad_nfwe_b;
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u32 pad_nfre_b;
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u32 pad_nfale;
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u32 pad_nfcle;
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u32 pad_nfwp_b;
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u32 pad_nfrb;
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u32 pad_d15;
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u32 pad_d14;
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u32 pad_d13;
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u32 pad_d12;
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u32 pad_d11;
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u32 pad_d10;
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u32 pad_d9;
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u32 pad_d8;
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u32 pad_d7;
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u32 pad_d6;
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u32 pad_d5;
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u32 pad_d4;
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u32 pad_d3;
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u32 pad_d2;
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u32 pad_d1;
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u32 pad_d0;
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u32 pad_ld0;
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u32 pad_ld1;
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u32 pad_ld2;
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u32 pad_ld3;
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u32 pad_ld4;
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u32 pad_ld5;
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u32 pad_ld6;
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u32 pad_ld7;
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u32 pad_ld8;
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u32 pad_ld9;
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u32 pad_ld10;
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u32 pad_ld11;
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u32 pad_ld12;
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u32 pad_ld13;
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u32 pad_ld14;
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u32 pad_ld15;
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u32 pad_hsync;
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u32 pad_vsync;
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u32 pad_lsclk;
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u32 pad_oe_acd;
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u32 pad_contrast;
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u32 pad_pwm;
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u32 pad_csi_d2;
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u32 pad_csi_d3;
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u32 pad_csi_d4;
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u32 pad_csi_d5;
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u32 pad_csi_d6;
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u32 pad_csi_d7;
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u32 pad_csi_d8;
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u32 pad_csi_d9;
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u32 pad_csi_mclk;
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u32 pad_csi_vsync;
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u32 pad_csi_hsync;
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u32 pad_csi_pixclk;
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u32 pad_i2c1_clk;
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u32 pad_i2c1_dat;
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u32 pad_cspi1_mosi;
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u32 pad_cspi1_miso;
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u32 pad_cspi1_ss0;
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u32 pad_cspi1_ss1;
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u32 pad_cspi1_sclk;
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u32 pad_cspi1_rdy;
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u32 pad_uart1_rxd;
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u32 pad_uart1_txd;
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u32 pad_uart1_rts;
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u32 pad_uart1_cts;
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u32 pad_uart2_rxd;
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u32 pad_uart2_txd;
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u32 pad_uart2_rts;
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u32 pad_uart2_cts;
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u32 pad_sd1_cmd;
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u32 pad_sd1_clk;
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u32 pad_sd1_data0;
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u32 pad_sd1_data1;
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u32 pad_sd1_data2;
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u32 pad_sd1_data3;
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u32 pad_kpp_row0;
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u32 pad_kpp_row1;
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u32 pad_kpp_row2;
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u32 pad_kpp_row3;
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u32 pad_kpp_col0;
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u32 pad_kpp_col1;
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u32 pad_kpp_col2;
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u32 pad_kpp_col3;
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u32 pad_fec_mdc;
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u32 pad_fec_mdio;
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u32 pad_fec_tdata0;
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u32 pad_fec_tdata1;
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u32 pad_fec_tx_en;
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u32 pad_fec_rdata0;
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u32 pad_fec_rdata1;
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u32 pad_fec_rx_dv;
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u32 pad_fec_tx_clk;
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u32 pad_rtck;
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u32 pad_de_b;
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u32 pad_gpio_a;
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u32 pad_gpio_b;
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u32 pad_gpio_c;
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u32 pad_gpio_d;
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u32 pad_gpio_e;
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u32 pad_gpio_f;
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u32 pad_ext_armclk;
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u32 pad_upll_bypclk;
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u32 pad_vstby_req;
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u32 pad_vstby_ack;
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u32 pad_power_fail;
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u32 pad_clko;
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u32 pad_boot_mode0;
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u32 pad_boot_mode1;
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};
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/*
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* software pad control
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*/
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/* Select 3.3 or 1.8 volts */
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#define MX25_PIN_PAD_CTL_DVS_33 (0 << 13)
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#define MX25_PIN_PAD_CTL_DVS_18 (1 << 13)
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/* Enable hysteresis */
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#define MX25_PIN_PAD_CTL_HYS (1 << 8)
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/* Enable pull/keeper */
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#define MX25_PIN_PAD_CTL_PKE (1 << 7)
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/* 0 - keeper / 1 - pull */
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#define MX25_PIN_PAD_CTL_PUE (1 << 6)
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/* pull up/down strength */
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#define MX25_PIN_PAD_CTL_100K_PD (0 << 4)
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#define MX25_PIN_PAD_CTL_47K_PU (1 << 4)
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#define MX25_PIN_PAD_CTL_100K_PU (2 << 4)
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#define MX25_PIN_PAD_CTL_22K_PU (3 << 4)
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/* open drain control */
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#define MX25_PIN_PAD_CTL_OD (1 << 3)
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/* drive strength */
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#define MX25_PIN_PAD_CTL_DS_NOM (0 << 1)
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#define MX25_PIN_PAD_CTL_DS_HIGH (1 << 1)
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#define MX25_PIN_PAD_CTL_DS_MAX (2 << 1)
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#define MX25_PIN_PAD_CTL_DS_MAX11 (3 << 1)
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/* slew rate */
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#define MX25_PIN_PAD_CTL_SRE_SLOW (0 << 0)
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#define MX25_PIN_PAD_CTL_SRE_FAST (1 << 0)
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struct iomuxc_pad_ctl {
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u32 pad_a13;
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u32 pad_a14;
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u32 pad_a15;
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u32 pad_a17;
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u32 pad_a18;
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u32 pad_a19;
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u32 pad_a20;
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u32 pad_a21;
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u32 pad_a23;
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u32 pad_a24;
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u32 pad_a25;
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u32 pad_eb0;
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u32 pad_eb1;
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u32 pad_oe;
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u32 pad_cs4;
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u32 pad_cs5;
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u32 pad_nf_ce0;
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u32 pad_ecb;
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u32 pad_lba;
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u32 pad_rw;
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u32 pad_nfrb;
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u32 pad_d15;
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u32 pad_d14;
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u32 pad_d13;
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u32 pad_d12;
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u32 pad_d11;
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u32 pad_d10;
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u32 pad_d9;
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u32 pad_d8;
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u32 pad_d7;
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u32 pad_d6;
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u32 pad_d5;
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u32 pad_d4;
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u32 pad_d3;
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u32 pad_d2;
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u32 pad_d1;
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u32 pad_d0;
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u32 pad_ld0;
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u32 pad_ld1;
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u32 pad_ld2;
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u32 pad_ld3;
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u32 pad_ld4;
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u32 pad_ld5;
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u32 pad_ld6;
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u32 pad_ld7;
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u32 pad_ld8;
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u32 pad_ld9;
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u32 pad_ld10;
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u32 pad_ld11;
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u32 pad_ld12;
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u32 pad_ld13;
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u32 pad_ld14;
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u32 pad_ld15;
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u32 pad_hsync;
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u32 pad_vsync;
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u32 pad_lsclk;
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u32 pad_oe_acd;
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u32 pad_contrast;
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u32 pad_pwm;
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u32 pad_csi_d2;
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u32 pad_csi_d3;
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u32 pad_csi_d4;
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u32 pad_csi_d5;
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u32 pad_csi_d6;
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u32 pad_csi_d7;
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u32 pad_csi_d8;
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u32 pad_csi_d9;
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u32 pad_csi_mclk;
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u32 pad_csi_vsync;
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u32 pad_csi_hsync;
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u32 pad_csi_pixclk;
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u32 pad_i2c1_clk;
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u32 pad_i2c1_dat;
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u32 pad_cspi1_mosi;
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u32 pad_cspi1_miso;
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u32 pad_cspi1_ss0;
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u32 pad_cspi1_ss1;
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u32 pad_cspi1_sclk;
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u32 pad_cspi1_rdy;
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u32 pad_uart1_rxd;
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u32 pad_uart1_txd;
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u32 pad_uart1_rts;
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u32 pad_uart1_cts;
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u32 pad_uart2_rxd;
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u32 pad_uart2_txd;
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u32 pad_uart2_rts;
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u32 pad_uart2_cts;
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u32 pad_sd1_cmd;
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u32 pad_sd1_clk;
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u32 pad_sd1_data0;
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u32 pad_sd1_data1;
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u32 pad_sd1_data2;
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u32 pad_sd1_data3;
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u32 pad_kpp_row0;
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u32 pad_kpp_row1;
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u32 pad_kpp_row2;
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u32 pad_kpp_row3;
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u32 pad_kpp_col0;
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u32 pad_kpp_col1;
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u32 pad_kpp_col2;
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u32 pad_kpp_col3;
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u32 pad_fec_mdc;
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u32 pad_fec_mdio;
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u32 pad_fec_tdata0;
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u32 pad_fec_tdata1;
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u32 pad_fec_tx_en;
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u32 pad_fec_rdata0;
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u32 pad_fec_rdata1;
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u32 pad_fec_rx_dv;
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u32 pad_fec_tx_clk;
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u32 pad_rtck;
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u32 pad_tdo;
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u32 pad_de_b;
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u32 pad_gpio_a;
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u32 pad_gpio_b;
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u32 pad_gpio_c;
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u32 pad_gpio_d;
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u32 pad_gpio_e;
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u32 pad_gpio_f;
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u32 pad_vstby_req;
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||||
u32 pad_vstby_ack;
|
||||
u32 pad_power_fail;
|
||||
u32 pad_clko;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Pad group drive strength and voltage select
|
||||
* Same fields as iomuxc_pad_ctl plus ddr type
|
||||
*/
|
||||
/* Select DDR type */
|
||||
#define MX25_PIN_PAD_CTL_DDR_18 (0 << 11)
|
||||
#define MX25_PIN_PAD_CTL_DDR_33 (1 << 11)
|
||||
#define MX25_PIN_PAD_CTL_DDR_MAX (2 << 11)
|
||||
struct iomuxc_pad_grp_ctl {
|
||||
u32 grp_dvs_misc;
|
||||
u32 grp_dse_fec;
|
||||
u32 grp_dvs_jtag;
|
||||
u32 grp_dse_nfc;
|
||||
u32 grp_dse_csi;
|
||||
u32 grp_dse_weim;
|
||||
u32 grp_dse_ddr;
|
||||
u32 grp_dvs_crm;
|
||||
u32 grp_dse_kpp;
|
||||
u32 grp_dse_sdhc1;
|
||||
u32 grp_dse_lcd;
|
||||
u32 grp_dse_uart;
|
||||
u32 grp_dvs_nfc;
|
||||
u32 grp_dvs_csi;
|
||||
u32 grp_dse_cspi1;
|
||||
u32 grp_ddrtype;
|
||||
u32 grp_dvs_sdhc1;
|
||||
u32 grp_dvs_lcd;
|
||||
};
|
||||
|
||||
/*
|
||||
* Pad input select control
|
||||
* Select which pad to connect to an input port
|
||||
* where multiple pads can function as given input
|
||||
*/
|
||||
#define MX25_PAD_INPUT_SELECT_DAISY(in) ((in & 0x7) << 0)
|
||||
struct iomuxc_pad_input_select {
|
||||
u32 audmux_p4_input_da_amx;
|
||||
u32 audmux_p4_input_db_amx;
|
||||
u32 audmux_p4_input_rxclk_amx;
|
||||
u32 audmux_p4_input_rxfs_amx;
|
||||
u32 audmux_p4_input_txclk_amx;
|
||||
u32 audmux_p4_input_txfs_amx;
|
||||
u32 audmux_p7_input_da_amx;
|
||||
u32 audmux_p7_input_txfs_amx;
|
||||
u32 can1_ipp_ind_canrx;
|
||||
u32 can2_ipp_ind_canrx;
|
||||
u32 csi_ipp_csi_d_0;
|
||||
u32 csi_ipp_csi_d_1;
|
||||
u32 cspi1_ipp_ind_ss3_b;
|
||||
u32 cspi2_ipp_cspi_clk_in;
|
||||
u32 cspi2_ipp_ind_dataready_b;
|
||||
u32 cspi2_ipp_ind_miso;
|
||||
u32 cspi2_ipp_ind_mosi;
|
||||
u32 cspi2_ipp_ind_ss0_b;
|
||||
u32 cspi2_ipp_ind_ss1_b;
|
||||
u32 cspi3_ipp_cspi_clk_in;
|
||||
u32 cspi3_ipp_ind_dataready_b;
|
||||
u32 cspi3_ipp_ind_miso;
|
||||
u32 cspi3_ipp_ind_mosi;
|
||||
u32 cspi3_ipp_ind_ss0_b;
|
||||
u32 cspi3_ipp_ind_ss1_b;
|
||||
u32 cspi3_ipp_ind_ss2_b;
|
||||
u32 cspi3_ipp_ind_ss3_b;
|
||||
u32 esdhc1_ipp_dat4_in;
|
||||
u32 esdhc1_ipp_dat5_in;
|
||||
u32 esdhc1_ipp_dat6_in;
|
||||
u32 esdhc1_ipp_dat7_in;
|
||||
u32 esdhc2_ipp_card_clk_in;
|
||||
u32 esdhc2_ipp_cmd_in;
|
||||
u32 esdhc2_ipp_dat0_in;
|
||||
u32 esdhc2_ipp_dat1_in;
|
||||
u32 esdhc2_ipp_dat2_in;
|
||||
u32 esdhc2_ipp_dat3_in;
|
||||
u32 esdhc2_ipp_dat4_in;
|
||||
u32 esdhc2_ipp_dat5_in;
|
||||
u32 esdhc2_ipp_dat6_in;
|
||||
u32 esdhc2_ipp_dat7_in;
|
||||
u32 fec_fec_col;
|
||||
u32 fec_fec_crs;
|
||||
u32 fec_fec_rdata_2;
|
||||
u32 fec_fec_rdata_3;
|
||||
u32 fec_fec_rx_clk;
|
||||
u32 fec_fec_rx_er;
|
||||
u32 i2c2_ipp_scl_in;
|
||||
u32 i2c2_ipp_sda_in;
|
||||
u32 i2c3_ipp_scl_in;
|
||||
u32 i2c3_ipp_sda_in;
|
||||
u32 kpp_ipp_ind_col_4;
|
||||
u32 kpp_ipp_ind_col_5;
|
||||
u32 kpp_ipp_ind_col_6;
|
||||
u32 kpp_ipp_ind_col_7;
|
||||
u32 kpp_ipp_ind_row_4;
|
||||
u32 kpp_ipp_ind_row_5;
|
||||
u32 kpp_ipp_ind_row_6;
|
||||
u32 kpp_ipp_ind_row_7;
|
||||
u32 sim1_pin_sim_rcvd1_in;
|
||||
u32 sim1_pin_sim_simpd1;
|
||||
u32 sim1_sim_rcvd1_io;
|
||||
u32 sim2_pin_sim_rcvd1_in;
|
||||
u32 sim2_pin_sim_simpd1;
|
||||
u32 sim2_sim_rcvd1_io;
|
||||
u32 uart3_ipp_uart_rts_b;
|
||||
u32 uart3_ipp_uart_rxd_mux;
|
||||
u32 uart4_ipp_uart_rts_b;
|
||||
u32 uart4_ipp_uart_rxd_mux;
|
||||
u32 uart5_ipp_uart_rts_b;
|
||||
u32 uart5_ipp_uart_rxd_mux;
|
||||
u32 usb_top_ipp_ind_otg_usb_oc;
|
||||
u32 usb_top_ipp_ind_uh2_usb_oc;
|
||||
};
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
|
||||
void mx25_uart1_init_pins(void);
|
||||
#if defined CONFIG_FEC_MXC
|
||||
extern void mx25_fec_init_pins(void);
|
||||
#endif
|
||||
|
||||
#endif
|
Loading…
Add table
Reference in a new issue