Commit graph

15642 commits

Author SHA1 Message Date
Vignesh R
91dba55ca6 soc: keystone: Merge into ti specific directory
Merge drivers/soc/keystone/ into drivers/soc/ti/
and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11 20:07:12 -04:00
Grygorii Strashko
fd6b40b1ba firmware: ti_sci: Add support for NAVSS resource management
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.

This patch adds support for requesting and configuring such resources
from TI-SCI firmware.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11 20:07:12 -04:00
Tom Rini
f95fdf237d Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various rmobile fixes
2019-04-11 14:29:22 -04:00
Lukasz Majewski
9eba5e4160 DTS: imx53: Add imx53-kp-u-boot.dtsi file with u-boot specific property
This file adds the "u-boot,i2c-transaction-bytes" to mc34708 PMIC.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-11 15:21:33 +02:00
Andre Przywara
067e0b9684 sunxi: Allow booting from 128KB SD/eMMC offset
On modern Allwinner SoCs (tested: H2+, A64, H5, H6) the BootROM can
actually load the SPL also from sector 256 (128KB) of an SD card or eMMC
chip. For more details, see [1].
In this case the boot source indicator (written at offset 0x28 of SRAM A1)
has bit 4 set, so it's 0x10 for SD card and 0x12 for eMMC.

Add those new values to the existing boot source check to allow booting
the SPL from those "high" disk offsets as well. For this to work, the
value of CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to be adjusted,
for instance to 0x140 (right after the high SPL). Doing this dynamically
sounds desirable, but looks nasty to implement.

[1] https://groups.google.com/forum/#!topic/linux-sunxi/MaiijyaAFjk

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
9d0f9e8374 arm: sunxi: Enable DRAM ODT by default on H3/H5
Most of the boards we support with H3/H5 enable DRAM on-die termination,
which is consistent with the high DRAM clocks that are used.

Make it the default (like it's done for other similar platforms) instead
of defining it in each defconfig.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
882b71e47d arm: sunxi: Set the default DRAM ZQ value to 3881979 on H3/H5
Most H3/H5 boards we support have the DRAM ZQ value set to 3881979,
which is also consistent with the default set for the R40.

Make this value the default on H3/H5 instead of 123.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
9c2b0ddc41 arm: sunxi: Allow per-platform DRAM ZQ configuration on sun8i
A few sun8i platforms define specific default DRAM ZQ values, but they
are not taken in account because of MACH_SUN8I being used for the 123
default first.

Replace MACH_SUN8I with the list of platforms that don't have specific
DRAM ZQ values, to avoid overwriting the default for those that do.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Michael Trimarchi
ddd6930215 sunxi: dram_sun8i: Fix A33 memory initialization
While the exact problem is not known, based on discussion between
Philipp Tomsich and André Przywara it is guessed that exit self-refresh
timing is not set with correct value. There may be implicit enter or
exit Self-Refresh anywhere as part of some training phase.

In ZynqMP register guide [1], which is close to the various
Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL
tXS is bits [6:0]: Self refresh exit delay. So it could be safely
increased and it only affects the time after the self-refresh “exit”,
which happens only after (re-)initialisation.

There was no document for cpu in question so based on oscilloscope
readings [2][3] and observed result by comparing allwinner architecture.
So set it same as  Allwinner H5 silicon.

Before this patch, failure rate of was 7%.

This was tested on A33 allwinner cpu, dual rank connection connected
with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3
1.5V

And also this is tested in A33-OLinuXino dev board.

[1] https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html
[2] https://ibb.co/R70zmyS
[3] https://ibb.co/HVVCGQ8

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:32:59 +05:30
Jagan Teki
1692c73ccb sun50i: a64: Add Oceanic 5205 5inMFD initial support
Oceanic 5205 5inMFD is a 5 inch Multi function display baseboard
designed to mount SoPine SOM.

Key features:
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 2GB DDR3 RAM
- SD Slot
- SPI-NOR flash
- EMAC, RTL8211E
- MCP2515 CAN
- 4-lane, MIPI-DSI panel
- Goodix 911 CTP
- USB Host
- 12V DC power supply

Linux commit details about the sun50i-a64-oceanic-5205-5inmfd.dts sync:
"arm64: allwinner: a64: Add Oceanic 5205 5inMFD initial support"
(sha1: 00f7980a3bd53d12abc34f68146a8eed0e894248)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-10 15:25:38 +05:30
Marek Vasut
81abfa68f1 ARM: dts: rmobile: Enable USB on E2 Alt
The E2 Alt board has two USB ports, add missing DT nodes to make the
USB available.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
317d13ac63 ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0
Synchronize R-Car Gen3 device trees with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
3abd800eb9 ARM: dts: rmobile: Synchronize Gen2 DTs with Linux 5.0
Synchronize R-Car Gen2 device trees with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
b414ab70cd ARM: dts: rmobile: Import R8A77965 M3NULCB DTs
Import R8A77965 M3N ULCB device trees from Linux 5.0 ,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
c6435c317a pinctrl: renesas: Add R8A77965 pin control tables
Add pin control tables for R8A77965 from Linux 5.0 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
933143997b clk: renesas: Add R8A77965 clock tables
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
ce417a2f23 ARM: rmobile: Add dedicated R8A77965 SoC support
Add dedicated entry for R8A77965 M3N SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
bdafee778d ARM: rmobile: Enable multi-DTB fit LZO compression
Enable LZO compression of the multi-DTB fitImages, since the U-Boot
with multiple DTs enabled is becoming quite large and the DTs can
be well compressed. The LZO compression saves almost 200 kiB on the
Salvator-X(S) and ULCB targets.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
4fa8375ffe ARM: renesas: Save boot parameters passed in by ATF
The ATF can pass additional information via the first four registers,
x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer
to a device tree with platform information. Save these registers for
future use.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:09 +02:00
Tom Rini
5a451f11c8 First set of u-boot-atmel features and fixes for 2019.07 cycle
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcrEcDAAoJEB6zHgIOrC/I1dgH/3mHQNW8bqiNCJYcoVQdheHb
 e06TqbWHNlOG/NilYybvdeF+LjeCqhX4PzyL/sdcyBf3D/tK4cVvHpZrQyjb2s6K
 5IZSKJ+cZznmq6Hv7b//d30Azhx8bi8luxs60kkj+PF0xI1EyU3JteUqAs4Ooxd7
 z+HdcRFuAaps6sy0+szB3fTw9HTGrhFvQuHasDGb2uahhpwGzu/P0RchIDksOdzH
 3L4EOvgq8MZCiZ3ZtFWMWzQoCjcKf5Fuux41qar8gG/LrkWRfKG+LfWfZtTiTsjf
 vC9bYWmdKtkSLFj1PWgLBfGxev5zwPUbqI2EP4OlagfNs3os5pVFCYV5NZ6ovdE=
 =kMXf
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2019.07-a' of git://git.denx.de/u-boot-atmel

First set of u-boot-atmel features and fixes for 2019.07 cycle
2019-04-09 12:10:40 -04:00
Stefan Roese
a71e2f933b arm: at91: Add gardena-gateway-at91sam support
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip
AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage.
This patch adds support for this board including SPL support. Therefore
the AT91Boostrap is not needed on this platform any more.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
d4c8873f93 arm: at91: at91sam9x5.dtsi: Add watchdog handle
This makes it possible to reference the watchdog DT node via "&watchdog"
from board dts files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
da8a771241 arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL lds
This patch adds _image_binary_end to the SPL linker script. This will be
used be the upcoming GARDENA AT91SAM based platform, which uses DT in
SPL and configures CONFIGURE_SPL_SEPARATE_BSS.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
256c2ff0cc arm: at91: Enable watchdog support
This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09 09:28:50 +03:00
Stefan Roese
ce4d04af99 arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabled
This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.

Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
e6a2769360 arm: at91: Makefile: Compile lowlevel_init only when really necessary
Make sure that lowlevel_init is not compiled when
CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Ilko Iliev
d9bd42900c board: pm9g45: Migrate to CONFIG_DM
Migrate the following options to CONFIG_DM:
  CONFIG_DM_GPIO
  CONFIG_DM_MMC
  CONFIG_DM_ETH
  CONFIG_DM_SERIAL
  CONFIG_DM_USB

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2019-04-09 09:28:50 +03:00
Alexander Dahl
7dee1848d7 ARM: at91: sama5d2: Wrap cpu detection to fix macb driver
When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?

That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:

	#ifndef cpu_is_sama5d2
	#define cpu_is_sama5d2() 0
	#endif

That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.

The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:

	=> dhcp
	ethernet@f8008000: PHY present at 1
	ethernet@f8008000: Starting autonegotiation...
	ethernet@f8008000: Autonegotiation complete
	ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff)
	BOOTP broadcast 1
	BOOTP broadcast 2
	BOOTP broadcast 3
	BOOTP broadcast 4
	BOOTP broadcast 5
	BOOTP broadcast 6
	BOOTP broadcast 7
	BOOTP broadcast 8
	BOOTP broadcast 9
	BOOTP broadcast 10
	BOOTP broadcast 11
	BOOTP broadcast 12
	BOOTP broadcast 13
	BOOTP broadcast 14
	BOOTP broadcast 15
	BOOTP broadcast 16
	BOOTP broadcast 17

	Retry time exceeded; starting again

Notice the wrong reported link speed, although both SoC and phy only
support 100 MBit/s!

The real issue on reliably detecting the features of that cadence
ethernet mac IP block, is probably more complicated, though.

Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-04-09 09:28:50 +03:00
Tom Rini
ffb269ab30 Merge git://git.denx.de/u-boot-riscv
- RISC-V arch support SMP.
- Support Andestech's PLIC and PLMT.
- qemu, fu54e, ae350 boards enable SMP by default.
- Fix CONFIG_DEFAULT_DEVICE_TREE failure.
2019-04-08 22:32:11 -04:00
Jagan Teki
85c3d46322 arm: sunxi: Enable DM_MMC on required SoCs
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.

Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]

So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.

Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.

[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html

Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-08 16:35:15 -04:00
Tom Rini
c48b07a9fd - i.MX8QXP-MEK ethernet fix
-----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCXKtM/A4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXIuwAJwPGkXMY2V1JWjtWrxV3Ctey8rkvACeML/qP1Ee
 m/WnldHMc++lLZRMVvw=
 =aYD0
 -----END PGP SIGNATURE-----

Merge tag 'fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-staging

- i.MX8QXP-MEK ethernet fix
2019-04-08 10:11:29 -04:00
Andrejs Cainikovs
e82fa10b3e dts: imx8qxp-mek: Add PHY post reset delay
PHY cannot be detected unless we wait about 150 ms.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-08 15:24:39 +02:00
Stefan Roese
ccd063e981 watchdog: Move watchdog_dev to data section (BSS may not be cleared)
This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2019-04-08 09:21:39 -04:00
Rick Chen
48b90d9db5 riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure
It occurs since commit 27cb7300ff
("Ensure device tree DTS is compiled").

More details can refer to
89c2b5c020
ARM: fix arch/arm/dts/Makefile

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:46:00 +08:00
Rick Chen
a1ce531ab2 riscv: dts: ae350 support SMP
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Rick Chen
dda00ae4ef riscv: ax25: Andes specific cache shall only support in M-mode
Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Rick Chen
8848474c5e riscv: ax25: Add platform-specific Kconfig options
Add ax25 RISC-V platform-specific Kconfig options,
to include CPU and timer drivers. Also disable
ATCPIT100 SoC timer and replace by PLMT.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Rick Chen
a1f24875c3 riscv: Add a SYSCON driver for Andestech's PLMT
The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Rick Chen
0d389468e2 riscv: Add a SYSCON driver for Andestech's PLIC
The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Lukas Auer
8ac39e2974 riscv: hang if relocation of secondary harts fails
Print an error message and hang if smp_call_function() returns an error,
indicating that relocation of the secondary harts has failed.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
e043240252 riscv: do not rely on hart ID passed by previous boot stage
RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task must be handled by the boot
ROM. Explicitly populate register a0 with the hart ID from the mhartid
CSR to avoid possible problems on RISC-V processors with a boot ROM that
does not handle this task.

Suggested-by: Rick Chen <rick@andestech.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
f28ad250e6 riscv: boot images passed to bootm on all harts
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
3dea63c844 riscv: add support for multi-hart systems
On RISC-V, all harts boot independently. To be able to run on a
multi-hart system, U-Boot must be extended with the functionality to
manage all harts in the system. All harts entering U-Boot are registered
in the available_harts mask stored in global data. A hart lottery system
as used in the Linux kernel selects the hart U-Boot runs on. All other
harts are halted. U-Boot can delegate functions to them using
smp_call_function().

Every hart has a valid pointer to the global data structure and a 8KiB
stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
1446b26f76 riscv: save hart ID in register tp instead of s0
The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
2503ccc55f riscv: delay initialization of caches and debug UART
Move the initialization of the caches and the debug UART until after
board_init_f_init_reserve. This is in preparation for SMP support, where
code prior to this point will be executed by all harts. This ensures
that initialization will only be performed once on the main hart running
U-Boot.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
f152febb2a riscv: implement IPI platform functions using SBI
The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
34a0626fc3 riscv: import the supervisor binary interface header file
Import the supervisor binary interface (SBI) header file from Linux
(arch/riscv/include/asm/sbi.h). The last change to it was in commit
6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-04-08 09:44:25 +08:00
Lukas Auer
fa33f08fd6 riscv: add infrastructure for calling functions on other harts
Harts on RISC-V boot independently, U-Boot is responsible for managing
them. Functions are called on other harts with smp_call_function(),
which sends inter-processor interrupts (IPIs) to all other available
harts. Available harts are those marked as available in the device tree
and present in the available_harts mask stored in global data. The
available_harts mask is used to register all harts that have entered
U-Boot. Functions are specified with their address and two function
arguments (argument 2 and 3). The first function argument is always the
hart ID of the hart calling the function. On the other harts, the IPI
interrupt handler handle_ipi() must be called on software interrupts to
handle the request and call the specified function.

Functions are stored in the ipi_data data structure. Every hart has its
own data structure in global data. While this is not required at the
moment (all harts are expected to boot Linux), this does allow future
expansion, where other harts may be used for monitoring or other tasks.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:25 +08:00
Tom Rini
0e62d5b2ab Fixes for 2019.04
- fix bashism for MX8
 	- fix ethernet for MX53
 	- fix docs for i.MX8
 -----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlynLM8PHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et38/QL/Rc3p1pF6Dr9zKzxA0rcMoBo9MzzTrUP6XrN
 8syDBJNo2u93Msv78xHTQMCcfxRR3bkTYiWPEzWphC4Qk2IZIe2sETxu2BqsmWRI
 qzK5+L7oU3qJYqY8mZTUKPhmNxDu7E6yGXI1cWboWSR+/DMTxrUHZU5gjQyaQ/WN
 Diko1+lyaygZyPv0FzBdx7Vv+agQusGXGu4XbRkOXhrE6ytMv2ZjCzUtMYRIUg8H
 057DtJfwgU+zfimUoeuiltAwywh9UGxmlR4kb6rF5VZWX0Xn/XoVbMR6qRQXaFIz
 PzlNu3FEpOmvBQ5W5xySHS0CzbeTisIopJehZbkCc+XaEr80GplN995rGWGIN5av
 nlYS7rWHyIcVxoQNT61JTfVC1blFu6+tiokINWFI8as0fMrEAU4okzT4oBaGxdun
 CVcZDo9ytxKWLqtpD0MIQW4r4kJ27yWe3s4ot+v/+jb+XwkatX2J6oaiKviFFhuc
 BwniIb9lsi3ESIOaQXjpJ+qAw9gWYA==
 =//jr
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20190405' of git://git.denx.de/u-boot-imx

Fixes for 2019.04

	- fix bashism for MX8
	- fix ethernet for MX53
	- fix docs for i.MX8
2019-04-05 09:09:56 -04:00
Lukasz Majewski
da60b4301c DTS: Fix ETH PHY reset on HSC|DDC boards (imx53)
After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b79106

The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-02 13:44:18 +02:00
Tom Rini
da06f9a185 Merge branch 'master' of git://git.denx.de/u-boot-sh
Minor fixes for the Alt board and PHY use on Gen2.
2019-04-01 23:30:00 -04:00
Marek Vasut
e3b086cf04 ARM: dts: rmobile: Activate I2C7 on Alt
Activate I2C7 on Alt to allow access to the PMIC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-30 08:28:25 +01:00
Philipp Tomsich
a2893baa47 Revert "rockchip: Drop call to rockchip_dnl_mode_check() for now"
Due to a final resolution not coming up in time for 2019.04 and
following the consensus on the discussion, we'll keep this around
for 2019.04 after all.

This reverts commit 0d968ceb1f.
2019-03-29 09:21:13 +01:00
Tom Rini
d32519ac8a Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various fixes for bugs found by u-boot test.py
2019-03-26 23:19:11 -04:00
Patrick Delaunay
abe66b1b5d Convert CONFIG_ENV_SPI_* to Kconfig
This converts the following to Kconfig:
  CONFIG_ENV_SPI_BUS
  CONFIG_ENV_SPI_CS
  CONFIG_ENV_SPI_MAX_HZ
  CONFIG_ENV_SPI_MODE

Most of time these value are not needed, CONFIG_SF_DEFAULT
with same value is used, so I introduced CONFIG_USE_ENV_SPI_*
to force the associated value for the environment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25 17:36:59 -04:00
Patrick Delaunay
ac31d0d873 exynos: replace CONFIG_ENV_SPI_BASE by CONFIG_SYS_SPI_BASE
Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE
(it is not the location for environment but the location for U-Boot)
and, as it is the only platform with use this define, remove
it from whitelist.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25 17:35:52 -04:00
Marek Vasut
c49d0ac38a ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulator
An ADATA 16GB Industrial MLC card has so much capacitance on the Vcc
pin that the usual toggling of regulator to power the card off and on
is insufficient. When the card is calibrated into UHS SDR104 mode, it
will remain in that mode across the power cycle and subsequent attempt
to communicate with the card will fail.

The test with this card is to insert it into an SDHI slot and perform
"mmc dev 0 ; mmc dev 0", where the second "mmc dev 0" will fail.

Fix this problem by increasing the off-on delay from 0 to 20 mS.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Masahiro Yamada
344db3f330 mips: add missing dtb-y to arch/mips/dts/Makefile
Since commit 27cb7300ff ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

I am going to revert that commit, so device tree must be explicitly
listed in Makefile.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-03-22 12:15:12 -04:00
Masahiro Yamada
680207a1c5 powerpc: fix arch/powerpc/dts/Makefile
Since commit 27cb7300ff ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

I am going to revert that commit, so wrong code must be fixed.

CONFIG_MCR3000 is not defined anywhere. CONFIG_TARGET_MCR3000 is the
correct one.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-03-22 12:15:10 -04:00
Masahiro Yamada
89c2b5c020 ARM: fix arch/arm/dts/Makefile
Since commit 27cb7300ff ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

As a result, a lot of wrong code have been merged unnoticed.

I am going to revert that commit, and lots of hidden issues have
come to light:

[1] Typos

  armada-3720-uDPU.dts, sun8i-a83t-tbs-a711.dts

  use the extension ".dts" instead of ".dtb"

[2] DTB is associated to undefined CONFIG option

  For example, mx6sllevk_defconfig defines CONFIG_MX6SLL, but
  associates its device tree to CONFIG_MX6SL, which is undefined.

[3] Lots of entries are missing

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
[trini: add imx6ul pico dtbs]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-03-22 12:15:09 -04:00
Alexander Graf
ef331e3685 armv8: Disable exception vectors in SPL by default
Commit 1416e2d225 ("armv8: make SPL exception vectors optional") had a
typo in it which effectively disabled exception handling in SPL code always.

Since nobody complained, I guess we may as well disable exception handling
in SPL always by default.

So fix the bug to make the config option effective, but disable exception
handling in SPL by default. This gets us to the same functionality as before
by default, but with much less code included in the binary.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-22 12:15:03 -04:00
Keerthy
6dad56d733 arm: lib: bootm: Push the Starting kernel print to the end
Push the Starting kernel print to the end just before the
dm_remove_devices call.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-22 08:35:50 -04:00
Tom Rini
a00d15757d Merge git://git.denx.de/u-boot-marvell
- Enable network interface on clearfog_gt_8k (Baruch)
- Fix dreamplug boot by adding an spi0 alias to the DT (Chris)
- Fix / enhance Marvell ddr3 setup / parameters (Chris)
- Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris)
- Enable SPL_FLASH_BAR on db-88f6820-amc (Chris)
- Use correct pcie controller name in Armada-38x dts files (Chris)
- Disable d-cache on Kirkwood platforms as currently needed (Chris)
- Add a more descriptive comment to pci_mvebu.c (Stefan)
- Update Marvell maintainers entry (Stefan)
2019-03-19 19:58:48 -04:00
Tom Rini
810ae23fbc Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2019-03-19 07:13:23 -04:00
Chris Packham
599f7aa541 ARM: kirkwood: disable dcache for Kirkwood boards
Prior to commit 93b283d49f ("ARM: CPU: arm926ejs: Consolidate cache
routines to common file") the kirkwood boards didn't have and dcache
support. The network and usb drivers rely on this. Set
CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.

Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Chris Packham
825dd50f59 ARM: mvebu: use correct name for pcie controller
When armada-385.dtsi was sync'd from Linux the name of the node
describing the pcie controller was changed from pcie-controller to pcie.
Some of the boards that include armada-385.dtsi were missed in the
update retaining the old name. This updates the affected boards.

Reported-by: Влад Мао <vlaomao@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Chris Packham
5860532264 ARM: kirkwood: add spi0 alias for dreamplug
The conversion to DM_SPI managed to break accessing the environment on
dreamplug. This is because the environment code relies on being to able
to select the SPI device based on the sequence number. Add an alias so
that the spi0 bus gets sequence number 0.

Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Ley Foon Tan
ff0005b56a ARM: dts: socfpga: Add missing altr,sysmgr-syscon for EMAC
Syscon register is required in dts to select correct
PHY interface.

Fix error below:

Net:   Failed to get syscon: -2

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-03-16 13:30:03 +01:00
Tom Rini
8303467e80 Merge git://git.denx.de/u-boot-fsl-qoriq
- DPAA2 fixes and DDR errata workaround for LS1021A
2019-03-15 11:58:17 -04:00
Alison Wang
158097052a armv7: ls102xa: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:01 +05:30
Tom Rini
9659eb46af Merge branch 'master' of git://git.denx.de/u-boot-samsung 2019-03-14 11:37:11 -04:00
Adam Ford
8d0370905c arm: dts: imx6qdl-u-boot: Enable spba-bus@2000000 simple bus
spba-bus has a few nodes under it including the UART1 and
some ESPI buses.  In order to use them in SPL, the
u-boot,dm-spl flag needs to be added to the spba-bus@2000000
container.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
75cd09cb18 imx8qxp: Fix the reported CPU frequency
Currently the CPU frequency is incorrectly reported:

CPU:   NXP i.MX8QXP RevB A35 at 147228 MHz

Fix this problem by using a direct call to the SCU firmware to
retrieve the Cortex A35 CPU frequency.

With this change applied the CPU frequency is displayed correctly:

CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz

Tested-by: Marcelo Macedo <marcelo.macedo@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
737d8bd820 pico-imx6ul: Convert to DM MMC
Select CONFIG_DM_MMC=y in order to support MMC driver model.

This allows the MMC board related code to be removed.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2019-03-13 09:14:35 +01:00
Fabio Estevam
e5c2244fc8 pico-imx6ul: Import dts files from kernel
Import the device tree files from kernel 5.0-rc6 in preparation
for driver model conversion.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2019-03-13 09:14:35 +01:00
Tom Rini
6a08213d52 Merge git://git.denx.de/u-boot-x86
- ACPI changes and fixes to Intel Tangier/Edison
- i8254 beeper fixes
2019-03-11 11:24:20 -04:00
Bin Meng
3592965aff x86: crownbay: Enable the beeper sound driver
Use the i8254 sound driver to support creating simple beeps.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
8edaf34cfe x86: coreboot: Add the missing pc speaker node in the device tree
This is currently missing and without it the i8254 beeper driver
won't work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
9b2c8c3066 x86: Add a dtsi file for the pc speaker
The pc speaker driven by the i8254 is generic enough to deserve
a single dtsi file to be included by boards that use it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
7d0a53a40c x86: Make sure i8254 is setup correctly before generating beeps
The i8254 timer control IO port (0x43) should be setup correctly
by using PIT counter 2 to generate beeps, however in U-Boot other
codes like TSC driver utilizes PIT for TSC frequency calibration
and configures the counter 2 to a different mode that does not
beep. Fix this by always ensuring the PIT counter 2 is correctly
initialized so that the i8254 beeper driver works as expected.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Krzysztof Kozlowski
be26c4af3a arm: dts: exynos: Adjust whitespace around status property
Just add spaces around '=' sign for clarity.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:36 +09:00
Krzysztof Kozlowski
ae781d56fe arm: dts: exynos: Add ramp delay property to LDO regulators to Odroid XU3 family
Add startup time to LDO regulators of S2MPS11 PMIC on Odroid XU3/XU4/HC1
family of boards to be sure the voltage is proper before relying on the
regulator.

The datasheet for all the S2MPS1x family is inconsistent here and does
not specify unambiguously the value of ramp delay for LDO.  It mentions
30 mV/us in one timing diagram but then omits it completely in LDO
regulator characteristics table (it is specified for bucks).

However the vendor kernels for Galaxy S5 and Odroid XU3 use values of 12
mV/us or 24 mV/us.

Without the ramp delay value the consumers do not wait for voltage
settle after changing it.  Although the proper value of ramp delay for
LDOs is unknown, it seems safer to use at least some value from
reference kernel than to leave it unset.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Krzysztof Kozlowski
b5d3faa9f9 arm: dts: exynos: Add supply for ADC block to Odroid XU3 family
The ADC block requires VDD supply to be on so provide one.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Tom Rini
19c8c9c103 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Arria10 DRAM fixes and Gen5 cache fixes
2019-03-10 10:16:07 -04:00
Andy Shevchenko
d9b59fc9ae x86: edison: Add the rest of UARTs present on board
Intel Edison has three UART ports, i.e.
 port 0 - Bluetooth
 port 1 - auxiliary, available for general purpose use
 port 2 - debugging, usually console output is here

Enable all of them for future use.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
ab83e5c1a2 x86: edison: Use proper number of serial interface
The console is actually serial #2. When we would like to enable other ports,
this would be not okay to mess up with the ordering.

Thus, fix the number of default console interface to be 2.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
edf18a83f8 x86: acpi: Not every platform has serial console a first device
We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.

For example, on properly described Intel Edison board the console UART
is a third one.

Use current serial device as described in global data.

Fixes: a61cbad78e ("dm: serial: Adjust serial_getinfo() to use proper API")
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
c652dd1557 x86: acpi: Add DMA descriptors for I2C1 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Note, I2C6, which is available to user, has no DMA request lines connected.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
1d2825aa30 x86: acpi: Add DMA descriptors for SPI5 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Marek Vasut
7544ad0303 ARM: socfpga: Disable D cache in SPL
The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09 17:59:13 +01:00
Dinh Nguyen
532a54e652 ARM: socfpga: fix data and tag latency values for pl310 cache controller
The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-03-09 17:59:13 +01:00
Eugeniu Rosca
3a4511ce4a ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3N
v2019.01 commit cbff9f80ce ("ARM: dts: rmobile: Sync Gen3 DTs with
Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi.

Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is
equivalent to partially reverting below v2019.01 commits:
 - f529bc551b ("ARM: dts: rmobile: Extract USB nodes on M3N")
 - 830b94f768 ("ARM: dts: rmobile: Extract SDHI nodes on M3N")

Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously:
 - not needed if no U-boot-specific changes are needed in those nodes.
 - potentially dangerous/error-prone, since the duplicated properties
   override the properties originally defined in <soc>.dtsi. One
   possible consequence is that <soc>.dtsi is getting an update from
   Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation,
   the obsolete property values from <soc>-u-boot.dtsi will take
   precedence masking some of the <soc>.dtsi updates, potentially
   leading to all kind of obscure issues.

Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user"
of r8a77965-u-boot.dtsi) before and after the patch (slightly
reformatted to avoid 'git am/apply' issues and to reduce the width).

What below output means is there is already a mismatch in some of
SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no
U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in
r8a77965-u-boot.dtsi.

$> dtdiff before-r8a77965-salvator-x-u-boot.dtb \
           after-r8a77965-salvator-x-u-boot.dtb
 --- /dev/fd/63  2019-03-09 12:57:40.877963983 +0100
 +++ /dev/fd/62  2019-03-09 12:57:40.877963983 +0100
 @@ -1471,7 +1471,7 @@
        bus-width = <0x4>;
        cd-gpios = <0x51 0xc 0x1>;
        clocks = <0x6 0x1 0x13a>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa5 0x4>;
        max-frequency = <0xc65d400>;
        pinctrl-0 = <0x4d>;
 @@ -1492,7 +1492,7 @@

      sd@ee120000 {
        clocks = <0x6 0x1 0x139>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa6 0x4>;
        max-frequency = <0xbebc200>;
        power-domains = <0x1 0x20>;
 @@ -1504,7 +1504,7 @@
      sd@ee140000 {
        bus-width = <0x8>;
        clocks = <0x6 0x1 0x138>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        fixed-emmc-driver-type = <0x1>;
        interrupts = <0x0 0xa7 0x4>;
        max-frequency = <0xbebc200>;
 @@ -1526,7 +1526,7 @@
        bus-width = <0x4>;
        cd-gpios = <0x5a 0xf 0x1>;
        clocks = <0x6 0x1 0x137>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa8 0x4>;
        max-frequency = <0xc65d400>;
        pinctrl-0 = <0x56>;
 @@ -1868,14 +1868,14 @@

      usb-phy@ee0a0200 {
        #phy-cells = <0x0>;
 -      clocks = <0x6 0x1 0x2be>;
 +      clocks = <0x6 0x1 0x2bf>;
        compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy";
        phandle = <0x47>;
        pinctrl-0 = <0x4c>;
        pinctrl-names = "default";
        power-domains = <0x1 0x20>;
        reg = <0x0 0xee0a0200 0x0 0x700>;
 -      resets = <0x6 0x2be>;
 +      resets = <0x6 0x2bf>;
        status = "okay";
      };

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-03-09 17:57:04 +01:00
Marek Vasut
fc3ed156f9 ARM: dts: rmobile: Force 1-bit bus width on Gen2 QSPI
U-Boot currently uses Gen2 QSPI in 1-bit mode, enforce it until
we can do better using the new SPI NOR framework.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-09 17:57:04 +01:00
Tom Rini
85887300ae Merge git://git.denx.de/u-boot-fsl-qoriq
- Enable DHCP as boot-source in distro boot for NXP layerscape
  platforms
- fix register layout for SEC on Layerscape architectures
- fixes related to DPAA2 ethernet
2019-03-04 13:05:53 -05:00
Laurentiu Tudor
7122f79141 armv8: fsl-layerscape: avoid DT fixup warning
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:

WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.

Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:14 +05:30
Laurentiu Tudor
e82d9ee73a armv8: fsl-layerscape: fix SEC QI ICID setup
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:09 +05:30
Rajesh Bhagat
32413125b3 configs: fsl: move DDR specific defines to Kconfig
Moves below DDR specific defines to Kconfig:

CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESH

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 20:56:01 +05:30
Heinrich Schuchardt
70eb82539b powerpc: enabled building with CONFIG_DM=y
Moving to the driver model requires CONFIG_DM to be enabled. Currently
several boards like kmeter1_defconfig produce a build error when CONFIG_DM
is enabled:

In file included from include/common.h:35,
                 from ./arch/powerpc/include/asm/fsl_lbc.h:10,
                 from include/mpc83xx.h:10,
                 from ./arch/powerpc/include/asm/ppc.h:27,
                 from ./arch/powerpc/include/asm/u-boot.h:18,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/dm/device.h:13,
                 from include/linux/mtd/mtd.h:26,
                 from drivers/mtd/mtdconcat.c:25:
include/image.h: In function ‘image_check_target_arch’:
include/image.h:846:3: error: #error "please define IH_ARCH_DEFAULT in
                       your arch asm/u-boot.h"
 # error "please define IH_ARCH_DEFAULT in your arch asm/u-boot.h"
   ^~~~~
include/image.h:848:31: error: ‘IH_ARCH_DEFAULT’ undeclared (first use in
                        this function); did you mean ‘IH_ARCH_COUNT’?
  return image_check_arch(hdr, IH_ARCH_DEFAULT);

The error can be avoided by moving the definition of IH_ARCH_DEFAULT before

     #include <asm/ppc.h>

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-02 18:11:20 +05:30
Tom Rini
cfba74d0be Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- SoCFPGA cache/gpio fixes
2019-02-28 18:57:32 -05:00
Tom Rini
35b05146f6 Merge branch 'master' of git://git.denx.de/u-boot-sh
- Gen2/Gen3 fixes for warnings and sdhi
2019-02-28 18:57:17 -05:00
Tom Rini
da206916a1 Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Various Bananapi fixes
2019-02-28 14:22:50 -05:00
Marek Vasut
86dc480d73 ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a ("armv7: add PL310 support to u-boot")
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2019-02-28 14:21:46 -05:00
Anup Patel
98a66ffa3a riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd
This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V
because bootm will update initrd location in DTB only if
CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable
this option then bootm assumes DTB already has initrd details
which is not the case most of the time.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27 09:12:34 +08:00
Anup Patel
3fda0262c3 riscv: Add SiFive FU540 board support
This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Anup Patel
b630d57d0a clk: Add fixed-factor clock driver
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 09:12:33 +08:00
Anup Patel
26f4fd1cb4 riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB ethernet stops working
for U-Boot because it is a 32bit DMA capable device.

To handle 32bit DMA capable devices on 64bit systems, we provide
custom implementation of board_get_usable_ram_top() which ensures
that usable ram top is not more then 4GB. This in-turn ensures
that U-Boot always runs within 4GB hence DMA addresses generated
by DMA mapping APIs will be within 4GB too.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Anup Patel
1fa625b8e4 riscv: Add place-holder asm/arch/clk.h for driver compilation
Some of the drivers (such as Cadence MACB ethernet driver) expect
asm/arch/clk.h to be provided by arch support so we add place-holder
asm/arch-generic/clk.h for RISC-V generic CPU.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27 09:12:33 +08:00
Anup Patel
70b8562dcf riscv: Add asm/dma-mapping.h for DMA mappings
This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27 09:12:33 +08:00
Anup Patel
fdff1f96a6 riscv: Rename cpu/qemu to cpu/generic
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Anup Patel
7c8d210b91 riscv: Enable create symlink using kconfig
We select CREATE_ARCH_SYMLINK for RISC-V so that we can have
include/asm/arch linked to include/asm/arch-xyz.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Marek Vasut
30b62ca086 ARM: rmobile: Imply SoC per board
Imply all SoCs supported by a given board. This allows building single
U-Boot binary for boards which can have multiple SoCs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
669367f6a4 ARM: rmobile: Imply pinctrl drivers per SoC
Imply preferred pin control driver per SoC, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
46467ceaf4 ARM: rmobile: Imply clock drivers per SoC
Imply preferred clock driver per SoC, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
4a9743f73c ARM: socfpga: Clear PL310 early in SPL
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller. This can in turn cause e.g. SPL to fail reading data
from SD/MMC.

The obvious solution here would be to fully reset the L2 cache controller
via the reset manager MPUMODRST L2 bit, however this causes bus hang even
if executed entirely from L1 I-cache to avoid generating any bus traffic
through the L2 cache controller.

This patch thus configures and enables the L2 cache controller very early
in the SPL boot process, clears the L2 cache and disables the L2 cache
controller again.

The reason for doing it in SPL is because we need to avoid accessing any
of the potentially stale data in the L2 cache, and we are certain any of
the stale data will be below the OCRAM address range. To further reduce
bus traffic during the L2 cache invalidation, we enable L1 I-cache and
run the invalidation code entirely out of the L1 I-cache.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25 16:07:36 +01:00
Marek Vasut
2c0b300bc3 ARM: socfpga: Configure PL310 latencies
Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25 16:07:36 +01:00
Marek Vasut
b275c9aba6 ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a ("armv7: add PL310 support to u-boot")
2019-02-25 16:07:36 +01:00
Tom Rini
888f9aa5ca Merge branch 'master' of git://git.denx.de/u-boot-tegra 2019-02-20 12:28:57 -05:00
Tom Rini
0c41e59a37 Merge git://git.denx.de/u-boot-x86
- Add support for sound.

Albeit the big changeset, changes are pretty limited to x86 only and a
few new sound drivers used by x86 so I think it would be good to have
this in the next release.
2019-02-20 12:28:40 -05:00
Tom Rini
176b32cd4f Merge git://git.denx.de/u-boot-fsl-qoriq
- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs
2019-02-20 12:26:05 -05:00
Tristan Bastian
8105816cbb ARM: tegra: enable ums on nyan boards
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for
other tegra devices: commit e6607cffef.
But the nyan devices never received that functionality.

Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:44 -07:00
Tristan Bastian
74a7d9af3f nyan-big: change spi delay
Internal keyboard of nyan-big is only working when cold booting by pressing [reload/refresh]+[power] button.
With this patch keyboard is working by only pressing [power] button.

Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:44 -07:00
Simon Glass
e2c901c99e x86: Add sound support for samus
Enable sound on samus using the broadwell I2S and an RT5677 audio codec.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-20 15:27:11 +08:00
Simon Glass
3f3411ebf8 x86: broadwell: Add support for serial I/O devices
Add support for initing the I2C device and ADSP on broadwell. These are
needed for sound to work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
c692f82240 x86: broadwell: Don't bother probing the PCH for pinctrl
At present the pinctrl probes the PCH but since it only uses it to obtain
a PCI address, this is no necessary. Avoiding this fixes one of the two
co-dependent loops in broadwell.

This driver really should be a proper pinctrl driver, but for now it
remains a syscon device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
23e8bd7e49 x86: broadwell: Add support for the ADSP
The Application Digital Signal Processor is used for sound processing with
broadwell. Add a driver to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
79a5be820d sound: x86: Add beeping support in i8254
Adjust the code to allow beeping at different frequencies, using a
calculated value for timer 2.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
6744c0d652 sound: x86: link: Add sound support
Add sound support for link, using the HDA codec implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
ecc7973d1c sandbox: sound: Silence sound for testing
When testing the sound system we don't need the hear the beeps. The
testing works by checking the data that would be emitted. Add a
device-tree property to silence the sound, and enable it for testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
2850266965 sound: Add uclass operations for beeping
Some audio codecs such as Intel HDA do not need to use digital data to
play sounds, but instead have a way to emit beeps. Add this interface as
an option. If the beep interface is not supported, then the sound uclass
falls back to the I2S interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:08 +08:00
Simon Glass
67b0cda76a x86: ivybridge: Add a way to get the HDA config setting
Add a way check to whether HD audio is enabled. Use ioctl() to avoid
adding too many unusual operations to PCH.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:08 +08:00
Simon Glass
b45c833c71 sandbox: pch: Add a test for the PCH uclass
This uclass currently has no tests. Add a sandbox driver and some simple
tests to provide basic coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Use "sandbox,pch" for the compatible string, for consistency]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:26:36 +08:00
Simon Glass
c882163b09 x86: sandbox: pch: Add a CONFIG option for PCH
At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:25:30 +08:00
Simon Glass
3a44bfdf08 x86: Adjust I/O macros to work on 64-bit machines
At present these macros give warnings on 64-bit machines and do not
correctly do 32-bit accesses. Update them to use linux types.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:25:29 +08:00
Simon Glass
c6d84a30fe sandbox: Add a note about the growing state_info struct
This struct is getting larger and in some cases is being used for things
which would be better put into a driver. For example hwspinlock is not
used outside of sandbox_hwspinlock.c.

Add a note to encourage people to put things elsewhere.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:25:29 +08:00
Derald D. Woods
36a75344d7 ARM: omap3: evm: Update DM SPL support
- Switch to using the omap3-u-boot.dtsi file for needed properties
- Enable SPL_OF_CONTROL

This commit is based on the following series:

https://patchwork.ozlabs.org/project/uboot/list/?series=92472
https://patchwork.ozlabs.org/project/uboot/list/?series=92462

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-19 16:58:24 -05:00
Tom Rini
e0cc7df9fd omap3_beagle: Update for DM SPL support
- Switch to using the omap3-u-boot.dtsi file for needed properties.
- Remove a few SPL features to free up more SRAM space.
- Switch CONFIG_SYS_TEXT_BASE to the normal default, we don't need to
  worry about X-Loader at this point anymore.
- A few related updates to SPL options as part of switching to DM SPL.

Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19 16:58:23 -05:00
Adam Ford
0cd9465c0b ARM: omap3_logic: Enable SPL booting device tree
With the generic omap3-u-boot.dtsi file available, this patch
increased the memory of the various incarnations of the omap3_logic
board, and points their respective u-boot.dtsi files to the newly
created generic one, and removes the PLATDATA from the board file.

These are all done at once because the're all utilizing the same
omap3logic.c board file.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-19 16:58:23 -05:00
Adam Ford
ed59a76db0 ARM: DTS: omap3-u-boot.dtsi
Create generic omap3-u-boot.dtsi file that omap3 based boards
can include to generate device tree in SPL for booting MLO.

Credit should go to Tom Rini.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19 16:58:23 -05:00
Hannes Schmelzer
eaba7df704 board/BuR/brxre1: convert do DM
This commit converts the brxre1 board to DM,
for this we have todo following things:

- add a devicetree-file for this board
- drop all obsolete settings from board header-file
- use dm_i2c_xxx calls for read/write to the resetcontroller
- request gpios before operate them

Serues-cc: trini@konsulko.com
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-19 08:55:43 -05:00
Peng Ma
f11e492aea armv8: ls1043a: move SCSI_AHCI and SCSI to arm/Kconfig
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface
support.
this changed is to fixed the ls1043ardb compile warning as fallows:

===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the
v2019.07 release. Failure to update by the deadline may
result in board removal.See doc/driver-model/MIGRATION.txt
for more info.
====================================================

Signed-off-by: Peng Ma <peng.ma@nxp.com>
[PK: reword the patch subject]
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Rajesh Bhagat
5c08d96f3a armv8: layerscape: move CONFIG_LAYERSCAPE to Kconfig
Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Rajesh Bhagat
bbf5b25282 armv8: layerscape: move TZASC and TZPC configs to Kconfig
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig
for LS1088A and LS2088A platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Pankaj Bansal
1eba723c72 lx2160aqds : Add support for LX2160AQDS platform
LX2160AQDS is a development board that supports LX2160A
family SoCs. This patch add base support for this board.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[PK: Sqaush patch for "secure boot defconfig" & add maintainer]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Meenakshi Aggarwal
e088e587ed armv8: emc2305: add support for fan controller
Add support for fan controller emc2305.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Priyanka Jain
58c3e62040 armv8: lx2160ardb : Add support for LX2160ARDB platform
LX2160ARDB is an evaluation board that supports LX2160A
family SoCs. This patch add base support for this board.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han
and re-arrange defconfig]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Pankaj Bansal
2e53759dc6 armv8: fsl-layerscape: reorder rgmii dpmacs' enablement
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.

Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
or not? if it is (fsl_serdes_init has already enabled the dpmac), then
don't enable it.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Priyanka Jain
8c4875395b armv8, lx2160a: Initialize ethernet array in serdes_init
Add code to initial ethernet interface arrays
with corresponding dpmac-id values in serdes_init function
for LX2160A.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Meenakshi Aggarwal
b3b7706b2f arch: arm: lib: Flush L3 after relocation to DDR
Flush L3 cache after uboot relocated to DDR.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Priyanka Jain
fc615be4a6 armv8: lx2160a: Update CONFIG_SYS_FSL_PEBUF_BASE
As per hardware documentation,
CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Simon Goldschmidt
473f55676a arm: socfpga: gen5: remove hacked ETH RST handling
The 'dwmac_socfpga' ETH driver can now get the MACs out of reset
via the socfpga reset driver and can set PHY mode via syscon.

This means we can now remove the ad-hoc code to do this from
arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-18 13:00:53 +01:00
Chen-Yu Tsai
da95ed58c4 sunxi: Add Bananapi M2+ H5 board
As the H5 is pin compatible with the H3, vendors tend to upgrade their
existing H3 products with an H5 SoC swap. This is the case with the
Bananapi M2+ H5.

Add the following to support it:

  - device tree file: synced from Linux v5.0-rc1,
  - defconfig: copy of bananapi_m2_plus_h3_defconfig with only SoC
	       family and default device tree file name changed
  - MAINTAINERS entry

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-18 14:46:53 +05:30
Chen-Yu Tsai
7761eb5bea sunxi: Sync Bananapi M2+ device tree from Linux v5.0-rc1
As of commit aa8fee415f46 ("ARM: dts: sun8i: h3: Split out
non-SoC-specific parts of Bananapi M2 Plus") in the Linux kernel, the
device tree for the Bananapi M2+ has been split into a common dtsi file,
and an SoC-specific board device tree file that includes both the shared
dtsi file and the soc dtsi file. This was done to support both the H3
and H5 variants of the same board. This is similar to what was done for
the Libre Computer ALL-H3-CC in U-boot commit d7b17f1c24 ("sunxi: Split
out common board design for ALL-H3-CC device tree").

The newly split files are directly synced from Linux tag v5.0-rc1.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-18 13:54:23 +05:30
Tom Rini
b89074f650 u-boot-imx-2019-02-16
---------------------
 
 - vhybrid: add calibration
 - gw_ventana: fixes
 - Improve documentation for Secure Boot (HABv4)
 - Fix Marvell Switch
 - MX6 Sabre, switch to DM
 - Fixes for NAND
 -----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlxn6N8PHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et3SiEL/iU7JK7wYL1f2KN9k5ejWuYBsbh8rzvlnjVL
 8gdry7NsTCMFATk/MKBRkKxlguumE2PCjijEqsbpQArxVVsR9cmuw7d4RagXJqcZ
 T0Wl8RCgNWDgwm717/boX5jlTWd8HA5DETQP5atJhkd5aiM95kM3lNP1K8AJ2mmP
 GMEUEPeEh3Kht9tU4OibHkNApZD8wTWSS9FndSocEi9tEPrEbvhFW8Q5sZv+aRsO
 d7GQVSsesmC7dV2b0t0GpQKEDlkco787A+F9ScL5Twb8+eAhDzhJxYFBs1vP8Gu2
 miVcGpfO3ZBwpgk/RjI6rGPOzFuaiW8LRttWBgjYcDXykCPmsk+5nojdN197qzkj
 KvfcgVlFAWZ1mVsHiYlbaKwlUllVtM1RxJewFNkteMe4C8yWH9307IUApZCwnwTV
 xZPmhSdoAWbBfe3kTmYpJkrRYcdgpJ1gx9JSyfGi8lg+nlaX6rFVqM0Y8qsk8teo
 a7yShI2cFG1Hv2LJ2eAVrjqMtjP9ZA==
 =TWGQ
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-2019-02-16' of git://git.denx.de/u-boot-imx

u-boot-imx-2019-02-16
---------------------

- vhybrid: add calibration
- gw_ventana: fixes
- Improve documentation for Secure Boot (HABv4)
- Fix Marvell Switch
- MX6 Sabre, switch to DM
- Fixes for NAND
2019-02-16 08:31:05 -05:00
Max Krummenacher
6ed4d26c21 imx: cpu.c: give access to reset cause in spl
This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR
register content intact so that U-Boot proper can evaluated the
reset_cause again should this be needed.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15 22:01:15 +01:00
Marcel Ziswiler
63c918d188 ARM: dts: i.MX6Q, i.MX6QDL: fix address/size-cells warnings
This fixes the following warnings:

arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /clocks: unnecessary #address-cells/#size-cells without "ranges" or
 child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/aips-bus@02100000/mipi@021e0000: unnecessary #address-cells/
 #size-cells without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu@02400000/port@2: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu@02400000/port@3: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu@02800000/port@2: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property
arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 /soc/ipu@02800000/port@3: unnecessary #address-cells/#size-cells
 without "ranges" or child "reg" property

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
67f165ddfd arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]
Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones
from kernel v4.20 (commit 8fe28cb58bcb2).

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
e72e3549a8 arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] files
This allows us to keep the basic dts[i] files up-to-date with
the ones in kernel, but at the same time allowing the u-boot
to add its own properties to the existing nodes.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
79536013a3 usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGE
Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL,
makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE.
Everything that is not part of the usb storage support in SPL is now
build under SPL_USB_HOST_SUPPORT.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Venkatesh Yadav Abbarapu
053d4bd472 arm64: zynqmp: Change the spi-rx-bus-width property to x1
As per the zc1275 design x1 mode is enabled so changing the
spi-rx-bus-width property to x1.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Shubhrajyoti Datta
ccc8a11935 arm64: zynqmp: Fix i2c boot warning
Fix the below warning as the core looks for the compatible
string.

[    5.198919] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@19
[    5.207454] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@19
[    5.216394] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@30
[    5.224986] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@30
[    5.233927] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@35
[    5.242527] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@35
[    5.263880] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@36
[    5.272477] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@36
[    5.281415] i2c i2c-18: of_i2c: modalias failure on
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@51
[    5.290008] i2c i2c-18: Failed to create I2C device for
/amba/i2c@ff030000/i2c-mux@75/i2c@3/dev@51

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Michal Simek
1317a5e5ea arm64: zynqmp: Remove autodetected devices without description
It will never reach mainline that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Amit Kucheria
9a06ed88f4 arm64: dts: Fix various entry-method properties to reflect documentation
The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be
set to "psci".

Linux commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states
bindings examples") attempted to fix this earlier but clearly more is
needed.

Linux docs:
Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Michal Simek
91af22bc6b xilinx: dts: Remove additional empty lines
Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Mounika Grace Akula
3c8ee337eb arm64: zynqmp: Add reset-on-timeout for all boards and modify default timeout value
This patch adds reset-on-timeout to FPD WDT which will trigger an
interrupt to PMU when watchdog expiry happens and PMU takes the
necessary action. If this property is not enabled, reason will not be
known when watchdog expiry happens.
This patch also modifies the default timeout to 60 seconds. Reason is
that if u-boot enables WDT, it will set the timeout to 10 seconds and
this is not enough to boot till Linux and start the WDT application in
Linux. 60 seconds is the maximum safest value to boot till Linux and
start the WDT application.

Users need to change this timeout value to fit their needs.

Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Luis Araneda
9896dc6558 ARM: dts: zynq: correct and improve the model property of dt files
Replace the current value of the model property by a more accurate
description of each board (which includes the manufacturer), as some
of the boards had the same value ("Xilinx Zynq")

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Luis Araneda
cd6160b9c1 ARM: dts: zynq: Set correct manufacturer for ZedBoard and MicroZed boards
Both boards are made by Avnet, Inc. So add an additional
value to the compatible property

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Michal Simek
7b85f7901d ARM: dts: Use mmc@ instead sdhci@
mmc name is recommended based on devicetree specification.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Marcin Niestroj
c4f225d19f ARM: dts: imx6ul-lite*: add DTS files for liteSOM and liteboard
Import liteSOM and liteboard dts files from Linux v4.20. They will
be used after transition to driver model and device-tree based boot.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-02-15 12:45:15 +01:00
Lukasz Majewski
dc619924c7 ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code
This patch extends the vf610 DDR memory controller code to support SW
leveling.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-02-15 12:16:50 +01:00
Lukasz Majewski
548cc1095f ddr: vybrid: Provide code to perform on-boot calibration
This patch provides the code to calibrate the DDR's
DQS to DQ signals (RDLVL).

It is based on:
VFxxx Controller Reference Manual, Rev. 0, 10/2016, page 1600
10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"

and NXP's community thread:
"Vybrid: About DDR leveling feature on DDRMC."
https://community.nxp.com/thread/395323

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 12:16:50 +01:00
Lukasz Majewski
c5b22a5360 ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)
This commit provides extra defines needed for DDR memory controller
calibration (read leveling performing).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-02-15 12:16:50 +01:00
Michal Simek
35e2b92344 arm64: zynqmp: Fix logic around CONFIG_ZYNQ_SDHCI
Replace SDHCI controller listing by Kconfig symbol to let SPL know that
this board is using multiple SDHCIs controllers.
Kconfig help message should explain why this is needed.
Origin symbols were used in full u-boot but with moving to distro boot
this was fixed already.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Michal Simek
6a9a7b81c6 arm64: zynqmp: Remove addresses for i2c controllers
All platforms have been converted to DM that's why there is no reason to
keep addresses in headers. They are all read from DT now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
8bdad43333 arm64: zynqmp: Switch all platforms to DM_I2C
CONFIG_PCA953X is not needed because of PCA953X is integrated in gpio
subsystem already. That's why also remove CMD_PCA953X which is only for
this driver.

zcu102/zcu104-revC/zcu106/zcu111 contain links to eeprom which stores MAC address.

DM_I2C is not enabled for the whole SoC because it increase size for
mini configurations and there is no I2C symbol present to setup
dependencies.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
e0bc7574fa ARM: zynq: Remove addresses for i2c controllers
All platforms have been converted to DM that's why there is no reason to
keep addresses in headers. They are all read from DT now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
aeac8921ab ARM: zynq: Convert Syzygy to DM_I2C
Boards have only one controller enabled that's why move to DM_I2C is
easy.
Add also i2c alias for not to be shown as i2c bus -1 because alias
doesn't exist.
Config file points to MAC stored in eeprom but it is not listed that's
why I have added 24c08 part.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Siva Durga Prasad Paladugu
eebbfd865b arm64: versal: Add mini configuration for Versal
This patch adds new mini target for versal.
This configuration is very minimal in size which runs
from OCM. It contains support for mtest which can be
used for running DDR memory tests.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Michal Simek
47a766f950 arm64: versal: Move IOU_SWITCH_DIVISOR0 to Kconfig
Move hardcoded IOU_SWITCH_DIVISOR0 to Kconfig to be able to set it up
for different platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:10 +01:00
Siva Durga Prasad Paladugu
0fbd2a8225 arm64: versal: Add mini eMMC configuration
This patch adds mini eMMC configuration which has only
emmc0 and emmc1 functionalities and can run from small
amount of memory. This is required for memory constraint
devices.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Siva Durga Prasad Paladugu
4244f2b7e8 arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMU
This patch adds new config option which is used for
reserving a specific memory for MMU Table and in this
case we are using TCM for that purpose.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Alexander Graf
2f8ab1218f arm: Leave smccc calls in .text when efi_loader=n
Commit 81ea00838c ("efi_loader: PSCI reset and shutdown") put the SMCCC
assembly code into the efi specific code section. This is wrong when we
do not have EFI_LOADER enabled, as that strips efi runtime sections from
the output binary

Reported-by: Michal Simek <monstr@monstr.eu>
Reported-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tested-by: Michal Simek <monstr@monstr.eu>
Fixes: 81ea00838c ("efi_loader: PSCI reset and shutdown")
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
6b59607f10 x86: do not use i386 code for x86_64 memory functions
arch/x86/lib/string.c contains assembler implementations of memcpy(),
memmove(), and memset() written for i386. Don't use it on x86_64.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
f6c6df7ebc efi_loader: refactor switch to non-secure mode
Refactor the switch from supervisor to hypervisor to a new function called
at the beginning of do_bootefi().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
e4fd695645 efi_selftest: allow building on ARMv7-M
ARMv7-M only supports the Thumb instruction set. Our current crt0 code does
not support it. With the patch we can build all unit tests of the EFI
subsystem that do not require crt0.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:05 +01:00
Andy Shevchenko
24b56e2bf3 x86: tangier: Add initial ACPI support for PMIC device
Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS
and access is going via SCU device, enumerated via PCI.

For now, we add just a minimum support of PMIC device to allow enabling,
e.g. USB OTG, in the OS.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-12 14:37:17 +08:00
Bin Meng
bc1a8f0d7a x86: Use the existing GDT in the ROM for 64-bit U-Boot proper
It is unnecessary to use a RAM version GDT for 64-bit U-Boot proper.
In fact we can just use the ROM version directly, which not only
eliminates the risk of being overwritten by application, but also
removes the complexity of patching the cpu_call64().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12 14:37:17 +08:00
Bin Meng
9168326037 x86: Don't copy the cpu_call64() function to a hardcoded address
Before jumping to 64-bit U-Boot proper, SPL copies the cpu_call64()
function to a hardcoded address 0x3000000. This can have potential
conflicts with application usage. Switch the destination address
to be allocated from the heap to avoid such risk.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12 14:37:16 +08:00
Bin Meng
dbb0696ba0 x86: Change 4-level page table base address to low memory
At present the 4-level page table base address for 64-bit U-Boot
proper is assigned an address that conflicts with CONFIG_LOADADDR.
Change it to an address within the low memory range instead.

Fixes crashes seen when 'dhcp' on QEMU x86_64 with
"-net nic -net user,tftp=.,bootfile=u-boot".

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12 14:37:16 +08:00
Baruch Siach
d7f165cf67 arm: mvebu: cf gt-8k: dts: add PCIe slot reset support
Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices
on Clearfog GT-8K.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Baruch Siach
f301ba55c8 arm: mvebu: mcbin: dts: fix PCIe reset polarity
The PCIe slot PERST signal is active low. Fix the gpio signal
description in the dts.

This happened to work because the pcie_dw_mvebu driver sets the reset
gpio level to 1 (high) to release the reset. The following commit will
fix that.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Tom Rini
151b8339cc Samsung sound patches (applied for Samsung maintainer)
Common sound support
 buildman environment support
 of-platdata documentation improvements
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlxf7igRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIreYKfggApQiL0Gv6NdGAQN+zfpjKY5a2QyjKsAxa
 KLm3q8XyXIQXufMWOEPoW1iWm0iixpIFgChy8ff3m/OPDzsx99UXDTyvjitsSxtQ
 5tFu8K78nUZT6OOE3HNhhlyW/xK442oKBzGt4MUt3kUZOELsCNuftgbJUWksHuO3
 6pPrgt36E0uRGbUA4ioYCU336viJRPOOCdqb8hHViEihFj/IEv5T82RdE5y97YxG
 dT7BZxjPkBH5ZN1uD/tdxG1k6IZBagZiYoDAsYp4YqNwmVsm5sLrZ9QVSf7EcH/y
 qX8butZesiMd7xm7RROlrIImh7fb36N3zsoRiUWZDo1Al3IRkmZyVA==
 =tdut
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dm

Samsung sound patches (applied for Samsung maintainer)
Common sound support
buildman environment support
of-platdata documentation improvements
2019-02-10 08:11:32 -05:00
Simon Glass
e898799ce4 samsung: mmc: Drop old MMC init code
Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remove those boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09 12:50:22 -07:00
Simon Glass
f656daea64 spring: Update flashmap details
Update the flashmap so that this board can be started over USB A-A. It
is slightly different from snow.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-09 12:50:22 -07:00
Simon Glass
8d135f5c6f spring: Update sound to use max98088 codec
Update the spring settings to use this codec, which is what it actually
shipped with.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-09 12:50:22 -07:00
Simon Glass
e2932310a5 exynos: Convert to use CONFIG_BLK
Move all exynos boards over to use CONFIG_BLK.

This converts s5p_goni also, but adding dummy functions for pinmux and
peripheral ID. This will not function correctly, but gives the maintainer
more time to convert the board if desired.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09 12:50:21 -07:00
Andreas Dannenberg
4a1fa524e9 arm: mach-k3: common: Clean up ATF image startup function
Perform some cosmetic cleanup of the ATF image startup function, namely
fixing a spelling mistake, capitalization of a few words, spacing, as
well aligning how errors are printed and as using panic() for cases that
were using a combination of printf() + hang().

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 07:51:02 -05:00
Philippe Reynes
2f4a686f21 dt: bcm63158: add watchdog
This commit add watchdog and sysreset watchdog
in the bcm63158 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:51:00 -05:00
Philippe Reynes
be2fc084d9 bcm963158: add initial support
This add the initial support of the broadcom reference
board bcm963158 with a bcm63158 SoC.

This board has 1 GB of ram, 512 MB of flash (nand),
2 usb port, 1 uart, 4 ethernet ports (LAN), 1 ethernet port (WAN).

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:59 -05:00
Philippe Reynes
ea1a7de532 bcm63158: add initial support
This add the initial support of the broadcom bcm63158 SoC family,
only the cpu, dram and uart are supported.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:59 -05:00
Patrick Delaunay
e74b74c528 dts: stm32mp1: clock tree update
- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
  - PLL3P set to 208.8MHz for MCU sub-system
  - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
  - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
  - PLL4P set to 99MHz for SDMMC and SPDIFRX
  - PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00