Commit graph

5194 commits

Author SHA1 Message Date
Fabio Estevam
f8fdb81f6c compat: Remove is_power_of_2() definition
Use the is_power_of_2() definition from log2.h to align with the
kernel implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 16:46:59 -05:00
Fabio Estevam
56adb7b308 ARM: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:51:59 -05:00
Tom Rini
60b25259a5 Merge git://git.denx.de/u-boot-samsung 2015-11-05 07:46:45 -05:00
Tom Rini
28824407f3 Merge git://git.denx.de/u-boot-socfpga 2015-11-05 07:46:28 -05:00
Chin Liang See
a55f28624e arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash
With a working QSPI calibration, the SCLK can now run up to 100MHz

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 02:34:15 +01:00
Michal Simek
1e370ef7e7 ARM: zynq: Remove zc70x target
Remove zc70x target which was one setting for zc702 and zc706.
Currently zc702 and zc706 are separated.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-04 14:49:53 +01:00
Simon Glass
42800ffa79 arm: zynq: Move serial driver to driver model
Update this driver to use driver model and change all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Michal Simek
c2490bf546 ARM: zynqmp: Enable DM and OF binding
SPI requires DM and OF that's why enable DM for ZynqMP
and start to use configuration based on embedded OF.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-04 14:49:53 +01:00
Simon Glass
035c6b271d arm: zynq: dts: Add U-Boot device tree additions
We need to mark some device tree nodes so that they are available before
relocation. This enables driver model to find these automatically. In the
case of SPL it ensures that these nodes will be retained in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Simon Glass
71556fbcbf dm: arm: zynq: Enable device tree control in SPL
Move to using device tree control in SPL so that we can use the same driver
code in both SPL and U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Simon Glass
c54c0a4c1c arm: zynq: Support the debug UART
Add support for the debug UART to assist with early debugging. Enable it
for Zybo as an example.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:52 +01:00
Simon Glass
bd44758a41 arm: zynq: Drop unnecessary code in SPL board_init_f()
Move to the new way of starting up SPL. Clearing of BSS and calling
board_init_r() is now handled by crt0.S.

Also tidy up the header include order.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:52 +01:00
Michal Simek
44303dfa79 ARM: zynqmp: Add DTS for ep108 board
Add DTS for ep108 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
2015-11-04 14:49:51 +01:00
Dinh Nguyen
c624d07f3f arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-11-03 17:32:16 +01:00
Wenyou Yang
a3b59b1523 mmc: atmel: Add atmel sdhci support
The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia
Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC)
Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO
V3.0 specification. It is compliant with the SD Host Controller Standard
V3.0 specification.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-03 14:21:31 +01:00
Wenyou Yang
c19000556e arm: at91: clock: Add the generated clock support
Some peripherals may need a second clock source that may be different
from the system clock. This second clock is the generated clock (GCK)
and is managed by the PMC via PMC_PCR.

For simplicity, the clock source of the GCK is fixed to PLLA_CLK.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-03 14:21:31 +01:00
Wenyou Yang
ce39680f7e arm: at91: Change the Chip ID registers' addresses
Provide the specific addresses for the Chip ID and Chip ID Extension
registers, instead of the offset, which make it use on other chips.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-03 14:21:30 +01:00
Minkyu Kang
55a70c51ac arm: exynos: clean up checkpatch issues
This patch will fix these checkpatch issues.

ERROR: Macros with complex values should be enclosed in parentheses
+#define DEFAULT_DQS_X4		(DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)

		ERROR: space prohibited before that ',' (ctx:WxW)
+	writel(val , &drex0->concontrol);
 	           ^

ERROR: space prohibited before that ',' (ctx:WxW)
+	writel(val , &drex1->concontrol);
    	           ^

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:22 +09:00
Przemyslaw Marczak
5d0434315c Exynos4412: pinmux: disable pull for MMC pins
There are 8 pins for SD card in Exynos, but the MUX was configured
only for 7, since the one was used for card detection.
This caused the pin's pull wrong configuration.

This commit fixes this and the card detect can work properly,
after call this function.

Tested-on: Odroid U3 and Odroid X2.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:10 +09:00
Przemyslaw Marczak
9090d1dd0e Odroid-XU3: dts: enable ADC, with request for pre-reloc bind
This ADC is required for Odroid's board revision detection.
The pre-reloc request is enabled, since board detection will
be done in one of early function call.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
54b51e6b12 Exynos54xx: dts: add ADC node
This commit adds common ADC node, which is disabled as default.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
4d577e0810 Odroid-XU3: enable s2mps11 PMIC support
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
3b3ad9015e dm: adc: add Exynos54xx compatible ADC driver
This commit adds driver for Exynos54xx ADC subsystem.

The driver is implemented using driver model, amd provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()

The basic parameters of ADC conversion, are:
- sample rate: 600KSPS
- output the data as average of 8 time conversion

ADC features:
- sample rate: 600KSPS
- resolution: 12-bit
- channels: 10 (analog multiplexer)

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
d64c8adedc Exynos5422/5800: set cpu id to 0x5422
The proper CPU ID for those Exynos variants is 0x5422,
but before the 0x5800 was set. This commit fix this back.

Changes:
- set cpu id to 0x5422 instead of 0x5800
- remove macro proid_is_exynos5800()
- add macro proid_is_exynos5422()
- change the calls to proid_is_exynos5800() with new macro

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:37:59 +09:00
Przemyslaw Marczak
3b72b60099 Peach-Pi: dts: add cpu-model string
This platform is based on Exynos5800 but the cpu id is 0x5422.
This doesn't fit the common Exynos SoC name convention, so now,
the CPU name is defined by device tree string, to be printed
properly.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:37:59 +09:00
Przemyslaw Marczak
fdbb740d7c s5p: cpu_info: print "cpu-model" if exists in dts
The CPU name for Exynos was concatenated with cpu id,
but for new Exynos platforms, like Chromebook Peach Pi
based on Exynos5800, the name of SoC variant does not
include the real SoC cpu id (0x5422).

For such case, the CPU name should be defined in device tree.

This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:37:59 +09:00
Josh Wu
478ec83489 at91: simplify spl board_init_f function
crt0.S do both memset the bss section and call board_init_r for us, so
remove them from board_init_f().

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-01 22:02:14 +01:00
Tom Rini
588eec2a86 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-10-30 12:56:58 -04:00
Adrian Alonso
ee3899aa6c imx: hab: add mx7 secure boot support
Add mx7 secure boot support, add helper macro IS_HAB_ENABLED_BIT
to get the corresponding bit mask per SoC (mx7 or mx6) to identify
if securue boot feature is enabled/disabled.

On authenticate_image only check for mmu enabled on mx6 SoC to
force pu_irom_mmu_enabled so ROM code can perform mmu cache flush
mx7 SoC ROM code does not have this issue as ROM enables cache support
based on fuse settings.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:22:37 +01:00
Adrian Alonso
fba6f9efa4 imx: hab: use read_fuse for secure boot settings
Use read_fuse api fuction call to read secure boot fuse
settings (enabled/disabled).

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:22:37 +01:00
Adrian Alonso
bb955146f0 arm: imx: add secure boot fuse details for imx7 SoC
Add secure boot fuse details (location) bank = 1, word = 3;
for imx7 SoC platforms.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:22:36 +01:00
Adrian Alonso
6b50bfe56d arm: imx: add secure boot fuse details for imx6 SoC
Add secure boot fuse details (location) bank = 0, word = 6;
for imx6 SoC platforms.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:22:36 +01:00
Adrian Alonso
f68c61a3da imx: hab: add secure boot fuse details
Add secure boot fuse helper struct to abstract the way
to find out secure boot settings per SoC iMX family

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:22:36 +01:00
Adrian Alonso
6d846c726b imx: hab: rework unified rom section for mx7
Rework unified section macro select via Kconfig option
instead of macro definition in mx7_common header file.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:22:36 +01:00
Adrian Alonso
a89729c9ca imx: hab: use unified rom section for mx6sx and mx6ul
Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target
platforms to resolve corresponding HAB_RVT_BASE base address,
the RVT table contains pointers to the HAB API functions in
ROM code.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:20:57 +01:00
Adrian Alonso
7a7281a91c imx: hab: rework secure boot support for imx6
Rework secure boot support for imx6, move existing hab support
for imx6 into imx-common for SoC reuse.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:20:57 +01:00
Adrian Alonso
fc5ad4778d imx: cpu: move common chip revision id's
Move common chip revision id's to main cpu header file
mx25 generic include cpu header for chip revision

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:20:56 +01:00
Heiko Schocher
d62f2f8cdf arm, imx: add some gpr register defines
add some missing gpr register defines.

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-10-30 15:08:39 +01:00
Peng Fan
2bb014820c imx-common: timer: clean up code
We can reuse common functions in lib/time.c, but not reimplement
functions in imx-common/time.c.
Only keep timer_init ,get_tbclk and implement timer_read_counter in
imx-common/time.c.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-30 14:59:43 +01:00
tang yuantian
4632ad773e arm: ls1021a: Add sata support on qds and twr board
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:02 -07:00
Hou Zhiqiang
831c068fcf armv8/ls1043a: Enable secondary cores
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:02 -07:00
Yangbo Lu
8ef0d5c438 armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
This patch adds esdhc support for ls1043ardb.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Shaohui Xie
e82973414d armv8/ls1043a: Add Fman support
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Gong Qianyu
3ad4472923 armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Mingkai Hu
f3a8e2b7d4 armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
2015-10-29 10:34:01 -07:00
Mingkai Hu
8281c58fd4 armv8/fsl_lsch2: Add fsl_lsch2 SoC
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Mingkai Hu
9f3183d2d6 armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Mingkai Hu
435acd83b2 armv7/ls1021a: move ns_access to common file
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:58 -07:00
horia.geanta@freescale.com
5757e06c69 arm: ls102xa: enable snooping for CAAM transactions
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]

Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:58 -07:00
Aneesh Bansal
f4f0b7403a Data types defined for 64 bit physical address
Data types and I/O functions have been defined for
64 bit physical addresses in arm.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:57 -07:00
Alison Wang
0cbba8e953 ls102xa: fdt: Disable IFC in SD boot for QSPI
As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled
in SD boot for QSPI. This patch will add fdt support for
this rule.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:56 -07:00
Alison Wang
6a00a9cb15 armv8/fsl-lsch3: fdt: Check the pointer returned from call to a function may be NULL
Pointer 'reg' returned from call to function 'fdt_getprop' may be
NULL, will be passed to function and may be dereferenced there by
passing argument 1 to function 'of_read_number'. So check pointer
'reg' first.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 09:09:55 -07:00
Jagan Teki
976dfb0fd8 dts: zed: Enable zynq qspi controller node
Enabled zynq qspi controller node for zed board.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
7b0d345981 dts: zc770-xm010: Enable zynq qspi controller node
Enabled zynq qspi controller node for zc770-xm010 board.

=> sf probe 0 -- bus1 for selecting qspi controller
=> sf probe 1 -- bus0 for selecting spi controller

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
e94c71c075 dts: zc706: Enable zynq qspi controller node
Enabled zynq qspi controller node for zc706 board.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
e9cf6ec516 dts: zc702: Enable zynq qspi controller node
Enabled zynq qspi controller node for zc702 board.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25 20:17:01 +05:30
Jagan Teki
659cc15630 dts: microzed: Enable zynq qspi controller node
Enabled zynq qspi controller node for microzed board,
verified the same on spansion spi-nor flash.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:01 +05:30
Jagan Teki
70676cb3b5 dts: zynq: Add zynq qspi controller nodes
This patch adds zynq qspi controller nodes in zynq-7000.dtsi.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:01 +05:30
Masahiro Yamada
09f3ca3dd5 arm, powerpc: select SYS_GENERIC_BOARD
We have finished Generic Board conversion for ARM and PowerPC, i.e.
all the boards have been converted except OpenRISC, SuperH, SPARC,
which have not supported Generic Board framework yet.

Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro
defines in include/configs/*.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-10-24 13:50:38 -04:00
Simon Glass
5fa030b9f0 zynq: Move SPL console init out of board_init_f()
We should not init the console this early since it precludes using driver
model for the UART, since it is not set up at the start of board_init_f().
See the README for more information. The debug UART does not have this
restriction. If we want to do early init with the console on it can be done
in spl_board_init().

Move the preloader_console_init() call from board_init_f() to board_init_r().

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
2015-10-24 13:50:37 -04:00
Simon Glass
5ba534d247 arm: Switch 32-bit ARM to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24 13:50:36 -04:00
Simon Glass
931bec31b4 arm: Switch aarch64 to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Tested on LS2085ARDB and LS2085AQDS (armv8 SoC).
Tested-by: York Sun <yorksun@freescale.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24 13:50:36 -04:00
Mugunthan V N
eae7ae1853 am437x: Add am57xx_evm_defconfig using CONFIG_DM
Import various DT files for am57xx-beagle-x15 from
Linux Kernel v4.2
Add config file for this board, enable DM, DM_GPIO,
DM_SERIAL and DM_MMC.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-10-22 14:44:02 -04:00
Mugunthan V N
7a837bcf12 am437x: Add am437x_sk_evm_defconfig using CONFIG_DM
Import various DT files for am437x-sk-evm from Linux Kernel v4.2
Add config file for this board, enable DM, DM_GPIO, DM_SERIAL
and DM_MMC.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:44:01 -04:00
Mugunthan V N
48038c4acb am437x: Add am437x_gp_evm_defconfig using CONFIG_DM
Import various DT files for am4372, an43xx pinctrl and
am437x-gp-evm from Linux Kernel v4.2
Add config file for this board, enable DM, DM_GPIO, DM_SERIAL
and DM_MMC.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:44:00 -04:00
Mugunthan V N
11e1582506 omap_hsmmc: update struct hsmmc to accomodate base address from DT
Existing driver gets the actual omap hammc base address + 0x100
bytes as the first 0x100 bytes is not used by the driver. But
with DM conversion the base address from DT is different, to
accommodate the offset adding res0[0x100] to struct hsmmc.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:22:28 -04:00
Mugunthan V N
e5520e188b dra7xx: Add dra74_evm_defconfig using CONFIG_DM
Import various DT files for dra7-evm from Linux Kernel v4.2
Add config file for this board, enable DM and DM_GPIO

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:22:28 -04:00
Lokesh Vutla
2a9a842ebe ARM: dts: k2g: Add DT support
Add basic DT support for k2g evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:26 -04:00
Roger Quadros
3b68939fa0 ARM: k2g: add SD card and eMMC support
Add MMC support for k2g

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-10-22 14:22:25 -04:00
Vitaly Andrianov
4657a2d44e driver: net: keystone_net: add support for rgmii phy
In K2G, Ethernet doesn't support SGMII instead it support RGMII,
adding support to the driver to connect to RGMII phy.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:23 -04:00
Mugunthan V N
bf7bd4e725 driver: net: keystone_net: fix phy mode configuration
Phy mode is a board property and it can be different between
multiple board and ports, so it should not be hardcoded in
driver to one specific mode. So adding a field in eth_priv_t
structure to pass phy mode to driver.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:22 -04:00
Vitaly Andrianov
cddb330035 ARM: k2g: update keystone nav rx queue numbers
update K2G nav rx queue number

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:21 -04:00
Vitaly Andrianov
11d8222a26 ARM: k2g: Correct base addresses
Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO,
and MSMC segments.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:20 -04:00
Vitaly Andrianov
5dd6af2ecb ARM: k2g: Add support for pin mux configuration
Add api for configuring pin mux.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:19 -04:00
Vitaly Andrianov
235dd6e8d1 ARM: k2g: Add ddr3 info
Add ddr3 related info

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:18 -04:00
Vitaly Andrianov
0fba27b690 ARM: k2g: Add PSC info
Add psc information for k2g

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:17 -04:00
Vitaly Andrianov
e6d71e1ca5 ARM: k2g: Add clock information
Add clock information for Galileo

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-10-22 14:22:16 -04:00
Vitaly Andrianov
bda920c65e ARM: k2g: Add pll data
Add pll data for k2g

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:15 -04:00
Lokesh Vutla
f9c4a51c3e ARM: k2g: Add kconfig support
Add Kconfig support

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:13 -04:00
Lokesh Vutla
f11a328b54 ARM: k2g: Add support for CPU detection
Adding CPU detection support for Keystone2 Galileo.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:12 -04:00
Lokesh Vutla
1985abe207 ARM: keystone2: Use dtb images by default
Now that OF_CONTROL is enabled on all keystone2 platforms,
build the default images with DT.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:11 -04:00
Lokesh Vutla
16d7f5b51a ARM: dts: k2e: Enable OF_CONTROL and DM
Import k2e specific DT files from Linux Kernel and enable
OF_CONTROL, DM, DM_SERIAL.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:11 -04:00
Lokesh Vutla
cec6a6bf1d ARM: dts: k2l: Enable OF_CONTROL and DM
Import k2l specific DT files from Linux Kernel and enable
OF_CONTROL, DM, DM_SERIAL.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:21:39 -04:00
Lokesh Vutla
391839fb04 ARM: dts: k2hk: Enable OF_CONTROL and DM
Import k2hk specific DT files from Linux Kernel and enable
OF_CONTROL, DM, DM_SERIAL.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:20:35 -04:00
Lokesh Vutla
8a9bb065da ARM: dts: keystone2: Do not use LPAE addresses in U-Boot
Keystone dts files assumes that LPAE is enabled and top level root
node uses 64bit addresses. This breaks the keystone boot with
CONFIG_OF_CONTROL enabled. So do not use 64 bit addresse in U-Boot DT.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:19:51 -04:00
Lokesh Vutla
351f969088 ARM: dts: Keystone2: Import generic dt files from Linux Kernel
Import various generic dts files from Linux kernel so that
all keystone2 platforms can be DT in U-boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:19:50 -04:00
Lokesh Vutla
8c80b1937b ARM: keystone2: Fix serial port init
With CONFIG_DM_SERIAL is enabled NS16550_init() cannot be
called directly. Driver probe should be taking care of this.
So call this function only when DM_SERIAL is not enabled.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:19:49 -04:00
Paul Kocialkowski
2da87ab353 omap-common: Common get_board_serial function to pass serial through ATAG
Since there is a common function to grab the serial number from the die id bits,
it makes sense have one to parse that serial number and feed it to the serial
ATAG.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:18:31 -04:00
Paul Kocialkowski
679f82c349 omap-common: Common function to display die id, replacing omap3-specific version
This introduces omap_die_id_display to display the full die id.
There is no need to store it in an environment variable, that no boot script
is using anyway.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:18:30 -04:00
Paul Kocialkowski
07815eb9f3 omap-common: Common serial and usbethaddr functions based on die id
Now that we have a common prototype to grab the omap die id, functions to figure
out a serial number and usb ethernet address can use it directly.
Those also get an omap_die_id prefix for better consistency.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:22 -04:00
Paul Kocialkowski
9fd5401659 omap5: omap_die_id support
This introduces omap5 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:21 -04:00
Paul Kocialkowski
987a40d52e omap4: omap_die_id support
This introduces omap4 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:20 -04:00
Paul Kocialkowski
b50a768528 omap3: omap_die_id support
This replaces the previous get_dieid definition with omap_die_id, that matches
the common omap_die_id definition.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:18 -04:00
Paul Kocialkowski
72931b15e7 omap-common: Common omap_die_id definition
This introduces a common definition for omap_die_id, that aims at providing a
common interface for accessing omap platform's die id bits.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:17 -04:00
Tom Rini
e8d124fae0 Merge git://git.denx.de/u-boot-marvell 2015-10-20 21:59:40 -04:00
Stefan Roese
1d51ea1913 arm: mvebu: Enable DM_SERIAL on AXP / A38x boards
This patch enables DM_SERIAL for all ARCH_MVEBU boards (AXP & A38x).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-21 02:25:01 +02:00
Stefan Roese
9cffb2335c arm: mvebu: Add DM (driver model) support
This patch adds driver model support for some Marvell MVEBU SoC's. Including
Armada XP and 38x. All 3 currently mainlined boards are converted. DM is now
selected automatically for MVEBU platforms.

With this DM support now available for MVEBU, hardcoding the base addresses
and other information is not necessary any more. Probing should be done
by using the values provided via the device tree now instead. For this
the driver also need to be converted to DM. Patches for some of the drivers
will follow.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-21 02:25:01 +02:00
Stefan Roese
39a230aad3 arm: mvebu: Add basic Armada XP / 38x dtsi/dts files
These will be needed by the upcoming DM (driver model) support for
the Armada XP / 38x SoC's. This will provide DT based probing.

The dts files are copied 1:1 from the Linux kernel release v4.2.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-21 02:25:01 +02:00
Stefan Roese
78de2c0c3e arm: mvebu: Do not call board_init_r() from board_init_f()
Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the MVEBU SPL with the correct SPL design as well as reduces
the stack utilisation slightly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-21 02:25:01 +02:00
Stefan Roese
42cc034f19 arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPL
When running on the AXP I sometimes noticed a strange behavior. As some
characters are not echoed on the U-Boot prompt. Not disabling the
lowlevel_init code, especially calling cpu_init_cp15() in the main
U-Boot seems to solve this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-10-21 02:25:00 +02:00
Stefan Roese
944c7a3176 arm: mvebu: Add option to use UART xmodem protocol via kwboot
This patch enables the use of the kwboot tool, to boot mainline U-Boot
on the Marvell Armada XP/38x SoC's. This is done by returning to the
SoC's BootROM after SPL has initialized the SDRAM. We need to make sure
to not reconfigure the internal register space and MBARs. Otherwise
the BootROM will not be able to continue after SPL jumps back to it.

To use this feature, please don't forget to change the BOOT_FROM line
in your board specfic kwbimage.cfg file this way:

    BOOT_FROM uart

Tested on these Marvell eval boards:
DB-MV784MP-GP - Armada XP
DB-88F6820-GP - Armada 38x

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-21 02:25:00 +02:00
Maxime Ripard
fd8133b725 sunxi: Add CHIP support
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.

The DT is identical to the DT submitted to the upstream kernel.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-10-20 22:48:29 +02:00
Maxime Ripard
862ba7ed32 axp209: Sync the DTSI with the kernel
Linux had a number of changes to the AXP209 DTSI. Sync ours.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-10-20 22:48:29 +02:00
Maxime Ripard
f0e8e8dacf sun5i: Sync the DTSI with the kernel
Add the latest kernel changes to the sun5i family DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-10-20 22:48:28 +02:00
Maxime Ripard
f7d6b3cc16 sunxi: board: Only try to use the MMC related functions if enabled
So far, even if CONFIG_MMC was not enabled the board code was trying to use
the MMC-related functions, resulting in linker errors.

Protect those calls by an ifdef.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-10-20 22:48:28 +02:00
Hans de Goede
fc01daee8b sunxi: Add defconfig for the Sinovoip BPI-M2 board
The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features
1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver,
stereo headphone jack and hdmi video output.

The dts changes are identical to the dts files submitted upstream.

A few notes on the use if dldo and aldo regulators. DLDO1 is used
for Vdd for the ethernet phy, ALDO2 is used for AVdd for the ethernet
phy. ALDO1 is used to power the sdio wifi module.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-10-20 18:40:28 +02:00
Hans de Goede
6944aff1ca sunxi: power: Unify axp pmic function names
Stop prefixing the axp functions for setting voltages, etc. with the
model number, there ever is only one pmic driver built into u-boot,
this allows simplifying the callers.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-10-20 18:40:27 +02:00
Hans de Goede
70ac9295e3 sunxi: Remove board defconfig-s for specific Q8 tablet PCB-s
We now have generic q8_a?3_defconfig files for Q8 formfactor tablets with
an A13 / A23 / A33 SoC, there is no need for these PCB variant specific
defconfig-s and they only serve to confuse the user.

Note that in case of the forfun_q88db_defconfig and TZX-Q8-713B7_defconfig
for A13 based Q8 tablets there is not even a dts file for these in the
upstream kernel, which is all the more reason to remove them.

The generic q8_a?3_defconfig files have been tested on an Et_q8_v1_6,
Ippo_q8h_v1_2_a33_1024x600, Ippo_q8h_v1_2 and TZX-Q8-713B7 tablet, and the
forfun_q88db_defconfig is identical to q8_a13_tablet_defconfig.

This leaves only the Ippo_q8h_v5 untested with the new generic defconfigs
but there is no reason to assume that it will not work.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-10-20 18:40:27 +02:00
Hans de Goede
6d0bdfdde5 sunxi: Switch to using malloc_simple for the spl
common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a
Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes,
and .data from 0x54c to 0x144 bytes.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-20 18:40:27 +02:00
Hans de Goede
ff42d107bf sunxi: Enable CONFIG_SPL_STACK_R
Select CONFIG_SPL_STACK_R for sunxi boards, this gives us much more
room on the stack once we've the DRAM running.

Besides being a good change to have on itself, this also paves the
way for switching to using malloc_simple in the SPL which cuts of
close to 4KiB of the SPL size.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-20 18:40:27 +02:00
Stefan Roese
c3d891405b arm: mvebu: Move Armada XP/38x Kconfig to mach specific Kconfig file
Introduce a mach-mvebu/Kconfig for all Armada based SoC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-10-20 07:12:44 +02:00
Tom Rini
7003e4cf76 Merge branch 'master' of git://git.denx.de/u-boot-arm 2015-10-19 11:30:38 -04:00
Lubomir Rintel
79ad5cef15 ARM: rpi: add another revision of Raspberry Pi A+
Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
2015-10-19 08:12:25 +02:00
Lokesh Vutla
8626cb8021 ARM: k2e/l: Apply WA for selecting PA clock source
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-17 20:16:13 -04:00
Tom Rini
ac6a53219a Merge git://git.denx.de/u-boot-socfpga 2015-10-16 20:21:04 -04:00
Dinh Nguyen
3790a8c662 arm: dts: socfpga: add "u-boot,dm-pre-reloc" to socfpga_cyclone5_socdk dts
We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-17 01:47:31 +02:00
Dinh Nguyen
8d8e13e129 arm: socfpga: enable data/inst prefetch and shared override in the L2
Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-17 01:47:31 +02:00
Alison Wang
53fd4b8c22 arm: mmu: Add missing volatile for reading SCTLR register
Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.

(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163)

Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU  and later causes a PCIE VA access
failure.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2015-10-16 07:55:51 +02:00
Tom Rini
1275456d31 Merge branch 'master' of git://git.denx.de/u-boot-arm 2015-10-15 17:45:39 -04:00
Fabio Estevam
aaf87f03ad pci: pcie_imx: Fix hang on mx6qp
PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-10-15 09:05:13 -04:00
Thierry Reding
b1964c72bd armv8/gic: Fix GIC v2 initialization
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-15 14:47:03 +02:00
Thierry Reding
ad3d6e88a1 armv8/mmu: Set bits marked RES1 in TCR
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.

For EL1, only bit 23 is not reserved, so only write bit 31 as 1.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-15 14:46:43 +02:00
Thierry Reding
55aa0bed98 armv8/mmu: Clean up TCR programming
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-15 14:41:20 +02:00
Albert ARIBAUD
13a3972585 Merge remote-tracking branch 'u-boot/master' 2015-10-14 10:46:36 +02:00
Fabio Estevam
f861f51c46 ls102xa: Fix reset hang
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.

Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.

This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.

In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.

This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.

Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-12 12:56:32 -04:00
Vladimir Zapolskiy
4c90234586 lpc32xx: fix calculation of HCLK PLL output clock
Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-10-11 17:12:13 -04:00
Vladimir Zapolskiy
f0aa26f006 lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN config
According to ARM PrimeCell PL175 documentation WAIT_OEN config value
is defined without any additional clocks added to the value set by a
client, the change fixes the wrong interface to WAIT_OEN config.

The change also touches a single user of LPC32xx EMC and corrects
configured "output enable delay" value on its side according to the
changed interface.

No functional change intended.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-10-11 17:12:13 -04:00
Ian Campbell
e392b923ed arndale: Apply Cortex-A15 errata #773022 and #774769
We run 4 Arndale boards in our automated test framework, they have
been running quite happily for quite some time using a Debian Wheezy
userspace.

However when upgrading to a Debian Jessie we started seeing frequent
segmentation faults from gcc when building the kernel, to the extent
that it is unable to successfully build the kernel twice in a row, and
often fails on the first attempt.

Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417
which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html
and CPU Errata 773022 and 774769.

This errata needs to be applied to all processors in an SMP system,
meaning that the usual strategy of applying them in
arch/arm/cpu/armv7/start.S is not appropriate (since that applies to
the boot processor only). Instead we apply these errata in the secure
monitor which is code that is traversed by all processors as they are
brought up.

The net affect on Arndale is that ACTLR changes from 0x40 to
0x2000042. I ran 17 kernel compile iterations overnight with no
segfaults.

Runtime testing was done on our v2014.10 based branch and forward
ported (with only minimal and trivial contextual conflicts) to current
master, where it has been build tested only.

I suppose in theory these errata apply to any Exynos5250 based boards,
but Arndale is the only one I have access to and I have therefore
chosen to be conservative and only apply it there.

Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list
numerically sorted.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
2015-10-11 17:12:11 -04:00
Ryan Harkin
fc04b92354 vexpress64: fvp dram: add DRAM configuration
Create an additional FVP configuration to boot images pre-loaded into
DRAM.

Sometimes it's preferential to boot the model by loading the files
directly into DRAM via model parameters, rather than using
SemiHosting.

An example of model parmaters that are used to pre-load the files
into DRAM:
    --data cluster0.cpu0=Image@0x80080000 \
    --data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \
    --data cluster0.cpu0=uInitrd@0x84000000

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Update board/armltd/vexpress64/Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-10-11 17:11:47 -04:00
Yuan Yao
a8ee68df49 dm: dts: ls1021a-twr: Enable DSPI2 on LS1021ATWR
Erratum A-008022 has been fixed on LS1021A Rev2.0.
So we can use DSPI2 now, this patch enable DSPI2
in dts for LS1021ATWR.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Sjoerd Simons
b1f492ca9e rockchip: Reconfigure the malloc based to point to system memory
When malloc_base initially gets setup in the SPL it is based on the
current (early) stack pointer, which for rockchip is pointing into SRAM.
This means simple memory allocations happen in SRAM space, which is
somewhat unfortunate. Specifically a bounce buffer for the mmc allocated
in SRAM space seems to cause the mmc engine to stall/fail causing
timeouts and a failure to load the main u-boot image.

To resolve this, reconfigure the malloc_base to start at the relocated
stack pointer after DRAM  has been setup.

For reference, things did work fine on rockchip before 596380db was
merged to fix memalign_simple due to a combination of rockchip SDRAM
starting at address 0 and the dw_mmc driver not checking errors from
bounce_buffer_start. As a result, when a bounce buffer needed to be
allocated mem_align simple would fail and return NULL. The mmc driver
ignored the error and happily continued with the bounce buffer address
being set to 0, which just happened to work fine..

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-03 10:24:33 -06:00
Tom Rini
996ec1dcc5 Merge branch 'master' of git://git.denx.de/u-boot-fdt 2015-10-03 10:48:06 -04:00
Przemyslaw Marczak
cce573e8d8 trats: fdt: disable unused DW MMC
This device uses SDHCI driver, for eMMC and SD cards.
Trying bind the DW MMC driver with fdt node without all
required properties, causes printing an error.

This commit disables the DW MMC node.

Tested-on: Trats

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Łukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2015-10-03 14:39:19 +01:00
Przemyslaw Marczak
7241df1c39 mach-exynos: clock: restore calling dead exynos4_get_mmc_clk()
After rework of code by:

commit: d952796 Exynos5: Use clock_get_periph_rate generic API

function get_mmc_clk() always returns -1 for Exynos 4.

This was caused by omitting, that SDHCI driver for Exynos 4,
calls get_mmc_clk(), with mmc device number as argument,
instead of pinmux peripheral id, like DW MMC driver for Exynos 5.

By this commit, the code directly calls a proper function
to get mmc clock for Exynos 4, without checking the peripheral id.

Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon).

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-10-03 14:39:19 +01:00
Hans de Goede
97fec7105c sunxi: Add generic defconfigs for A23 Q8 tablets with 800x480 LCD
The 7" Q8 tablet enclosure is used for a ton of slightly different cheap
chinese tablets. There are some differences in which accelerometer /
wifi is used, but other then that these are all the same from a u-boot /
kernel pov.

When we get to adding accelerometer support the plan is to add some kind
of autodetection and mangle the dt accordingly (likely using the new quirks
mechanism).

For now this is a non issue as we do not yet have accelerometer
support, and in the future, some sort of auto-detect is the way to go
as we cannot expect users to exactly know what is inside their tablet.

The dts files this commit adds are identical to the ones submitted
to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-10-03 12:08:04 +02:00
Tom Rini
b8d242121d Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-10-02 09:38:44 -04:00
Albert ARIBAUD \(3ADEV\)
931a1d2a14 vf610: add support for Phytec PCM052
Devices supported are:
- NFC (NAND FLASH)
- MMC
- QSPI (SPI NOR FLASH)
- I2C (only bus 2)
- I2C RTC
- I2C EEPROM
- FEC

Patch-series: 2
- remove useless CONFIG_SYS_SPD_BUS_NUM from config
- remove include of config_cmd_default.h
- remove duplicate CONFIG_CMD_NET

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-10-02 10:42:59 +02:00
Albert ARIBAUD \\(3ADEV\\)
3f353ceccb vf610: refactor DDRMC code
The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-10-02 10:42:31 +02:00
Peng Fan
e2748b4167 imx: mx6: correct enable_fec_anatop_clock
We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock,
otherwise we may overridden configuration before enable_fec_anatop_clock.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-02 10:42:31 +02:00
Tom Rini
2959f936c5 Merge git://git.denx.de/u-boot-marvell 2015-09-30 20:20:59 -04:00
Stefan Roese
787ddb7cd1 arm: mvebu: timer.c: Explicitly move "init_done" var to data section
As reported by Simon Guinot, commit ade741b3
"arm: mvebu: Call timer_init early before PHY and DDR init" breaks
Kirkwood platforms. As the static variable "init_done" is not
available at that early boot time. This patch moves it to explicitly
to the data section, making it available at that time.

Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Simon Guinot <simon.guinot@sequanux.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
2015-10-01 02:00:02 +02:00
Stefan Roese
cefd764222 arm: mvebu: Fix internal register config on A38x
Currently booting on A38x is broken. As the current code tries to detect
the SoC family to disable the MMU for the A38x at runtime. But before the
internal registers are switched to the new location (0xf100.0000), this
runtime detection does not work. As all macros / defines are already
assigned to the new location at 0xf100.0000. But the registers are sill
mapped to the default location at 0xd000.0000.

This patch now makes sure, no such runtime detection is used before
the internal registers are configured to the new location. After this,
the remaining cache cleanup is executed.

Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-01 01:59:34 +02:00
Hans de Goede
46f166caad sunxi: Add generic defconfigs for A33 Q8 tablets with 1024x600 / 800x480 LCD
The 7" Q8 tablet enclosure is used for a ton of slightly different cheap
chinese tablets. There are some differences in which accelerometer /
wifi is used, but other then that these are all the same from a u-boot /
kernel pov.

When we get to adding accelerometer support the plan is to add some kind
of autodetection and mangle the dt accordingly (likely using the new quirks
mechanism).

For now this is a non issue as we do not yet have accelerometer
support, and in the future, some sort of auto-detect is the way to go
as we cannot expect users to exactly know what is inside their tablet.

The dts[i] files this commit adds are identical to the ones submitted
to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-29 11:50:44 +02:00
Bernhard Nortmann
af654d1461 sunxi: retrieve FEL-provided values to environment variables
This patch extends the misc_init_r() function on sunxi boards
to test for the presence of a suitable "sunxi" SPL header. If
found, and the loader ("fel" utility) provided a non-zero value
for the boot.scr address, then the corresponding environment
variable fel_scriptaddr gets set.

misc_init_r() also sets (or clears) the "fel_booted" variable depending
on the active boot device, using the same logic as spl_boot_device().

The goal is to provide sufficient information (within the U-Boot
environment) to make intelligent decisions on how to continue the boot
process, allowing specific customizations for the "FEL boot" case.

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-09-29 11:50:07 +02:00
Bernhard Nortmann
a188438175 sunxi: (mksunxiboot) signature to indicate "sunxi" SPL variant
This patch follows up on a discussion of ways to improve support
for the sunxi FEL ("USB boot") mechanism, especially with regard
to boot scripts, see:
https://groups.google.com/d/msg/linux-sunxi/wBEGUoLNRro/rHGq6nSYCQAJ

The idea is to convert the (currently unused) "pad" bytes in the
SPL header into an area where data can be passed to U-Boot. To
do this safely, we have to make sure that we're actually using
our "sunxi" flavor of the SPL, and not the Allwinner boot0.

The modified mksunxiboot introduces a special signature to the
SPL header in place of the "pub_head_size" field. This can be
used to reliably distinguish between compatible versions of sunxi
SPL and anything else (older variants or Allwinner's boot0).

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-09-29 11:50:07 +02:00
Bernhard Nortmann
e954eb8028 sunxi: move SPL-related definitions to platform-specific include
The sunxi platform currently doesn't seem to make any use of the
asm/arch-sunxi/spl.h file. This patch moves some declarations from
tools/mksunxiboot.c into it.

This enables us to reuse those definitions when extending the
sunxi board code (boards/sunxi/boards.c).

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-09-29 11:50:07 +02:00
Hans de Goede
cb42d63554 sunxi: Simplify spl board_init_f function
crt0.S will both memset the bss sectioan and call board_init_r for us,
so there is no need to do either ourselves.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-29 11:50:07 +02:00
Simon Glass
1090a56c87 arm: Drop old non-generic-board code
This code is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@gmail.com>
2015-09-28 10:48:24 -04:00
Simon Glass
b352182a00 arm: Remove wireless_space board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-28 10:48:24 -04:00
Simon Glass
d7e8b2b98a arm: Remove da830evm board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-28 10:48:23 -04:00
Peter Griffin
9c71bcdc81 ARM: hikey: hi6220: Migrate over to DM_SERIAL and use UART3 by default.
Use DM for the pl01x serial driver on hikey. Also allow UART0 or
UART3 to be chosen via Kconfig.

By default we now output to UART3 as the latest version of ATF outputs
to this UART. Also UART3 comes out on the LS connector, as opposed to
UART0 which goes to a unpopulated header.

As part of this change we also enable CONFIG_BOARD_EARLY_INIT_F and
call the pinmux configuration code for the UART. Before we were
relying on ATF having already configured the pin configuration.

NB: Upstream Linux kernel doesn't yet support UART3, so serial console
will still be output on UART0 when booting a upstream kernel.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-28 10:48:22 -04:00
Peter Griffin
efd7b60a81 ARM: hikey: Select DM, DM_GPIO from Kconfig
Most platforms enable these options from Kconfig rather
than the configs header file.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-28 10:48:22 -04:00
Peter Griffin
f7ca45e891 ARM: hi6220: Add UART0 and UART3 base addresses
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-28 10:48:21 -04:00
Tom Rini
1a9c229bf7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-09-24 12:28:10 -04:00
Tom Rini
d0f30211e9 Merge git://git.denx.de/u-boot-socfpga 2015-09-24 12:28:06 -04:00
Masahiro Yamada
a4bb44b027 ARM: dts: uniphier: use SPDX-License-Identifier
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 01:01:37 +09:00
Masahiro Yamada
d47fe9bb83 ARM: uniphier: fix init page table for ProXstream2/PH1-LD6b USB boot
Currently, the USB boot mode is supported by an external loader and
U-boot proper image is put on the section 0.  This commit allows
access there.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:59:33 +09:00
Masahiro Yamada
019df879a9 ARM: uniphier: add ProXstream2 and PH1-LD6b support
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:59:33 +09:00
Masahiro Yamada
28f40d4a4d ARM: uniphier: add PH1-Pro5 support
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:59:28 +09:00
Masahiro Yamada
323d1f9d5b ARM: uniphier: allow to enable multiple SoCs
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:58:38 +09:00
Masahiro Yamada
e6eecca54f ARM: uniphier: unify low-level debug init code
Move init code of low-level debug into a single file.
This is helpful to create an image that runs on multiple SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
fcbcd59730 ARM: uniphier: fix glitch signal problem for low-level debug
Currently, IECTRL is enabled after pin-mux settings for the low-level
debugging for PH1-LD4 and PH1-sLD8.  While IECTRL is disabled, input
signals are pulled-down, i.e. glitch signal (Low to High transition)
problem occurs if pin-mux is set up first.  As a result, one invalid
character is input to the UART block and the auto-boot counting is
terminated immediately.

The correct initialization procedure is:
 [1] Enable IECTRL (if IECTRL exists for the pins)
 [2] Set up pin-muxing
 [3] Deassert the reset of the hardware block

Currently, the low-level debugging is working for PH1-sLD3 and
PH1-Pro4, but just in case, follow the sequence for all the SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
257b11f32d ARM: uniphier: delete unneeded input enable for low-level debug
The UART I/O ports for PH1-Pro4 has no input enable controlling.
This code is useless.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
8497ccc4c2 ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*
I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify
they belong to UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
c8df23cf33 ARM: uniphier: allow to disable CONFIG_MICRO_SUPPORT_CARD
Without this, build fails if CONFIG_MICRO_SUPPORT_CARD is disabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
d7728aa408 ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local file
It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally.
Move them to a C file as local macros.  Also, rename the C file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
8469700b6c ARM: uniphier: refactor LED function
The macro, led_write(), is now only used in C sources.  There is no
more reason to keep the tricky assembly macro.  Replace it with a
new C function led_puts().

Also, rename board.h to micro-support-card.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
0b198670c6 ARM: uniphier: remove useless wrapper functions
The wrapper functions, uniphier_board_*, are just making function
calls complex.  Remove them.

Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD
is disabled, so that prototype checking works.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
f1378cabc0 ARM: uniphier: remove unused header file
This has been unused since commit f4e190e317 ("ARM: uniphier:
enable SPL_OF_CONTROL").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
cf88affab6 ARM: uniphier: parse device tree to determine DRAM base and size
Device tree specifies the available memory ranges in its "/memory"
node.  Use it to simplify the CONFIG defines.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
9628afa7f5 ARM: uniphier: remove ifdef CONFIG_{SOC} conditionals from sg-regs.h
To achieve the complete run-time configuration by device trees, ifdef
conditionals in header files are not preferable.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
d5ed8c5727 ARM: uniphier: change the external bus address mapping
In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
 0x00000000 - 0x0fffffff
 0x40000000 - 0x4fffffff
are both mapped to the external bus (also called system bus),
so either was OK.

In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is
assigned for the serial NOR interface.

Going forward, use the latter for the external bus.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
9879842c6f ARM: uniphier: drop DCC micro support card support
Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards.  It has been painful to maintain
both.  Having one of them is enough.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-25 00:27:52 +09:00
Masahiro Yamada
1386233da3 ARM: uniphier: drop ad-hoc input enable settings
These input enable settings are handled by the pinctrl drivers.

Because the external bus pins are input-enabled by default, on-board
devices such as LED still work fine even with this delayed input
enabling.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:52 +09:00
Masahiro Yamada
11f3afeaa5 ARM: uniphier: drop ad-hoc early pin-muxing settings
As the UniPhier serial driver had already switched to Drive Model
and the pinctrl drivers are now enabled, these pin-muxing settings
are properly handled by the pinctrl drivers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-25 00:27:52 +09:00
Masahiro Yamada
b25c4ab5be ARM: dts: uniphier: prepare device trees to use pinctrl in SPL
Add "u-boot,dm-pre-reloc" for device nodes we want in SPL DTB
(spl/u-boot-spl.dtb).

The "soc" node (this is simple-bus node) also needs the property
to bind the pinctrl node located under it.

I am collecting this U-Boot specific hack to the bottom of board
DTS rather than inserting "u-boot,dm-pre-reloc" into SoC DTSI.
My goal is to sync DTSI with Linux for easier maintenance.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-25 00:27:52 +09:00
Peng Fan
f697c2acca imx: fix coding style
Fix coding style.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-24 11:32:38 +02:00
Peng Fan
4406da0f49 imx-common: wrap boot_mode_apply with CONFIG_CMD_BMODE
boot_mode_apply should be applied only with CONFIG_CMD_BMODE enabled.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-24 11:31:58 +02:00
Peng Fan
d449701b83 imx: mx7: discard unused global variable
Discard unused global variable.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-24 11:31:37 +02:00
Peng Fan
cf226d9942 imx-common: consider mux_ctrl_ofs when setting mux_mode
Some i.MXes use __NA_ or 0 to avoid setting mux_mode, but the following patch
only take i.MX6/7 into consideration.

"c3c8a5748897b24f18618047804317167a531dd3 imx-common: fix iomux settings"

Use is_soc_type(MXC_CPU_MX7) to avoid breaking other i.MXes when
setting mux_mode.

In this patch, switch to use "asm/imx-common/sys_proto.h" to avoid
build break for "is_soc_type" for vf610 and mx25.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2015-09-24 11:27:22 +02:00
Dinh Nguyen
3cbc7b878b arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files
Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and
socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA
board config files.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-23 03:55:28 +02:00
Peng Fan
f05f4528f2 imx: mx7: drop select CPU_V7 for board target
drop select CPU_V7 for board target, since ARCH_MX7 selects CPU_V7.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-20 09:55:11 +02:00
Peng Fan
c3c8a57488 imx-common: fix iomux settings
When setting iomux for a pin mux, there is no need to check mux_ctrl_ofs.
Also If still checking mux_ctrl_ofs, we have no chance to set iomux
for i.MX7D IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00, because the mux_ctrl_ofs
for this register is 0.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:39:06 +02:00
Thierry Reding
8e1601d994 ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:11:31 -07:00
Thierry Reding
aba11d4476 ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").

Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:11:31 -07:00
Mirza Krak
20613c9231 ARM: tegra: Add Tegra20 SPI device nodes
Add the device tree node for the SPI controllers found on Tegra20 SOCs.

Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:23 -07:00
Thierry Reding
97c02d87f4 ARM: tegra: clk_m is the architected timer source clock
While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies. clk_m will be divided down
from the oscillator.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:22 -07:00
Thierry Reding
c043c0259c ARM: tegra: Implement clk_m
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:22 -07:00
Thierry Reding
70bcb43e7d armv8: Make COUNTER_FREQUENCY optional
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:22 -07:00
Stephen Warren
6c7dc6236a ARM: tegra: fix PLLP frequency calc on T210
AFAIK, for all PLLs on all Tegra SoCs, the primary PLL output frequency
is (input * m) / (n * p). However, PLLP's primary output (pllP_out0) on
T210 is the VCO output, and divp is not applied. pllP_out2 does have divp
applied. All other pllP_outN are divided down from pllP_out0. We only
support pllP_out0 in U-Boot at the time of writing.

Fix clock_get_rate() to handle this special case.

This corrects the returned rate for PLLP to be 408MHz rather than 204MHz.
In turn, this causes high enough dividers to be calculated for the various
peripheral clocks that feed off of PLLP. Without this, some peripherals
failed to operate correctly. For instance, one of my SD cards worked
perfectly but an older (presumably slower) card could not be read.

Note that prior to commit 722e000ccd "Tegra: PLL: use per-SoC pllinfo
table instead of PLL_DIVM/N/P, etc.", the calculated PLL frequency was
816MHz since the wrong values were being extracted from the PLLP divider
register. This caused overly large peripheral dividers to be calculated,
which while wrong, didn't cause any correctness issues; things simply ran
slower than they could.

Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:22 -07:00
Axel Lin
a6b2daffde tegra: Remove tegra_spl_gpio_direction_output declaration from header file
This function is deleted by commit 2fccd2d96b
"tegra: Convert tegra GPIO driver to use driver model".

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:22 -07:00
Stephen Warren
2573428140 ARM: tegra: Add p2371-2180 board
P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and
two GPIO expansion headers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:22 -07:00
Stefan Roese
86dc8b14f9 arm: Remove unused reference to nomadik
Commit 0abdd9d0 "arm: Remove nhk8815 boards and nomadik arch" missed one
reference to this arch. Lets remove this as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2015-09-15 15:05:22 -04:00
Stefan Roese
68282f55b8 arm: Remove unused ST-Ericsson u8500 arch
This arch does not seem to be supported / used at all in the current
U-Boot mainline source tree any more. So lets remove the core u8500 code
and code that was only referenced by this platform.

Please note that this patch also removes these config options:

- CONFIG_PL011_SERIAL_RLCR
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT

As they only seem to be referenced by u8500 based boards. Without any
such board in the current code, these config option don't make sense
any more. Lets remove them as well.

If someone still wants to use this platform, then please send patches
to re-enable support by adding at least one board that references this
code.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-15 15:05:21 -04:00
Tom Rini
850f788709 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2015-09-13 17:25:16 -04:00
Fabio Estevam
3a384b494c imx-common: cpu: Do not print on invalid temperature
It is not very useful to have the message below on every boot
(especially when we are using early silicon):

U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device

, so turn the error message into debug level.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-13 10:50:55 +02:00
Peng Fan
ada5771f09 imx: mx6 discard 'select CPU_V7' for different targets
Discard the 'select CPU_V7' from Kconfig in arch/arm/cpu/armv7/mx6
for different targets, because ARCH_MX6 selects CPU_V7.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-13 10:38:48 +02:00
Peng Fan
d9cbb264e8 imx: mx6ul: support mx6ul 9x9 evk board
This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk,
the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are:
1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC.
2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk
   supports 512MB DDR3
3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package.

This patch add the following:
1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size()
2. Introduce a macro is_mx6ul_9x9_evk using
   CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL
   part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work,
   so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with
   mx6ul_14x14_evk. And we have no way to dymaically checking this chip
   is 9x9 or 14x14.
3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations.
   POWER related configurations also effect for mx6ul_14x14_evk. But
   power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to
   do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk.
4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM
   configurations.
5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file
   according to board_rev and board_name.
6. Add TARGET_MX6UL_9X9_EVK Kconfig entry

Boot Log:
U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53)
reading u-boot.img
reading u-boot.img

U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 41C
Reset cause: POR
Board: MX6UL 9x9 EVK
I2C:   ready
DRAM:  256 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:   FEC1
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-13 10:32:44 +02:00
Peng Fan
0eca9f6f0d Revert "imx: mx6: ddr correct tRFC and tXS"
This reverts commit 059323fb6a8f21637bb617919715c2427f24777c.

This commit 059323fb6a8f21637bb617919715c2427f24777c use JESD79-3E which
is not the newest spec. Should use JESD79-3F in which tRFC is 260ns for
4Gb chip.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-13 10:26:45 +02:00
Adrian Alonso
1a8150d4b1 imx: mx7dsabresd: Add support for MX7D SABRESD board
* Add i.MX7D SABRESD target board support with enabled modules:
  UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.

  Build target: mx7dsabresd_config

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:54 +02:00
Adrian Alonso
cd562c8d07 imx: imx7d: add imx-common cpu support for imx7d
Add imx-common cpu support for imx7d SoC
- Update reset_cause for imx7d
- Enable watchdog driver built for imx7d

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-09-13 10:11:54 +02:00
Adrian Alonso
648539c906 arm: imx-common: init: rework wdog settings for imx6/imx7
Rework imx_set_wdog_powerdown to be reused by imx6 and imx7

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:54 +02:00
Adrian Alonso
75a565f297 arm: imx-common: init: extend init_aips to support imx7
Extend init_aips to support imx7 SoC, use is_soc_type
and is_cpu_type to resolve at run time aips3 settings

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:54 +02:00
Adrian Alonso
c5752f73a5 imx: imx7d: Add SoC system support
Add imx7d basic SoC system support
Misc arch dependent functions for system bring up

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
7bebc4b04e imx: imx7d: clock control module support
* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
  root frequency generation denominated clock slices.
  Core clock slice: hihg speed clock for ARM core
  Bus clock slice: for bus clocks
  IP clock slice: Peripheral clocks
* At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
  In u-boot, we have to:
  - Configure PFD3- PFD7 for freq we needed in u-boot
  - Set clock root for peripherals (ip channel)

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
b1d902a9f7 imx: imx7d: initial arch level support
* Add system arch level header files
  - imx-regs.h: iMX7D SoC system architecture registers
  - crm_regs.h: Clock control module registers
  - sys_proto.h: helper callback function for SoC setup

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
6953574188 imx: system counter driver for imx7d and mx6ul
Add system counter driver for imx7d and mx6ul
imx7 and imx6ul supports system counter timer as well as
GPT timer (arch/arm/imx-common/timer.c); The default for
imx7 is systemcounter timer.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
50a082a88c arm: imx: imx-common: init: move arch init common setup
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
ab09e72866 arm: imx: common rework cache settings for imx6
Rework cache settings for imx6, move cache configuration
to imx-common/cache.c so it can be reused for newer SoC

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
1368f99346 thermal: imx_thermal: rework driver to be reused
Rework imx_thermal driver to be used across i.MX
processor that support thermal sensor

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
15c52b3ddd imx: arch-mx6: add is_soc_type helper macro
Add helper macro is_soc_type to identify iMX SoC family

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:52 +02:00
Peng Fan
208bd51396 arm: armv8 correct value passed to __asm_dcache_all
>From source code comments:
"x0: 0 flush & invalidate, 1 invalidate only"

Current value 0xffff can make invalidate work, since we only judge whether
input value is 0 or not, see following code:
"
    tbz     w1, #0, 1f
    dc      isw, x9
    b       2f
1:  dc      cisw, x9      /* clean & invalidate by set/way */
2:  subs    x6, x6, #1    /* decrement the way */
"

Later we may add "2 clean only" support. So following the comments,
correct value from 0xffff to 1.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2015-09-12 09:03:39 +02:00
Simon Glass
ed64190f67 arm: Correct comments in crt0.S for the recent SPL improvements
The current comments need a bit of tweaking since we now support stack
and global_data relocation in SPL. Also add a reference to the README.

For AArch64 this is not implemented, so leave a TODO for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tim Harvey <tharvey@gateworks.com>
2015-09-12 09:00:35 +02:00
Sylvain Lemieux
89983478bd gpio: lpc32xx: fix issues with port3 gpio
The current simplify lpc32xx gpio driver implementation assume a
maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO
and 6 GPIO to managed on port 3.

Update the driver to fix the following:
1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number)
   the second call to "gpio_request" will return -EBUSY.

2) The status of GPO_xx pin report the status of the
   corresponding GPI_xx pin when using the "gpio status" command.

3) The gpio driver may setup the direction register for the wrong
   gpio when calling "gpio_direction_input" (GPI_xx) or
   "gpio_direction_output" (GPO_xx) on port 3; the call to the
   direction is require to use the "gpio status" command.

The following change were done in the driver:
1) port3 GPI are cache in a separate 32 bits in the array.
2) port3 direction register written only for GPIO pins.
3) port3 GPO & GPIO (as output) are read using "p3_outp_state".
4) LPC32XX_GPI_P3_GRP updated to match the change.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-09-11 17:15:34 -04:00
Heiko Schocher
92a3188d7d bitops: introduce BIT() definition
introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-09-11 17:15:32 -04:00
Enric Balletbò i Serra
9d1b298799 board: Add Toby-Churchill SL50 board support.
Add support for Lightwriter SL50 series board, a small, robust and portable
Voice Output Communication Aids (VOCA) designed to meet the particular and
changing needs of people with speech loss resulting from a wide range of
acquired, progressive and congenital conditions.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2015-09-11 17:15:27 -04:00
Stefan Roese
da53ba0219 arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4
This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
switch between both ECC schemes for backwards compatibility.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2015-09-11 17:15:14 -04:00
Simon Glass
b9599dd857 arm: Remove tx25 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 17:15:12 -04:00
Simon Glass
ad4f54ea86 arm: Remove palmtreo680 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 17:14:44 -04:00
Simon Glass
1c87dd76c4 arm: Remove xaeniax board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 17:14:43 -04:00
Simon Glass
452ef83046 arm: Remove vpac270_nor_128 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 17:14:23 -04:00
Simon Glass
6e830dfc1a arm: Remove vl_ma2sc board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 17:12:57 -04:00
Simon Glass
bee2b99d06 arm: Remove vision2 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-09-11 16:05:03 -04:00
Simon Glass
b928e658f4 arm: Remove versatileab board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 15:01:25 -04:00
Simon Glass
0c81f37d9a arm: Remove tt01 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 15:00:52 -04:00
Simon Glass
f73db66d62 arm: Remove tk71 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 15:00:22 -04:00
Simon Glass
7650beb7ca arm: Remove scb9328 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 15:00:03 -04:00
Simon Glass
47b87d2eed arm: Remove rd6281a board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:59:16 -04:00
Simon Glass
daf770864d arm: Remove qong board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:59:16 -04:00
Simon Glass
49d8899ba9 arm: Remove pxa255_idp, zipitz2 boards
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:58:48 -04:00
Simon Glass
79d19734a9 arm: Remove portuxg20, stamp9g20 boards
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:58:48 -04:00
Simon Glass
f6eac00aba arm: Remove polaris and trizepsiv boards
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-09-11 14:58:47 -04:00
Simon Glass
8896325d73 arm: Remove palmtc board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:57:41 -04:00
Simon Glass
35782e9cca arm: Remove palmld board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:57:41 -04:00
Simon Glass
819216ddfa arm: Remove otc570 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:57:40 -04:00
Simon Glass
7a2c1b13d7 arm: Remove openrd boards
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:56:53 -04:00
Simon Glass
93b25c0813 arm: Remove omap3_sdp3430 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:56:52 -04:00
Simon Glass
8dc372f93b arm: Remove omap3_mvblx board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:56:51 -04:00
Simon Glass
0abdd9d01a arm: Remove nhk8815 boards and nomadik arch
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:56:04 -04:00
Simon Glass
b6073fd211 arm: Remove mx51_efikamx, mx51_efikasb boards
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:56:03 -04:00
Simon Glass
7cd768cf2c arm: Remove mv88f6281gtw_ge board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:55:18 -04:00
Simon Glass
9f840b8d56 arm: Remove lp8x4x board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:53:50 -04:00
Simon Glass
df0b116de1 arm: Remove jornada board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:53:10 -04:00
Simon Glass
36d14178fc arm: Remove mx31_litekit board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:52:46 -04:00
Simon Glass
bc0840bcb7 arm: Remove imx27lite, imx27_litekit and magnesium boards
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:52:11 -04:00
Simon Glass
3eb8f58d75 arm: Remove ima3-mx53 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:11:53 -04:00
Simon Glass
a6f7f78744 arm: Remove enbw_cmc board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:11:15 -04:00
Simon Glass
5522f12b3c arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards
These board have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:11:13 -04:00
Simon Glass
5ff33d0404 arm: Remove dig297 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:11:12 -04:00
Simon Glass
6761946fb7 arm: Remove unmaintained davinci boards
These boards have not been converted to generic board by the deadline.
Remove dm355evm, dm355leopard, dm365evm, dm6467evm, dvevm, ea20, schmoogie,
sffsdr, sonata.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:11:11 -04:00
Simon Glass
7495e41ba6 arm: Remove snowball and u8500_href boards
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:08:06 -04:00
Simon Glass
af7f884ba1 arm: Remove eukrea boards
These boards have not been converted to generic board by the deadline.
Remove all cpu9260 and cpuat91 boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:06:45 -04:00
Simon Glass
679d4456e9 arm: Remove balloon3 board
This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:06:44 -04:00
Lokesh Vutla
d6927a5d10 ARM: DRA7: emif: Fix disabling/enabling of refreshes
clrsetbits_le32/clrbits_le32 takes mask of the bits as input that
are needed to be set/clear. But emif driver passes the shift of the bits.
Fixing it here.

Reported-by: Mark Mckeown <m-mckeown@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-09-11 14:05:36 -04:00
Vladimir Zapolskiy
bab8d1e228 lpc32xx: remove duplicated DMA_CLK_ENABLE bit definition
Because there is an originally defined CLK_DMA_ENABLE macro in clk.h,
no reason to add another DMA_CLK_ENABLE macro with the same value.

Remove DMA_CLK_ENABLE, since it does not follow naming convention from
the code, this implies renaming of DMA_CLK_ENABLE to CLK_DMA_ENABLE in
lpc32xx/devices.c file.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-09-11 14:05:35 -04:00
Jelle van der Waa
2ad76bf2c7 sun5i: Add A10s-Wobo-i5 defconfig and dts
The Wobo i5 top set box is a somewhat curious A10s based top set box,
it uses an AXP209 rather then the AXP152 usually used in combination
with the A10s. It has an ethernet phy connected to PORTD rather then
PORTA, and its built-in usb wifi is connected via the otg controller.

The dts file changes are identical to the changes submitted to the
upstream kernel.

Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-09-10 20:13:01 +02:00
Hans de Goede
56f5eb401d sun5i: Add q8_a13_tablet defconfig and dts
This commits adds a generic support for q8 formfactor a13 based tablets.

These tablets ship in many variants, with the difference mainly being the
touchscreen controller / accelerometer / wifi chip used.

The wifi is USB based, and thus not listed in devicetree.

ATM the kernel does not support the touchscreen / accelerometer on these
devices. In the future we may need multiple configs with different
CONFIG_DEFAULT_DEVICE_TREE settings, this depends on how we solve the
hw differences on the kernel side.

For now this will suffice.

The dts files are identical to the dts files submitted to the upstream
kernel for these tablets.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-10 20:11:58 +02:00
Hans de Goede
05e4d62a63 sun4i: Add dts and defconfig for iNet-1 based tablets
The iNet-tek iNet-1 PCB is a PCB found in various generic 10.1" 1024x600
A10 based tablets such as the Point of View Protab2 XXL and the
Cherry M1007.

This patch has been tested on both rev2 and rev5 of this board / these
tablets.

These tablets feature the usual connectors: headphone, mini hdmi,
power-barrel, mini-usb and a micro-sd slot.

The dts is identical to the dts submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-10 17:11:45 +02:00
Hans de Goede
deed69d62d sun4i: Add defconfig and dts for inet9f-rev03 based tablets
The inet9f-rev03 pcb is specially designed for gaming tablets, such as
the qware tb-g100 tablet.

These 7" tablets feature a dpad, firebuttons and 2 joysticks on the sides
of the screen.

Besides this they have the usual connectors: power-barrel, mini usb,
mini hdmi, headphone and micro-sd slot.

The dts is identical to the dts submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-10 17:11:45 +02:00
Hans de Goede
dd9d013c03 sun4i: Add defconfig and dts for the pov protab2-ips9 tablet
The Point of View protab2-ips9 is a tablet with a 9" ips 1024x768 lcd
screen, microsd slot, headphones, mini hdmi, mini usb b and power barrel
connectors.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-10 16:55:22 +02:00
Dinh Nguyen
55c7a765f6 arm: socfpga: Add support for the Terasic DE-0 Atlas board
Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV
based board. The board can boot from SD/MMC. Ethernet is also supported.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-04 11:54:21 +02:00
Marek Vasut
d88995a82b arm: socfpga: Add support for DENX MCV SoM and MCVEVK board
Add support for DENX MCV SoM, which is CycloneV based and the
associated DENX MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-09-04 11:54:21 +02:00
Marek Vasut
952caa289e arm: socfpga: Add support for Terasic SoCkit board
Add support for Terasic SoCkit, which is CycloneV based board.
The board can boot either from SD/MMC or QSPI. Ethernet is also
supported.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-09-04 11:54:21 +02:00
Marek Vasut
a665b051b5 arm: socfpga: Do not call board_init_r() from board_init_f()
Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the SoCFPGA SPL with the correct SPL design as well as reduces
the stack utilisation slightly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-04 11:54:20 +02:00
Marek Vasut
dfd3dff50a arm: socfpga: Always enable OF_CONTROL and SPL_OF_CONTROL
The SoCFPGA probes mostly from OF and the OF is mandatory both in
U-Boot itself and U-Boot SPL. Enable it by default.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-09-04 11:54:20 +02:00
Marek Vasut
65d372c44c arm: socfpga: Assure ISWGRP 0 and 1 are inited
This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
correctly inited. In case those registers are not initialized,
it is not possible to access the registers synthesised in the
FPGA through the bridges. Any such access produces data abort.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-04 11:54:20 +02:00
Marek Vasut
129adf5bf4 mmc: dw_mmc: Probe the MMC from OF
Rework the driver to probe the MMC controller from Device Tree
and make it mandatory. There is no longer support for probing
from the ancient qts-generated header files.

This patch now also removes previous temporary workaround.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
2015-09-04 11:54:20 +02:00
Tom Rini
c9feb427ab Merge git://git.denx.de/u-boot-rockchip 2015-09-03 14:57:09 -04:00
Sjoerd Simons
81b0618ddf arm: Turn of d-cache before i-cache
Booting the kernel fails on RK3288 (and probably other rockchip SoCs)
when the i-cache is disabled/flushed before d-cache.

I have not investigated whether this is due to U-Boot hanging or whether
it's very early in the linux boot, but following the approach of the
various rockchip U-Boot forks (first disable d-cache then i-cache) makes
things work.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:25 -06:00
Sjoerd Simons
7e27815a46 rockchip: Disable sdio mmc slot on rk3288-firefly
U-Boot can't use the sdio card so turn it of to prevent things getting
confused/struck when trying to use the card as storage.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
e2e947ff6b rockchip: Add basic support for jerry
This builds and displays an SPL message, but does not function beyond that.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
17aa548ced rockchip: Add basic support for firefly-rk3288
The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.

This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
1b2fd5bf4e rockchip: Add SPI driver
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
3437469985 rockchip: Add I2C driver
Add an I2C driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
2444dae587 rockchip: Add core SoC start-up code
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
5ff093ab9e rockchip: rk3288: Add SDRAM init
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
13d80ff5af rockchip: rk3288: Add a simple syscon driver
Add a driver that provides access to system controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
3c5d0e34f6 rockchip: rk3288: Add SoC reset driver
We can reset the SoC using some CRU (clock/reset unit) registers. Add support
for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
7f4fd26bf2 rockchip: rk3288: Add header files for PMU and GRF
PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
99c1565082 rockchip: rk3288: Add clock driver
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3288.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:23 -06:00
Simon Glass
26ad30e9d3 rockchip: Add basic peripheral and clock definitions
Add header files for the peripherals and clocks supported on Rockchip
platforms. The particular implementation (and register set) for each is
SoC-specific, but it seems that the naming can be generic.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:23 -06:00
Simon Glass
1f8f7730a8 rockchip: gpio: Add rockchip GPIO driver
This supports RK3288 at present. It does not implement functions or support
for pull up/down.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:23 -06:00
Simon Glass
73a88d0e44 rockchip: rk3288: dts: Make core devices available early
In SPL we need access to the CRU and other peripherals so we can set up
SDRAM. Mark these so that they will remain in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:23 -06:00
Simon Glass
344c837686 rockchip: Bring in RK3288 device tree file includes and bindings
Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:23 -06:00
Simon Glass
c6aabe9289 arm: reset: Avoid a build error when the reset uclass is enabled
There can be only one do_reset(). When CONFIG_RESET is enabled this is
provided by the reset uclass, and ARM's version should be disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:23 -06:00
Tom Rini
345243eda4 arch/arm/Kconfig: Add back in missing entries.
In 2178282 we accidentally dropped out hilsilicon and cm_t43.  Bring
these back in.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-09-02 15:35:30 -04:00
Adam Ford
7b77b1f63b Convert omap3_logic to ti_omap3_common.h
Convert to using the common config files.

Signed-off-by: Adam Ford <adam.ford@logicpd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-09-02 11:33:20 -04:00
Tom Rini
0ffadab1b9 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-09-02 10:39:28 -04:00
Peng Fan
37cf215253 imx: vf610 add get_cpu_rev
Since we need to support runtime check for different drivers, we need
to add get_cpu_rev for vf610, otherwise there will be build errors.

This patch introduces a dummy CPU id which is not read from chip
silicon. Later when we can get the real id from chip, can fix the
value of MXC_CPU_VF610 then.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Suggested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-09-02 15:39:51 +02:00
Peng Fan
7296a02358 mxc: ocotp fix hole in shadow registers
There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.

Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.

When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:39:51 +02:00
Heiko Schocher
9627084c23 arm, imx6: add aristainetos 2b board version
there is a 2b board version of the aristainetos2
board. Differences to the v2:

- spi cs for the nor flash and display controller
  changed
- some pinmux changes
- LED gpio settings changed

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-09-02 15:38:16 +02:00
Peng Fan
d5b2112e75 imx: mx6ul_14x14_evk select MX6UL
There is no need to expose SoC choice to user, we already got
the SoC according to the build target. So default "select MX6UL"
for MX6UL_14x14_EVK target.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:13 +02:00
Peng Fan
f3e9bec865 arm: Add SYS_L2CACHE_OFF Kconfig entry
To i.MX6UL, SYS_L2CACHE_OFF is selected, but there is no Kconfig entry
for SYS_L2CACHE_OFF. Then "select SYS_L2CACHE_OFF" does not effect for
i.MX6UL, which is not expected.

Since SYS_L2CACHE_OFF is mainly used by ARM architecture, add it to
arch/arm/Kconfig.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-02 15:34:13 +02:00
Peng Fan
e7d3b21bb7 imx: mx6slevk: add SPL support
Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code to do related initialization.

Boot Log:

U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000)

CPU:   Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 50C
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:13 +02:00
Peng Fan
eb796cbb69 imx: mx6: ddr: add LPDDR2 support
Add LPDDR2 support:
1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2.
2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to
   mx6_ddr3_cfg, but still keep it a single one for easy to choose
   parameters for LPDDR2.
3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC.
4. Update comments.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-02 15:34:12 +02:00
Peng Fan
f2ff834365 imx: mx6: ddr init MMDC according to ddr_type
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.

Initialize ddr_type for different boards which enable SPL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
003fa83c43 imx: mx6: ddr add an entry ddr_type for mx6_ddr_sysinfo
Add ddr_type entry for mx6_ddr_sysinfo. It will be used for
differenrate DDR3 and LPDDR2.

Introduce an enum type for ddr_type.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-02 15:34:12 +02:00
Peng Fan
775d591f5d imx: mx6: ddr add mpzqlp2ctl entry
Add mpzqlp2ctl entry for mx6_mmdc_calibration.
MMDC_MPZQLP2CTL register is for init tZQINIT, tZQCL, tZQCS for LPDDR2 chips.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-02 15:34:12 +02:00
Peng Fan
1b811e285c imx: mx6: ddr add dram io configuration and header file for i.MX6SL
Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs.
Add a new function mx6sl_dram_iocfg to configure dram io.
Add header file to define macros for register address.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
2cd8cd06bb imx: mx6: ddr correct tRFC and tXS
To Chip density 4Gb, tRFC should be 300ns, see
"Table 61 — Refresh parameters by device density" of JESD79-3E.
tXS(min) is max(5nCK, tRFC(min) + 10ns).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-09-02 15:34:12 +02:00