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https://github.com/AsahiLinux/u-boot
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arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPL
When running on the AXP I sometimes noticed a strange behavior. As some characters are not echoed on the U-Boot prompt. Not disabling the lowlevel_init code, especially calling cpu_init_cp15() in the main U-Boot seems to solve this issue. Signed-off-by: Stefan Roese <sr@denx.de>
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944c7a3176
commit
42cc034f19
4 changed files with 25 additions and 12 deletions
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@ -27,6 +27,14 @@ static struct mbus_win windows[] = {
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
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};
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void lowlevel_init(void)
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{
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/*
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* Dummy implementation, we only need LOWLEVEL_INIT
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* on Armada to configure CP15 in start.S / cpu_init_cp15()
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*/
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}
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void reset_cpu(unsigned long ignored)
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{
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struct mvebu_system_registers *reg =
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@ -214,7 +222,10 @@ static void setup_usb_phys(void)
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int arch_cpu_init(void)
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{
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
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#if !defined(CONFIG_SPL_BUILD)
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struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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/*
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* Only with disabled MMU its possible to switch the base
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* register address on Armada 38x. Without this the SDRAM
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@ -234,18 +245,14 @@ int arch_cpu_init(void)
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* configured the internal register base to the value used
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* in the macros / defines in the U-Boot header (soc.h).
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*/
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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/*
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* To fully release / unlock this area from cache, we need
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* to flush all caches and disable the L2 cache.
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*/
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icache_disable();
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dcache_disable();
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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/*
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* To fully release / unlock this area from cache, we need
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* to flush all caches and disable the L2 cache.
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*/
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icache_disable();
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dcache_disable();
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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#endif
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/*
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@ -16,7 +16,9 @@
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#define CONFIG_SYS_L2_PL310
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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#endif
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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@ -13,7 +13,9 @@
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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#endif
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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@ -11,7 +11,9 @@
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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#endif
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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