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board: Add Toby-Churchill SL50 board support.

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Add support for Lightwriter SL50 series board, a small, robust and portable
Voice Output Communication Aids (VOCA) designed to meet the particular and
changing needs of people with speech loss resulting from a wide range of
acquired, progressive and congenital conditions.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
This commit is contained in:
Enric Balletbò i Serra 2015-09-07 07:43:20 +02:00 committed by Tom Rini
parent aa46b408a5
commit 9d1b298799
9 changed files with 768 additions and 0 deletions
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8
arch/arm/Kconfig
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@ -363,6 +363,13 @@ config TARGET_AM335X_EVM
select DM_SERIAL
select DM_GPIO
config TARGET_AM335X_SL50
bool "Support am335x_sl50"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_SERIAL
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
select CPU_V7
@ -755,6 +762,7 @@ source "board/st/stm32f429-discovery/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/birdland/bav335x/Kconfig"

31
board/tcl/sl50/Kconfig Normal file
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@ -0,0 +1,31 @@
if TARGET_AM335X_SL50
config SYS_BOARD
default "sl50"
config SYS_VENDOR
default "tcl"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "am335x_sl50"
config CONS_INDEX
int "UART used for console"
range 1 6
default 1
help
The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
in documentation, etc) available to it. Depending on your specific
board you may want something other than UART0 as for example the IDK
uses UART3 so enter 4 here.
config DM_GPIO
default y
config DM_SERIAL
default y
endif

6
board/tcl/sl50/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
SL50 BOARD
M: Enric Balletbo i Serra <enric.balletbo@collabora.com>
S: Maintained
F: board/tcl/sl50/
F: include/configs/am335x_sl50.h
F: configs/am335x_sl50_defconfig

13
board/tcl/sl50/Makefile Normal file
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@ -0,0 +1,13 @@
#
# Makefile
#
# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
obj-y += board.o

386
board/tcl/sl50/board.c Normal file
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@ -0,0 +1,386 @@
/*
* board.c
*
* Board functions for TCL SL50 board
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include <environment.h>
#include <watchdog.h>
#include <environment.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr3_sl50_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_sl50_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();
env_relocate_spec();
if (getenv_yesno("boot_os") != 1)
return 1;
#endif
return 0;
}
#endif
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr_sl50 = {
400, OSC-1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
int mpu_vdd;
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
/* BeagleBone PMIC Code */
int usb_cur_lim;
if (i2c_probe(TPS65217_CHIP_PM))
return;
/*
* Increase USB current limit to 1300mA or 1800mA and set
* the MPU voltage controller as needed.
*/
if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
} else {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
TPS65217_POWER_PATH,
usb_cur_lim,
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("tps65217_reg_write failure\n");
/* Set DCDC3 (CORE) voltage to 1.125V */
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
TPS65217_DCDC_VOLT_SEL_1125MV)) {
puts("tps65217_voltage_update failure\n");
return;
}
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set DCDC2 (MPU) voltage */
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
puts("tps65217_voltage_update failure\n");
return;
}
/*
* Set LDO3 to 1.8V and LDO4 to 3.3V
*/
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_1_8,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS2,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
return &dpll_ddr_sl50;
}
void set_uart_mux_conf(void)
{
#if CONFIG_CONS_INDEX == 1
enable_uart0_pin_mux();
#elif CONFIG_CONS_INDEX == 2
enable_uart1_pin_mux();
#elif CONFIG_CONS_INDEX == 3
enable_uart2_pin_mux();
#elif CONFIG_CONS_INDEX == 4
enable_uart3_pin_mux();
#elif CONFIG_CONS_INDEX == 5
enable_uart4_pin_mux();
#elif CONFIG_CONS_INDEX == 6
enable_uart5_pin_mux();
#endif
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
const struct ctrl_ioregs ioregs_evmsk = {
.cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
.cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
.cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
.dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
.dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs_bonelt = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs_evm15 = {
.cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
.cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
.cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
.dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
.dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs = {
.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
};
void sdram_init(void)
{
config_ddr(400, &ioregs_bonelt,
&ddr3_sl50_data,
&ddr3_sl50_cmd_ctrl_data,
&ddr3_sl50_emif_reg_data, 0);
}
#endif
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
return 0;
}
#endif
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif
/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
* in the environment
* Perform fixups to the PHY present on certain boards. We only need this
* function in:
* - SPL with either CPSW or USB ethernet support
* - Full U-Boot, with either CPSW or USB ethernet
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
&& defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
!defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#ifdef CONFIG_DRIVER_TI_CPSW
mac_lo = readl(&cdev->macid1l);
mac_hi = readl(&cdev->macid1h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!getenv("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("eth1addr", mac_addr);
}
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
/*
*
* CPSW RGMII Internal Delay Mode is not supported in all PVT
* operating points. So we must set the TX clock delay feature
* in the AR8051 PHY. Since we only support a single ethernet
* device in U-Boot, we only do this for the first instance.
*/
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY 0x100
#endif
#if defined(CONFIG_USB_ETHER) && \
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
rv = usb_eth_initialize(bis);
if (rv < 0)
printf("Error %d registering USB_ETHER\n", rv);
else
n += rv;
#endif
return n;
}
#endif

22
board/tcl/sl50/board.h Normal file
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@ -0,0 +1,22 @@
/*
* board.h
*
* TCL SL50 boards information header
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_H_
#define _BOARD_H_
void enable_uart0_pin_mux(void);
void enable_uart1_pin_mux(void);
void enable_uart2_pin_mux(void);
void enable_uart3_pin_mux(void);
void enable_uart4_pin_mux(void);
void enable_uart5_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(void);
#endif

154
board/tcl/sl50/mux.c Normal file
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@ -0,0 +1,154 @@
/*
* mux.c
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
static struct module_pin_mux uart1_pin_mux[] = {
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
{-1},
};
static struct module_pin_mux uart2_pin_mux[] = {
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
{-1},
};
static struct module_pin_mux uart3_pin_mux[] = {
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
{-1},
};
static struct module_pin_mux uart4_pin_mux[] = {
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
{-1},
};
static struct module_pin_mux uart5_pin_mux[] = {
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static struct module_pin_mux i2c1_pin_mux[] = {
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_uart1_pin_mux(void)
{
configure_module_pin_mux(uart1_pin_mux);
}
void enable_uart2_pin_mux(void)
{
configure_module_pin_mux(uart2_pin_mux);
}
void enable_uart3_pin_mux(void)
{
configure_module_pin_mux(uart3_pin_mux);
}
void enable_uart4_pin_mux(void)
{
configure_module_pin_mux(uart4_pin_mux);
}
void enable_uart5_pin_mux(void)
{
configure_module_pin_mux(uart5_pin_mux);
}
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
}

10
configs/am335x_sl50_defconfig Normal file
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CONFIG_ARM=y
CONFIG_TARGET_AM335X_SL50=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_CONS_INDEX=1
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set

138
include/configs/am335x_sl50.h Normal file
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/*
* am335x_sl50.h
*
* Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_AM335X_EVM_H
#define __CONFIG_AM335X_EVM_H
#include <configs/ti_am335x_common.h>
#undef CONFIG_BOOTDELAY
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_FIT
# define CONFIG_FIT
#endif
# define CONFIG_TIMESTAMP
# define CONFIG_LZO
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/*#define CONFIG_MACH_TYPE 3589 Until the next sync */
#define CONFIG_BOARD_LATE_INIT
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x80000000\0" \
"pxefile_addr_r=0x80100000\0" \
"kernel_addr_r=0x82000000\0" \
"fdt_addr_r=0x88000000\0" \
"ramdisk_addr_r=0x88080000\0" \
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1)
#define AM335XX_BOARD_FDTFILE \
"fdtfile=am335x-sl50.dtb\0" \
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
AM335XX_BOARD_FDTFILE \
MEM_LAYOUT_ENV_SETTINGS \
BOOTENV
#endif
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* PMIC support */
#define CONFIG_POWER_TPS65217
#define CONFIG_POWER_TPS65910
/* SPL */
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
/* Bootcount using the RTC block */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_AM33XX
#define CONFIG_SYS_BOOTCOUNT_BE
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifndef CONFIG_SPL_USBETH_SUPPORT
/* To support eMMC booting */
#define CONFIG_STORAGE_EMMC
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* Remove other SPL modes. */
#undef CONFIG_SPL_YMODEM_SUPPORT
#undef CONFIG_SPL_NAND_SUPPORT
#undef CONFIG_SPL_MMC_SUPPORT
#define CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_IS_IN_NAND
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
/* disable EFI partitions and partition UUID support */
#undef CONFIG_PARTITION_UUIDS
#undef CONFIG_EFI_PARTITION
/* General network SPL */
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#endif
#if defined(CONFIG_EMMC_BOOT)
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#endif
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_AM335X_SL50_H */