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arm, imx: add some gpr register defines
add some missing gpr register defines. Signed-off-by: Heiko Schocher <hs@denx.de>
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1 changed files with 35 additions and 0 deletions
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@ -413,10 +413,37 @@ struct src {
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};
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/* GPR1 bitfields */
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#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
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#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
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#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
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#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
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#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
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#define IOMUXC_GPR1_DPI_OFF BIT(24)
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#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
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#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
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#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
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#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
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#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
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#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
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#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
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#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
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#define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
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#define IOMUXC_GPR1_PCIE_INT BIT(14)
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#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
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#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
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#define IOMUXC_GPR1_GINT BIT(12)
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#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
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#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
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#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
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#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
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#define IOMUXC_GPR1_ACT_CS3 BIT(9)
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#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
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#define IOMUXC_GPR1_ACT_CS2 BIT(6)
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#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
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#define IOMUXC_GPR1_ACT_CS1 BIT(3)
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#define IOMUXC_GPR1_ADDRS0_OFFSET (1)
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#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
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#define IOMUXC_GPR1_ACT_CS0 BIT(0)
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/* GPR3 bitfields */
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#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
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@ -465,6 +492,14 @@ struct src {
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#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
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#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
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/* gpr12 bitfields */
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#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
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#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
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#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
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#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
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#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
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#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
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#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
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struct iomuxc {
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#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
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