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arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

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The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Dinh Nguyen 2015-11-02 17:11:21 -06:00 • committed by Marek Vasut
parent 96d59e9d6a
commit c624d07f3f
1 changed files with 3 additions and 3 deletions
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6
arch/arm/mach-socfpga/include/mach/reset_manager.h
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@ -69,9 +69,9 @@ struct socfpga_reset_manager {
#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
#define RSTMGR_QSPI RSTMGR_DEFINE(0, 5)
#define RSTMGR_SDMMC RSTMGR_DEFINE(0, 22)
#define RSTMGR_DMA RSTMGR_DEFINE(0, 28)
#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
/* Create a human-readable reference to SoCFPGA reset. */