We should load images to their destination, not their entry point.
Fixes: 7b86cd4274 ("imx8: support parsing i.MX8 Container file")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Implement the 'getprisec' subcommand of 'bmode' command for i.MX8M by
reading out the ROM log events. This event is set by the BootROM if it
switched to the secondary copy due to primary copy being corrupted.
Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Signed-off-by: Marek Vasut <marex@denx.de>
In case of a secondary image boot from the user area of an eMMC device,
the correct offset must be calculated. The offset is fused in the fuse
IMG_CNTN_SET1_OFFSET of the i.MX8M Nano and Plus. The calculation of the
offset is described in the reference manual (IMX8MNRM Rev. 2, 07/2022
and IMX8MPRM Rev. 1, 06/2021):
The fuse IMG_CNTN_SET1_OFFSET (0x490[22:19]) is defined as follows:
* Secondary boot is disabled if fuse value is bigger than 10,
n = fuse value bigger than 10.
* n == 0: Offset = 4MB
* n == 2: Offset = 1MB
* Others & n <= 10 : Offset = 1MB*2^n
Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Factor out parsing of ROM log in function spl_mmc_emmc_boot_partition().
This can be helpful to detect a secondary image boot without fiddling
around with MMC partitions. This way for example, U-Boot is able to
detect a secondary image boot and can enter some fallback scenario like
starting a recovery mode.
Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce two new weak functions, arch_spl_mmc_get_uboot_raw_sector() and
board_spl_mmc_get_uboot_raw_sector(), each of which can be overridden at
a matching level, that is arch/ and board/ , in addition to the existing
weak function spl_mmc_get_uboot_raw_sector().
This way, architecture code can define a default architecture specific
implementation of arch_spl_mmc_get_uboot_raw_sector(), while the board
code can override that using board_spl_mmc_get_uboot_raw_sector() which
takes precedence over the architecture code. In some sort of unlikely
special case where code has to take precedence over board code too, the
spl_mmc_get_uboot_raw_sector() is still left out to be a weak function,
but it should be unlikely that this is ever needed to be overridden.
Signed-off-by: Marek Vasut <marex@denx.de>
i.MX93 11x11 EVK fails to boot:
U-Boot SPL 2023.10-00558-g65b9b3462bec-dirty (Oct 03 2023 - 17:40:10 +0200)
SOC: 0xa0009300
LC: 0x40010
M33 prepare ok
Normal Boot
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Load image from 0x44400 by ROM_API
NOTICE: BL31: v2.8(release):android-13.0.0_2.0.0-0-ge4b2dbfa52f5
NOTICE: BL31: Built : 17:52:46, Sep 28 2023
That's because commit 9e644284ab ("dm: core: Report
bootph-pre-ram/sram node as pre-reloc after relocation"):
"[This] changes behavior of what nodes are bound in the U-Boot
proper pre-relocation phase. Change to bootph-all or add
bootph-some-ram prop to restore prior behavior."
Fix this by adding bootph-some-ram prop as suggested by the commit
above.
Fixes: 9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L
System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC
carrier board.
The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a
devicetree blob to the bootloader as an argument in the same was
previous R-Car gen3/gen4 SoCs. This blob contains a compatible string
which can be used to identify the particular SoC we are running on and
this is used to select the appropriate device tree to load.
The configuration renesas_rzg2l_smarc_defconfig is added to support
building for this target. In the future this defconfig will be extended
to support other SoCs and evaluation boards from the RZ/G2L family.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L
System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC
carrier board.
This patch is based on the corresponding Linux v6.5 device tree
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The memory map for the RZ/G2L family differs from that of previous R-Car
Gen3/Gen4 SoCs.
A high level memory map can be seen in figure 5.2 (section 5.2.1) of the
RZ/G2L data sheet rev 1.30 published May 12, 2023. A summary is included
here (note that this is a 34-bit address space):
* 0x0_0000_0000 - 0x0_0002_FFFF SRAM area
* 0x0_0003_0000 - 0x0_0FFF_FFFF Reserved area
* 0x0_1000_0000 - 0x0_1FFF_FFFF I/O register area
* 0x0_2000_0000 - 0x0_2FFF_FFFF SPI Multi area
* 0x0_3000_0000 - 0x0_3FFF_FFFF Reserved area
* 0x0_4000_0000 - 0x1_3FFF_FFFF DDR area (4 GiB)
* 0x1_4000_0000 - 0x3_FFFF_FFFF Reserved area
Within the DDR area, the first 128 MiB are reserved by TrustedFirmware.
The region from 0x43F00000 to 0x47DFFFFF inclusive is protected for use
in TrustedFirmware/OP-TEE, but all other memory is included in the
memory map. This reservation is the same as used in R-Car
Gen3/Gen4 and RZ/G2{H,M,N,E} SoCs.
DRAM information is initialised based on the data in the fdt.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a
devicetree blob to the bootloader as an argument in the same was
previous R-Car Gen3/Gen4 SoCs. This blob contains a compatible string
which can be used to identify the particular SoC we are running on.
We do this as reading the DEVID & PRR registers from u-boot is not
sufficient to differentiate between the R9A07G044L (RZ/G2L) and
R9A07G044C (RZ/G2LC) SoCs. An additional read from offset 0x11861178 is
needed but this address is in the OTP region which can only be read from
the secure world (i.e. TrustedFirmware). So we have to rely on
TrustedFirmware to determine the SoC and pass this information to u-boot
via an fdt blob.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
We don't want to rely on source files including <asm/types.h> before
<asm/arch/rmobile.h>.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add USB0 OTG support.
Currently, the USB0 OTG nodes are not enabled in the Linux kernel
devicetree.
For this reason, enable the USB0 OTG nodes inside imx8mp-evk-u-boot.dtsi
for now.
Also select several useful options such as USB gadget and fastboot.
Tested by running "ums 0 mmc 2".
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
The GPIO3 has to be available early during U-Boot proper start up for
DRAM size detect to work correctly. The GPIO3 is currently available in
SPL and late in U-Boot proper, which is insufficient. Add the missing
bootph-all to make the GPIO3 available also early in U-Boot proper.
Signed-off-by: Marek Vasut <marex@denx.de>
The xfi3 target has been removed by commit 539fba2c10 ("arm:
Remove xfi3 board"), but it missed to remove an entry from the
mxs Kconfig.
Remove it.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.
Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.
Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
SPDX-License tag is missing and checkpatch complains about it.
Add the SPDX-License tag using the same one from imx7d-sdb.dts.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
The current imx8mp-dhcom-som.dtsi describes production rev.200 SoM,
add DT overlay which reinstates rev.100 SoM description to permit
prototype rev.100 SoMs to be used until they get phased out.
Signed-off-by: Marek Vasut <marex@denx.de>
In case the i.MX8MP DHCOM rev.100 has been populated on the PDK3
carrier board, the on-SoM PHY PHYAD1 signal has been pulled high
by the carrier board and changed the PHY MDIO address from 5 to 7.
This has been fixed on production rev.200 SoM by additional buffer
on the SoM PHYAD/LED signals, remove the workaround.
Signed-off-by: Marek Vasut <marex@denx.de>
The current imx8mp-dhcom-som.dtsi describes prototype rev.100 SoM,
update the DT to describe production rev.200 SoM which brings the
following changes:
- Fast SoC GPIOs exposed on the SoM edge connector
- Slow GPIOs like component resets moved to I2C GPIO expander
- ADC upgraded from TLA2024 to ADS1015 with conversion interrupt
- EEPROM size increased from 256 B to 4 kiB
Signed-off-by: Marek Vasut <marex@denx.de>
Add DT overlays to support additional DH i.MX8MP DHCOM SoM 660-100
population options with 1x or 2x RMII PHY mounted on PDK2 or PDK3
carrier boards.
Use SPL DTO support to apply matching SoM specific DTO to cater
for the SoM differences. Remove ad-hoc patching of control DT from
fdtdec_board_setup().
Signed-off-by: Marek Vasut <marex@denx.de>
The current code works by sheer coincidence, because (see HABv4 API
documentation, section 3.4) the RVT authenticate_image call updates
the size that is passed in with the actual size ROM code pulls from
IVT/CSF . So if the input size is larger, that is "fine" . Pass in
size instead to make this really correct.
Signed-off-by: Marek Vasut <marex@denx.de>
- Generally we just drop the #ifdef CONFIG_SYS_LONGHELP and endif lines
and use U_BOOT_LONGHELP to declare the same variable name as before
- In a few places, either rename the variable to follow convention or
introduce the variable as it was being done inline before.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver adds support for the gpio features of the GPIO/PFC module in
the Renesas RZ/G2L (R9A07G044) SoC.
The new `rzg2l-pfc-gpio` driver is bound to the same device tree node as
the `rzg2l-pfc-pinctrl` driver as the same hardware block provides both
GPIO and pin multiplexing features.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This driver adds support for the pinctrl features of the GPIO/PFC module
in the Renesas RZ/G2L (R9A07G044) SoC.
A multi-function `rzg2l-pfc` driver is defined for UCLASS_NOP, which
binds the `rzg2l-pfc-pinctrl` UCLASS_PINCTRL driver dynamically. We also
define common macros and functions for the PFC in <renesas/rzg2l-pfc.h>.
This makes it easy to add an additional UCLASS_GPIO driver for the GPIO
functionality of this module in a follow-up patch.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The RZ/G2L family uses CONFIG_RCAR_64 but does not share a common PFC
driver with the R-Car gen3 & gen4 boards.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This driver provides clock and reset control for the Renesas R9A07G044L
(RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:
* driver code which is applicable to all SoCs in the RZ/G2L family.
* static data describing the clocks and resets which are specific to the
R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter)
is used to indicate that both SoCs are supported.
clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.
The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add a config option for the R9A07G044L SoC used in the RZ/G2L so that we
can make use of this in the subsequent driver patches.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The Renesas RZ/G2L family includes the following ARM SoCs:
* RZ/G2L (r9a07g044l)
* RZ/G2LC (r9a07g044c)
* RZ/G2UL (r9a07g043u)
* RZ/V2L (r9a07g054l)
Support for individual SoCs and evaluation boards will be added in
separate patches.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
When CLK is enabled, get_lpuart_clk_rate() needs to get a per clock of
lpuart, so that add a per clock for lpuart1.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
The USB_PWR signal operation is not reliable on this DWC3 controller
instance in case the signal is active high. Switch to GPIO control,
which always behaves correctly. Perform the change in u-boot extras
until this hits Linux upstream.
Signed-off-by: Marek Vasut <marex@denx.de>
This reverts commit 5c1c6b7306. The reason
for switching to i2c-gpio was due to an issue we were seeing in the
Linux kernel where the CPU would lock up on certain adverse I2C bus
conditions. We were never able to reproduce the lockup in U-Boot but
assumed that was probably just luck.
Since then we have discovered that the lock up was due to the I2C
transaction offload engine in the I2C controller not coping with the
adverse bus conditions (basically it thinks there's another master and
waits for a STOP condition that never comes). U-Boot doesn't use the I2C
offload feature so is not susceptible to the lockup.
We can therefore safely return to using the built-in I2C controller.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
ZyXEL NSA325 specifications:
Marvell Kirkwood 88F6282 SoC
1.6 GHz CPU
1x GBE LAN port (Marvell MV88E1318)
512 MB RAM
128 MB Eon NAND, SLC
I2C
1x USB 3.0 (on PCIe bus)
2x USB 2.0
2x SATA (hot swap slots)
Serial console
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The cn9130.dtsi defines a pinctrl node for SPI1 (until recently it was
mislabeled as spi0). Use this instead of having a duplicate definition
with a different label.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The CN9130-DB uses the SPI1 interface but had the pinctrl node labelled
as "cp0_spi0_pins". Use the label "cp0_spi1_pins" and update the node
name to "cp0-spi-pins-1" to avoid confusion with the pinctrl options for
SPI0.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Extend the padding process of u-boot-nand.imx target by adding 10k bytes
of zeros to the end of the binary using the 'dd' command.
The existing padding method did not generate a functional binary,
as discussed in more detail in this thread [1]. Instead, we adopt the
end-padding calculation method documented in 'board/doc/colibri_imx7.rst'
as a reference, which is relevant for iMX7 with NAND storage.
Adding 10k bytes of zeros provides an approximate value that makes the
proper padding for these NAND devices.
[1] https://lore.kernel.org/all/CAC4tdFUqffQzRQFv5AGe_xtbFy1agr2SEpn_FzEdexhwjdryyw@mail.gmail.com/
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
These IS_ENABLED(CONFIG_SPL_LOAD_FIT) cases can no longer be reached,
and thus get_fit_image_size() is also redundant.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Currently, spl_imx_romapi uses a somewhat tricky workaround for the
fact that a FIT image with external data doesn't directly allow one to
know the full size of the file: It does a dummy spl_load_simple_fit(),
having the ->read callback remember the largest offset requested, and
then does a last call to rom_api_download_image() to fetch the
remaining part of the full FIT image.
We can avoid that by just keeping track of how much we have downloaded
already, and if the ->read() requests something outside the current
valid buffer, fetch up to the end of the current request.
The current method also suffers from not working when CONFIG_IMX_HAB
is enabled: While in that case u-boot.itb is not built with external
data, so the fdt header does contain the full size of the dtb
structure. However, it does not account for the extra CONFIG_CSF_SIZE
added by board_spl_fit_size_align(). And also, the data it hands out
during the first dummy spl_load_simple_fit() is of course garbage, and
wouldn't pass the verification.
So we really need to call spl_load_simple_fit() only once, let that
figure out just how big the FIT image is (including whatever data, CSF
or "ordinary" external data, has been tacked on beyond the fdt
structure), and always provide valid data from the ->read callback.
This only affects the CONFIG_SPL_LOAD_FIT case - I don't have any
hardware or experience with the CONFIG_SPL_LOAD_IMX_CONTAINER case, so
I leave that alone for now.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The hab signing script doc/imx/habv4/csf_examples/mx8m/csf.sh does
fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset
to figure out the offset of u-boot.itb inside flash.bin. That works
fine for imx8mm, imx8mn, imx8mq, but fails for imx8mp because in that
case 'uboot' is merely a label and not actually the node name.
Homogenize these cases and make imx8mp the same as the other imx8m*
variants. The binman type is explicitly given and no longer derived
from the node name, and the csf.sh script will work for all four SOCs.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
If optee is detected configure it in the Linux device-tree:
- add /firmware/optee node
- add /reserved-memory nodes for optee_core and optee_shm
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Move the crypto and sec_jr* nodes from board-specific
u-boot.dtsi files into the common files. Additionally protect the
nodes with ifdef CONFIG_FSL_CAAM as they don't serve any purpose if
that is not enabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
There is no need to include the firmware/optee node if the optee
driver is not enabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Move the firmware/optee node to the common imx8mp-u-boot.dtsi and
protect it with an ifdef CONFIG_OPTEE as it is a meaningless node
without the optee driver enabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Move the firmware/optee node to the common imx8mm-u-boot.dtsi and
protect it with an ifdef CONFIG_OPTEE as it is a meaningless node
without the optee driver enabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Enable USB SDP SPL aka serial downloader recovery mode support.
While at it also enable fastboot support which may be used to
subsequently load further stages like a Toradex Easy Installer FIT
image.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Update the imx8mp-venice-gw74xx for revB:
- add CAN1
- add TIS-TPM on SPI2
- add FAN controller
- fix PMIC I2C bus (revA PMIC I2C was non-functional so no need for
backward compatible option)
- M2 socket GPIO's moved
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks imx8mm-venice-gw7905-0x consists of a SOM + baseboard.
The GW700x SOM contains the following:
- i.MX8M Mini SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- RGMII PHY
- PMIC
- SOM connector providing:
- FEC GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 2.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW7905 Baseboard contains the following:
- GPS
- microSD
- off-board I/O connector with I2C, SPI, GPIO
- EERPOM
- PCIe clock generator
- 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
- 1x half-length miniPCIe socket with USB2.0 and USB3.0
- USB 3.0 HUB
- USB Type-C with USB PD Sink capability and peripheral support
- USB Type-C with USB 3.0 host support
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks imx8mp-venice-gw73xx-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW73xx Baseboard contains the following:
- 1x RJ45 GbE (eQoS from SOM)
- 1x RJ45 GbE (PCI)
- off-board I/O connector with MIPI-CSI (3-lane), MIPI-DSI (4-lane),
- off-board I/O connector with RS232/RS485
- off-board I/O connector with SPI
- off-board I/O connector with I2C, UART, and GPIO
I2C, I2S and GPIO
- microSD (1.8V/3.3V)
- GPS
- Accelerometer
- EERPOM
- USB 3.0 Hub
- Front Panel bi-color LED
- re-chargeable battery (for RTC)
- PCIe clock generator
- PCIe switch
- on-board 802.11abgnac 1x1 WiFi and Bluetooth 5.2
- 1x USB Type-A host socket with USB 3.0 support
- 1x USB OTG with USB 2.0 support
- 2x MiniPCIe socket with PCI and USB 2.0
- 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
- Wide range DC input supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks imx8mp-venice-gw72xx-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW72xx Baseboard contains the following:
- 1x RJ45 GbE (eQoS from SOM)
- 1x RJ45 GbE (PCI)
- off-board I/O connector with MIPI-CSI (3-lane), MIPI-DSI (4-lane),
- off-board I/O connector with RS232/RS485
- off-board I/O connector with SPI
- off-board I/O connector with I2C, UART, and GPIO
I2C, I2S and GPIO
- microSD (1.8V/3.3V)
- GPS
- Accelerometer
- EERPOM
- USB 3.0 Hub
- Front Panel bi-color LED
- re-chargeable battery (for RTC)
- PCIe clock generator
- PCIe switch
- 1x USB Type-A host socket with USB 3.0 support
- 1x USB OTG with USB 2.0 support
- 1x MiniPCIe socket with PCI and USB 2.0
- 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
- Wide range DC input supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Linux microPlatform uses an rngb device in optee-os in boot scheme
SPL -> OPTEE -> U-Boot. To make rngb available for optee-os, enable
it in SPL.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
With enabled SKIP_LOWLEVEL_INIT, the weak function timer_init() is
used in the SPL build. For iMX6 SoC, this leads MMC to fail once
u-boot proper is booted due to a timing issue.
Always use iMX-specific timer_init() in SPL to fix timing issues.
Fixes: be277c3a89 ("imx: mx7: avoid some initialization if low level is skipped")
Signed-off-by: Michael Scott <mike@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Now we have to use UCLASS_SM driver instead of
raw smc_call() function call.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230921081346.22157-9-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
The common.h header should always be first, followed
by other headers in order, then headers with directories,
then local files.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230921081346.22157-8-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
A follow-up to commit 842fb5de42
("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer")
and commit 320a1938b6
("drivers: use devfdt_get_addr_index_ptr when cast to pointer").
In addition to using the *_ptr variants of these functions where the
address is cast to a pointer, this also changes devfdt_get_addr_*() to
dev_read_addr_*() in a few places. Some variable and field types are
changed from fdt_addr_t or phys_addr_t to void* where the cast was
happening later.
This patch fixes a number of compile warnings when building a 32bit
U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error
handling where the return value of dev_read_addr() etc. was checked for
NULL instead of FDT_ADDR_T_NONE.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
clk:
- remove additional compatible strings for Versal NET
net:
- zynq_gem: Fix clock calculation for MDC for higher frequencies
pinctrl:
- core: Extend pinmux status buffere size
- zynqmp driver: Show also tristate configuration
test:
- add test case for pxe get
Xilinx:
- describe SelectMAP boot mode
Zynq:
- Fix nand description in DT
ZynqMP:
- DTS sync patches with kernel and also W=1 related fixes
- Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
description for other SC based boards
- k24 psu_init cleanup
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Merge tag 'xilinx-for-v2024.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.01-rc1 v3
clk:
- remove additional compatible strings for Versal NET
net:
- zynq_gem: Fix clock calculation for MDC for higher frequencies
pinctrl:
- core: Extend pinmux status buffere size
- zynqmp driver: Show also tristate configuration
test:
- add test case for pxe get
Xilinx:
- describe SelectMAP boot mode
Zynq:
- Fix nand description in DT
ZynqMP:
- DTS sync patches with kernel and also W=1 related fixes
- Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
description for other SC based boards
- k24 psu_init cleanup
Make that condition more generic by checking if the memory controller
driver is enabled instead of using the EVM's config.
Signed-off-by: Dominik Haller <d.haller@phytec.de>
The following commit syncs the device tree from Linux tag
v6.6-rc1 to U-boot and fixes the following to be compatible with
the future syncs -
- Include k3-am68-sk-base-board.dts file
Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
include k3-am68-sk-base-board.dts for Linux fixes to propagate
to U-boot.
- Fixing the mcu_timer0
Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi
- Fixing secure proxy nodes
Linux DT now have these nodes defined so remove them and rename to
use the Linux DT ones.
- Remove cpsw node
The compatible is now fixed and the node is not required in
-u-boot specifically
- Remove aliases and chosen node
Use these from Linux and don't override when not required.
- Remove /delete-property/ from sdhci nodes
We have the necessary clock and dev data so remove these.
- Remove dummy_clocks and fs_loader0
These weren't being used anywhere so remove it.
- Remove mcu_ringacc override
All these have been put in a single commit to not break the
bisectability.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
The following commit syncs the device tree from Linux tag
v6.6-rc1 to U-boot and fixes the following to be compatible with
the future syncs -
- Include k3-j721s2-common-proc-board.dts file
Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
include k3-j721s2-common-proc-board.dts for Linux fixes to propagate
to U-boot.
- Fixing the mcu_timer0
Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi
- Fixing secure proxy nodes
Linux DT now have these nodes defined so remove them and rename to
use the Linux DT ones.
- Remove cpsw node
The compatible is now fixed and the node is not required in
-u-boot specifically
- Remove aliases and chosen node
Use these from Linux and don't override when not required.
- Remove /delete-property/ from sdhci nodes
We have the necessary clock and dev data so remove these.
- Remove dummy_clocks and fs_loader0
These weren't being used anywhere so remove it.
- Remove mcu_ringacc override
All these have been put in a single commit to not break the
bisectability.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
mcu_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices lsit so it an be enabled via the k3 power controller.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
The update causes instability in am68-sk boards so revert the patch in
the meantime till fix is available.
This reverts commit f1edf4bb6a.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Sync j7200 dts with Linux 6.6-rc1
- k3-j7200-r5-common-proc-board.dts now inherits from
k3-j7200-common-proc-board.dts instead of k3-j7200-som-p0.dtsi. This
allows us to trim down the r5 file considerably by using existing
properties
- remove pimux nodes from r5 file
- remove duplicate nodes & node properties from r5/u-boot files
- mcu_timer0 now used instead of timer1
mcu_timer0 device id added to dev-data.c file in order to work
- remove cpsw node
This node is no longer required since the compatible is now fixed
- remove dummy_clock_19_2_mhz
This node wasn't being used anyhere, so it was removed
- remove dummy_clock_200mhz
main_sdhci0 & main_sdhci1 no longer need dummy clock for eMMC/SD
- fix secure proxy node
mcu_secproxy changed to used secure_prxy_mcu which is already
defined in k3-j7200-mcu-wakeup.dtsi
- removed &mcu_ringacc property override since they're present in
v6.6-rc1
Signed-off-by: Reid Tonking <reidt@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
mcu_timer0 is now used as the tick timer in u-boot, so this adds the
timer to the soc device list so it can be enabled via the k3 power
controller.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
ao-secure node can be used to get information about the board,
so, for example, using show_board_info() we can get following
information for board with Meson A1 SoC:
SoC: Amlogic Meson A1 (A113L) Revision 2c:a (1:a)
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Link: https://lore.kernel.org/r/20231010100623.74475-3-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This patch adds basic clock driver for Amlogic A1 Family which supports
enabling/disabling some gates, getting frequencies and setting rate
with limited reparenting.
Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230925155209.130671-3-ivprusov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
All K3 boards now are secure by default, instead of setting this in each
defconfig, make it implied by the ARCH config.
The only exception is IOT2050, which I do not believe will have any
problems with being a TI_SECURE_DEVICE, but for now turn it off to keep
its config the same.
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
As the code to switch an ARM core from secure to the non-secure state
needs to know the base address of the Generic Interrupt Controller
(GIC), we read an Arm Cortex defined system register that is supposed to
hold that base address. However there are SoCs out there that get this
wrong, and this CBAR register either reads as 0 or points to the wrong
address. To accommodate those systems, so far we use a macro defined in
some platform specific header files, for affected boards.
To simplify future extensions, replace that macro with a Kconfig variable
that holds this override address, and define a default value for SoCs
that need it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.
Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.
Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.
Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Apple's M2 Ultra SoC are somewhat similar to the M1 Ultra but needs
a tweaked memory map as the M2 Pro/Max SoCs. USB, NVMe, UART, WDT
and PCIe are working with the existing drivers.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
system registers, that provide 64 bits worth of randomness on every
read. Since it's an extension, and implementing it is optional, there is
a field in the ID_AA64ISAR0_EL1 ID register to query the availability
of those registers.
Add a UCLASS_RNG driver that returns entropy via repeated reads from
those system registers, if the extension is implemented.
The driver always binds, but checks the availability in the probe()
routine.
This helps systems which suffer from low boot entropy, since U-Boot can
provide entropy via the generic UEFI entropy gathering protocol to the OS,
at an early stage.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
A53 U-Boot proper got broken because nodes marked as 'bootph-pre-ram'
are no longer available in U-Boot proper before relocation.
Fix this by marking all nodes in u-boot.dtsi as 'bootph-all'.
Fixes: 9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Since commit 9e644284ab ("dm: core: Report bootph-pre-ram/sram node
as pre-reloc after relocation") A53 u-boot proper is broken. This is
because nodes marked as 'bootph-pre-ram' are not available at u-boot
proper before relocation.
To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.
Fixes: 69b19ca67b ("arm: dts: k3-j721e: Sync with v6.6-rc1")
Cc: Neha Francis <n-francis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Tom Rini <trini@konsulko.com> # J721E-EVM GP
Tested-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
This is now done using binman but this file was leftover and is now
unused, remove it.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Since commit 9e644284ab ("dm: core: Report bootph-pre-ram/sram node
as pre-reloc after relocation") A53 u-boot proper is broken. This is
because nodes marked as 'bootph-pre-ram' are not available at u-boot
proper before relocation.
To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Some functions are not used outside this file, so make them static.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. Drop support
for it.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Use uintptr_t instead of phys_addr_t where appropriate, so passing the
addresses to writel() doesn't result in compile warnings when PHYS_64BIT
is set for 32bit builds (which is actually a useful configuration, as
the K3 SoC family boots from an R5 SPL, which may pass bank information
based on gd->bd->bi_dram to fdt_fixup_memory_banks() etc., so PHYS_64BIT
is needed for fixing up the upper bank).
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
- None of the callers perform error checking and based on the non-empty
versions of this function, there's no checking to be done, so make
this a void.
- Add a default weak version of the function.
- Remove the empty versions of exynos_init now that we have a weak
version.
Signed-off-by: Tom Rini <trini@konsulko.com>
The SelectMAP configuration interface provides an 8-bit,
16-bit or 32-bit bidirectional data bus interface to the Versal FPGA
configuration logic that can be used for both configuration and readback.
A connected microcontoller to the SelectMAP interface can load boot
image with bitstream, TF-A (ARM Trusted Firmware) and U-Boot.
This commit adds the missing identification of the SelectMAP mode.
Signed-off-by: Polak, Leszek <LPolak@arri.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/DU0PR07MB8419F7765892CDBCE7D559C5C8CFA@DU0PR07MB8419.eurprd07.prod.outlook.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.
MIO configuration is also shared with zcu111.
The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3b296ef0f52bd94e32bdeb6d1beee29ac85f00a2.1695808407.git.michal.simek@amd.com
VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.
The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/59d3b1f7e785bc65518b465e5122fd2787616a93.1695808407.git.michal.simek@amd.com
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs with only DT overlays to cover different i2c
structures.
All MIOs are fixed by the spec that's why not a problem to description
pinctrl setting.
Apart from eth phy reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).
NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).
i2c structure on Xilinx Versal evaluation platforms contain a lot of
devices but also connection to connectors like SFP. Because of this
complicated structure with also all level shifters, i2c muxes, etc. not all
devices are able to reliably work on 400kHz even if they are compatible
with this speed. That's why set i2c frequency to 100KHz to increase
reliability of the i2c bus.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8092340f92144f0cc9096194198f227015bc013.1695808407.git.michal.simek@amd.com
Linux requires to describe nand structure under nand controller.
If it is not described nand device is not detected by Linux.
Error shown by Linux kernel:
pl35x-nand-controller e1000000.nand-controller: Incorrect number of NAND chips (0)
pl35x-nand-controller: probe of e1000000.nand-controller failed with error -22
When wired:
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
nand: Micron MT29F2G08ABAEAWP
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3fcd68ccdfed5e6c079681e3b29e06583ec8a375.1695378830.git.michal.simek@amd.com
The DPSUB DT bindings now specify ports to model the connections with
the programmable logic and the DisplayPort output. Add them to the
device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1c91420e90bc823d7529834c33438216857c7161.1695378830.git.michal.simek@amd.com
Some boards are using one mdio bus which holds multiple phys and also
boards are using mdio node for bus description. That's why there are cases
where address/size-cells are unnecessary which is also reported by make W=1
dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle
it based on used description.
Error log:
/axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without
"ranges" or child "reg" property
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/02f308c774d4f2a798a9a8c066824114a19841a7.1695378830.git.michal.simek@amd.com
All zynqmp boards have been already described via mdio node that's why also
convert the rest of the boards. With using mdio node there is an option to
add reset property for the whole mdio bus which is reflected by
's/phy-reset-gpios/reset-gpios/g' for some boards.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.simek@amd.com
- Add Board: rk3568 Bananapi R2Pro;
- Update pcie bifurcation support;
- dwc_eth_qos controller support for rk3568 and rk3588;
- Compressed binary support for U-Boot on rockchip platform;
- dts and config updates for different board and soc;
[ trini: Fix conflict on include/spl.h ]
Signed-off-by: Tom Rini <trini@konsulko.com>
A RK8XX PMIC is typically using i2c0 on RK356x devices. Add bootph-all
to required pinctrl nodes to simplify use of the prevent booting on
power plug-in option in SPL.
With the following Kconfig options and nodes in u-boot.dtsi the prevent
booting on power plug-in option can work in SPL.
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_PMIC_RK8XX=y
&i2c0 {
bootph-pre-ram;
};
&rk817 {
bootph-pre-ram;
regulators {
bootph-pre-ram;
};
};
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync the device tree for RK3588 series with Linux 6.6-rc1.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Bananapi R2 Pro board.
tested:
- sdcard
- both front usb-ports
- sata
- wan-port
lan-ports are connected to mt7531 switch where driver needs to be
separated from mtk ethernet-driver.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Add support for generating a LZMA-compressed U-boot binary with the
help of binman, if CONFIG_SPL_LZMA is selected.
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for generating a GZIP-compressed U-boot binary with the
help of binman, if CONFIG_SPL_GZIP is selected.
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There is no support to initialize DRAM on rk3308 SoC using U-Boot
TPL or SPL, and therefore an external TPL binary must be used to
package a bootable u-boot-rockchip.bin image.
Default ROCKCHIP_EXTERNAL_TPL to yes if ROCKCHIP_RK3308.
Remove useless TPL_SERIAL.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a minimal generic RK3566/RK3568 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3566/RK3568 boards that follow reference board design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable missing PCIe Kconfig options now that PCIe bifurcation is fixed
to make use of the two on-board RTL8125B and the M.2 slot on NanoPi R5C
and NanoPi R5S.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update and sync Kconfig options for NanoPi R5C and NanoPi R5S with other
RK3568 boards.
SPL_FIT_SIGNATURE is enabled to add a checksum validation of the FIT
payload, also add LEGACY_IMAGE_FORMAT to keep boot scripts working.
OF_SPL_REMOVE_PROPS, SPL_DM_SEQ_ALIAS and SPL_PINCTRL change ensure
pinctrl for eMMC, SD-card and UART2 is applied in SPL.
MMC_HS200_SUPPORT and SPL counterpart is enabled to speed up eMMC load
times from on-board eMMC 5.1 modules.
Drop remaining unused or unsupported options to sync with other RK3568
boards.
Also sync device tree from linux v6.4 and drop u-boot,spl-boot-order and
use the default from rk356x-u-boot.dtsi.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Use the new SPL/TPL/VPL_SYS_MALLOC_F symbols to determine whether the
malloc pool exists.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Enable CONFIG_TPL_SYS_MALLOC_F for boards which have a non-zero value
for CONFIG_TPL_SYS_MALLOC_F_LEN
Note that the default is yes in most cases, so no changes are needed to
board defconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable CONFIG_SPL_SYS_MALLOC_F for boards which have a non-zero value
for CONFIG_SPL_SYS_MALLOC_F_LEN
Note that the default is yes in most cases, so no changes are needed to
board defconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rename this so that SPL is first, as per U-Boot convention. Also add
PAYLOAD_ since this is where in memory the parameters for the payload
have been stored.
Signed-off-by: Simon Glass <sjg@chromium.org>
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Sync k3-j721e DTS with kernel.org v6.6-rc1.
* Use mcu_timer0 defined in k3-j721e-mcu-wakeup.dtsi and remove
timer0, we have its clocks set up in clk-data now
* Remove hbmc node as support is buggy and needs to be fixed
* Remove aliases and chosen node, use them from Kernel
* Remove /delete-property/ and clock-frequency from sdhci,
usbss, and mcu_uart nodes as we have them in clk and dev data
* Remove dummy_clocks as they are not needed
* Remove cpsw node as it is not required since it has been fixed
in U-Boot
* Remove pcie nodes, they are not needed
* Remove mcu_i2c0 as it is used for tps659413 PMIC in j721e-sk
for which support is not yet added
* Change secproxy nodes to their Linux definitions
* Remove overriding of ti,cluster-mode in MAIN R5 to default to
lockstep mode same as Kernel
* Retain tps6594 node as TPS6594 PMIC support is still under
review in the Kernel [1], cleanup will be taken post its merge
[1] https://lore.kernel.org/all/20230810-tps6594-v6-0-2b2e2399e2ef@ti.com/
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Get rid of k3-j721e-r5-*-u-boot.dtsi as it is not
necessary. Change the inclusion hierarchy to be as follows:
k3-j721e-<board>.dts---
-
-->k3-j721e-r5-<board>.dts
-
k3-j721e-<board>-u-boot.dtsi---
Reason for explicitly mentioning the inclusion of -u-boot.dtsi in code
although it could've been automatically done by U-Boot is to resolve
some of the dependencies that R5 file requires.
Also remove duplicate phandles while making this shift as well as remove
firmware-loader as it serves no purpose without "phandlepart" property.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
When setting boot media to load the TIFS binary in legacy boot flow
(followed by J721E), get_timer() is called which eventually calls
dm_timer_init() to grab the tick-timer, which is mcu_timer0. Since we
need to set up the clocks before using the timer, move clk_k3 driver
probe before k3_sysfw_loader to ensure we have all necessary clocks set
up before.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
U-Boot uses mcu_timer0 as the tick-timer, so add it to device list.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since commit [1] A53 u-boot proper is broken. This is because nodes
marked as 'bootph-pre-ram' are not available at u-boot proper before
relocation.
To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Reported-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
CPSW node needs PHY, MDIO, pinmux, DMA and INTC nodes.
Mark them as 'bootph-all' so they are available in all
pre-relocation phases.
Fixes below dts warnings:
<stdout>: Warning (reg_format): /bus@f4000/ethernet@8000000/mdio@f00/ethernet-phy@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
<stdout>: Warning (unit_address_vs_reg): /bus@f4000/ethernet@8000000/mdio@f00: node has a unit name, but no reg or ranges property
<stdout>: Warning (pci_device_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
<stdout>: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (avoid_default_addr_size): /bus@f4000/ethernet@8000000/mdio@f00/ethernet-phy@1: Relying on default #address-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f4000/ethernet@8000000/mdio@f00/ethernet-phy@1: Relying on default #size-cells value
<stdout>: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size'
<stdout>: Warning (unique_unit_address): Failed prerequisite 'avoid_default_addr_size'
<stdout>: Warning (msi_parent_property): /bus@f4000/bus@48000000/dma-controller@485c0100:msi-parent: Could not get phandle node for (cell 0)
<stdout>: Warning (msi_parent_property): /bus@f4000/bus@48000000/dma-controller@485c0000:msi-parent: Could not get phandle node for (cell 0)
<stdout>: Warning (phys_property): /bus@f4000/ethernet@8000000/ethernet-ports/port@2:phys: Could not get phandle node for (cell 0)
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
Move cbass_mcu node to -r5-sk.dts as it is only required
for R5 SPL.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
CPSW node needs PHY, MDIO, pinmux, DMA and INTC nodes.
USB and MMC nodes need pinmux.
Mark them as 'bootph-all' so they are available in all
pre-relocation phases.
Fixes below dts warning:
<stdout>: Warning (dmas_property): /bus@f4000/ethernet@8000000:dmas: Could not get phandle node for (cell 0)
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
Move vtt_supply and cbass_mcu node to -r5-evm.dts as
it is only required for R5 SPL.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
_ alignment with kernel DT v6.5 for stm32f429 and stm32f746
_ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco
STM32 MPU:
_ alignment with kernel DT v6.6-rc1
_ add RNG support for stm32mp13
_ add USB, USB boot and stm32prog command support for stm32mp13
_ add support of USART1 clock for stm32mp1
_ only print RAM and board code with SPL_DISPLAY_PRINT flag for
stm32mp1
_ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc
for stm32mp15xx DHCOR
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Merge tag 'u-boot-stm32-20231004' of https://source.denx.de/u-boot/custodians/u-boot-stm
STM32 MCU:
_ alignment with kernel DT v6.5 for stm32f429 and stm32f746
_ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco
STM32 MPU:
_ alignment with kernel DT v6.6-rc1
_ add RNG support for stm32mp13
_ add USB, USB boot and stm32prog command support for stm32mp13
_ add support of USART1 clock for stm32mp1
_ only print RAM and board code with SPL_DISPLAY_PRINT flag for
stm32mp1
_ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc
for stm32mp15xx DHCOR
[ Fix merge conflict at board/st/common/stm32mp_dfu.c ]
Signed-off-by: Tom Rini <trini@konsulko.com>
stm32mp135f-dk board has a type-c connector to retrieve the connection
state. For now, simply force an active peripheral mode in u-boot for
flashing.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Device tree alignment with Linux kernel v6.6.rc1.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
commit 6b443faa313c519db755ff90be32758fd9c66453 Linux upstream.
This is a preparation patch for the upcoming support to manage CAN
peripherals in single configuration.
The addition ensures backwards compatibility.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230427204540.3126234-3-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 559a6e75b4bcf0fc9e41d34865e72cf742f67d8e Linux upstream.
Add pin configurations for using CAN controller on stm32f469-disco
board. They are located on the Arduino compatible connector CN5 (CAN1)
and on the extension connector CN12 (CAN2).
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230328073328.3949796-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 7355ad1950f41e755e6dc451834be3b94f82acd4 Linux upstream.
Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The
chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary,
that share some of the required logic like clock and filters. This means
that the secondary CAN can't be used without the primary CAN.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230328073328.3949796-4-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The patch applies the changes from Linux commit 10a970bc3ebfa ("ARM: dts:
stm32: support display on stm32f746-disco board") and removes the same
settings from stm32f746-disco-u-boot.dtsi.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit e4e724099f04072053cf411456e3e9aae48c4af1 Linux upstream.
In the schematics of document UM1907, the power supply for the micro SD
card is the same 3v3 voltage that is used to power other devices on the
board. By generalizing the name of the voltage regulator, it can be
referenced by other nodes in the device tree without creating
misunderstandings.
This patch is preparatory for future developments.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The patch applies the changes from Linux commit 008ef8b3a1a00 ("Add LTDC
(Lcd-tft Display Controller) support") and removes the same settings
from stm32f746-disco-u-boot.dtsi.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit f0215440069c4fb12958d2d321e05faa2708a11d Linux upstream.
The patch adds support for touchscreen on the stm32f746-disco board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 7a5f349e592c254f3c1ac34665b6c3905576efc2 Linux upstream.
The patch replaces the number 12 with the appropriate numerical constant
already defined in the file stm32f7-rcc.h.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 0920ccdf41e3078a4dd2567eb905ea154bc826e6 Linux upstream.
Add support for bxcan (Basic eXtended CAN controller) to STM32F746. The
chip contains three CAN peripherals, CAN1 and CAN2 in dual peripheral
configuration and CAN3 in single peripheral configuration:
- Dual CAN peripheral configuration:
* CAN1: Primary bxCAN for managing the communication between a secondary
bxCAN and the 512-byte SRAM memory.
* CAN2: Secondary bxCAN with no direct access to the SRAM memory.
This means that the two bxCAN cells share the 512-byte SRAM memory and
CAN2 can't be used without enabling CAN1.
- Single CAN peripheral configuration:
* CAN3: Primary bxCAN with dedicated Memory Access Controller unit and
512-byte SRAM memory.
-------------------------------------------------------------------------
| features | CAN1 | CAN2 | CAN 3 |
-------------------------------------------------------------------------
| SRAM | 512-byte shared between CAN1 & CAN2 | 512-byte |
-------------------------------------------------------------------------
| Filters | 26 filters shared between CAN1 & CAN2 | 14 filters |
-------------------------------------------------------------------------
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230427204540.3126234-6-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 011644249686f2675e142519cd59e81e04cfc231 Linux upstream.
Add pin configurations for using CAN controller on stm32f7.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230427204540.3126234-4-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Synchronize RZ R8A774E1 RZ/G2H DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize RZ R8A774C0 RZ/G2E DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize RZ R8A774B1 RZ/G2N DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize RZ R8A774A1 RZ/G2M DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Adam Ford <aford173@gmail.com>
Synchronize RZ R7S72100 RZ/A1 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A779G0 V4H DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A779F0 S4 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A779A0 E3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77995 D3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77990 E3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77980 V3H DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77970 V3M DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77965 M3-N DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77951 H3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A7794 E2 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A7790 H2 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ9031 PHYs on R-Car Gen3 Salvator-X boards. This allows software
to identify the PHY model at any time, regardless of the state of
the PHY reset line.
This is a fix for missed addition of these properties on Salvator-X
boards.
Ported from Linux kernel commit 722d55f3a9bd810f3a1a31916cc74e2915a994ce .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Commit 65cc0e2a65 ("global: Move remaining CONFIG_SYS_* to CFG_SYS_*")
renamed CONFIG_SYS_UBOOT_START to CFG_SYS_UBOOT_START. Unfortunately,
this meant that the value was no longer available to the Makefile. This
caused imxrt to fail to boot. All the other boards that used this
variable were unaffected because they were using the default value
which is CONFIG_TEXT_BASE.
This commit converts CFG_SYS_UBOOT_START to Kconfig and sets the default
value to CONFIG_TEXT_BASE.
Suggested-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
dm tree enhancement
adjust meaning of bootph-pre-ram/sram
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Merge tag 'dm-next-23sep23' of https://source.denx.de/u-boot/custodians/u-boot-dm into next
buildman file-keeping and build-progress improvements
dm tree enhancement
adjust meaning of bootph-pre-ram/sram
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h
Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
A '.update' extension does not get preserved by buildman, so change it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Michael Walle <michael@walle.cc>
Trying to boot a fitImage after a successful hab_auth_img operation
causes the following error:
## Loading kernel from FIT Image at 88000000 ...
Using 'conf-imx7d-smegw01.dtb' configuration
Trying 'kernel-1' kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: uncompressed
Data Start: 0x8800010c
Data Size: 9901752 Bytes = 9.4 MiB
Architecture: ARM
OS: Linux
Load Address: 0x80800000
Entry Point: 0x80800000
Hash algo: sha256
Hash value: 28f8779bbf010780f16dd3d84ecb9b604c44c5c2cf7acd098c264a2d3f68e969
Verifying Hash Integrity ... sha256Error in SEC deq
CAAM was not setup properly or it is faulty error!
The reason for this error is that the BootROM uses the CAAM Job Ring 0,
so disable its node in U-Boot to avoid the resource conflict.
imx8m dtsi files also have the Job Ring 0 disable since the following
kernel commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch?h=v6.5&id=dc9c1ceb555ff661e6fc1081434600771f29657c
For a temporary solution, disable the Job Ring 0 in imx7s-u-boot.dtsi.
Reported-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
The ivt_offset parameter is optional for both hab_auth_img_or_fail
and hab_auth_img commands.
Document it in their usage texts to make it clearer.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Since commit ea91031b22 ("imx: hab: extend hab_auth_img to calculate
ivt_offset"), it is possible to call the hab_auth_img command without the
last ivt_offset argument.
Currently, calling hab_auth_img_or_fail without the last
ivt_offset parameter causes a failure and the command usage text is shown.
Fix this problem by adjusting the argc logic to allow
calling hab_auth_img_or_fail with only the address and size parameters.
This way, both hab_auth_img and hab_auth_img_or_fail have the same
behavior with respect to the allowed number of command parameters.
Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
If CMD_ELF disabled and IMX_BOOTAUX enabled, the u-boot building ends
up with a linking error [1]. Select LIB_ELF to fix the building
issue.
[1]
ld: /tmp/ccaF1rpv.ltrans0.ltrans.o: in function `do_bootaux':
arch/arm/mach-imx/imx_bootaux.c:108: undefined reference to `valid_elf_image'
Fixes: c0f037f6a2 ("mach-imx: bootaux: elf firmware support")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Remember where these end up so that we can pass this information on to
the EFI layer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When CONFIG_CMD_USB and CONFIG_USB are disabled, still some compilation
errors are seen as below.
In file included from include/configs/xilinx_zynqmp.h:173,
from include/config.h:3,
from include/common.h:16,
from env/common.c:10:
include/config_distro_bootcmd.h:302:9: error: expected '}' before 'BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB'
302 | BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/config_distro_bootcmd.h:302:9: note: in definition of macro
'BOOTENV_DEV_NAME_USB'
302 | BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/configs/xilinx_zynqmp.h:77:41: note: in expansion of macro
'BOOTENV_DEV_NAME'
77 | # define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
func(USB, usb, 1)
| ^~~~
include/configs/xilinx_zynqmp.h:168:9: note: in expansion of macro
'BOOT_TARGET_DEVICES_USB'
168 | BOOT_TARGET_DEVICES_USB(func) \
| ^~~~~~~~~~~~~~~~~~~~~~~
include/config_distro_bootcmd.h:454:25: note: in expansion of macro
'BOOT_TARGET_DEVICES'
454 | "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0"
| ^~~~~~~~~~~~~~~~~~~
include/config_distro_bootcmd.h:474:9: note: in expansion of macro
'BOOTENV_BOOT_TARGETS'
474 | BOOTENV_BOOT_TARGETS \
| ^~~~~~~~~~~~~~~~~~~~
include/configs/xilinx_zynqmp.h:179:9: note: in expansion of macro
'BOOTENV'
179 | BOOTENV
| ^~~~~~~
include/env_default.h:120:9: note: in expansion of macro
'CFG_EXTRA_ENV_SETTINGS'
120 | CFG_EXTRA_ENV_SETTINGS
| ^~~~~~~~~~~~~~~~~~~~~~
In file included from env/common.c:32:
include/env_default.h:27:36: note: to match this '{'
27 | const char default_environment[] = {
| ^
scripts/Makefile.build:256: recipe for target 'env/common.o' failed
make[1]: *** [env/common.o] Error 1
Makefile:1853: recipe for target 'env' failed
make: *** [env] Error 2
make: *** Waiting for unfinished jobs....
Add CONFIG_USB_STORAGE as dependency for USB related macro's such as
BOOT_TARGET_DEVICES_USB() and DFU_DEFAULT_POLL_TIMEOUT and
CONFIG_THOR_RESET_OFF.
Remove CONFIG_ZYNQMP_USB from Kconfig and also from defconfig since it
is not used anywhere else.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230904031528.11817-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Correct the i2c address for si570 oscillator that generates the si570_user1
clock. i2c address was changed by commit b6a8c603d680 ("arm64: zynqmp: Fix
i2c addresses for vck190 SC") because address in node name wasn't aligned
with reg property. But actual 0x5f address is correct which is quite rare
because all other si570s are at 0x5d.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6f31881b0e2dd657f0d4ff0869c009c2e1224f22.1694441445.git.michal.simek@amd.com
Added no-wp DT property in OSPI flash node for all board dts & dtsi files
on which the WP# signal of the OSPI flash device is not connected. If this
property is set, then the software will avoid setting the status register
write disable (SRWD) bit in status register during status register
write operation.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7e88dd7b9306bdf0738b2248bf9017e1997d25dc.1694441445.git.michal.simek@amd.com
xlnx,mio_bank was used in past but it was renamed to xlnx,mio-bank because
'_' in property shoudln't be used. There is no impact on the platform
because if the properly is not defined bank 0 is default. Bank 0 and 1 have
the same configuration that's why there shouldn't be any issue.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ace68d4b7701d1606a85cb18242409fce941b363.1694441445.git.michal.simek@amd.com
Now that the zynqmp pinctrl driver supports the tri-state registers, make
sure that the pins requiring output-enable are configured appropriately for
SOMs.
Without it, all tristate setting for MIOs, which are not related to SOM
itself, are using default configuration which is not correct setting.
It means SDs, USBs, ethernet, etc. are not working properly.
In past it was fixed through calling tristate configuration via bootcmd:
usb_init=mw 0xFF180208 2020
kv260_gem3=mw 0xFF18020C 0xFC0 && gpio toggle gpio@ff0a000038 && \
gpio toggle gpio@ff0a000038
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7ecd98b2a302c5c6628e0234482f23c38e721fd6.1693492064.git.michal.simek@amd.com
Revision 2 is SW compatible with revision 1 but it is necessary to reflect
it in model and compatible properties which are parsed by user space.
Rev 2 has improved a power on boot reset and MIO34 shutdown glich
improvement done via an additional filter in the GreenPak chip.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6b9e68ebfb436da391daeb147f2a9985ac984c0c.1692951005.git.michal.simek@amd.com
All si570 mgt chips have factory default 156.25MHz but DT changed it to
148.5MHz. After tracking it is pretty much c&p fault taken from Zynq
zc702/zc706 boards where 148.5MHz was setup as default because it was
requirement for AD7511 chip available on these boards.
ZynqMP board don't contain this chip that's why factory default frequency
can be used.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c052ddf39e392e97f87f1c57ea06f3508733c672.1692947486.git.michal.simek@amd.com
This moves the aes operation that is performed by the pmu into a
separate file. This way it can be called not just from the shell
command, but also e.g. from board initialization code.
Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
Link: https://lore.kernel.org/r/20230725072658.16341-1-christian.taedcke-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The DTS uses constants for SERDES MUX idle state values which were earlier
provided as bindings header. But they are unsuitable for bindings.
So move these constants in a header next to DTS.
NOTE: sync with v6.6-rc1 will bring in this change naturally.
Signed-off-by: Nishanth Menon <nm@ti.com>
Introduce the new serdes header from kernel v6.6-rc1
The DTS uses constants for SERDES MUX idle state values which were earlier
provided as bindings header. But they are unsuitable for bindings.
So move these constants in a header next to DTS.
Signed-off-by: Nishanth Menon <nm@ti.com>
In 2cb43ef1c2 ("usb: ether: Fix error handling in usb_ether_init") the error
handling of usb_ether_init() was changed. Not a single other call site of this
function checks its return value, therefore follow suit in the am33xx code.
Do not cause the boot to halt if the usb gadget ethernet initialization fails:
initcall sequence 9ffdbd84 failed at call 808024b9 (err=-19)
### ERROR ### Please RESET the board ###
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Reviewed-by: Michal Suchánek <msuchanek@suse.de>
Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ9031 PHYs on R-Car Gen3 Salvator-X boards. This allows software
to identify the PHY model at any time, regardless of the state of
the PHY reset line.
This is a fix for missed addition of these properties on Salvator-X
boards.
Ported from Linux kernel commit 722d55f3a9bd810f3a1a31916cc74e2915a994ce .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The usb_gadget_handle_interrupts() is no longer used anywhere,
replace the remaining uses with dm_usb_gadget_handle_interrupts()
which takes udevice as a parameter.
Some of the UDC drivers currently ignore the index parameter altogether,
those also ignore the udevice and have to be reworked. Other like the
dwc3_uboot_handle_interrupt() had to be switched from index to udevice
look up to avoid breakage.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on khadas vim3
Signed-off-by: Marek Vasut <marex@denx.de>
To have the WDIOF_CARDRESET support for the TI AM65x platform watchdog,
this patch reserves some memories, which indicate if the current boot due
to a watchdog reset.
Signed-off-by: Li Hua Qian <huaqian.li@siemens.com>
Update the DDR settings to those generated using 0.10 version of Jacinto
7 DDRSS Register Configuration tool.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
BeagleBoard.org BeaglePlay is an easy to use, affordable open source
hardware single board computer based on the Texas Instruments AM625
SoC that allows you to create connected devices that work even at long
distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L.
Expansion is provided over open standards based mikroBUS, Grove and
QWIIC headers among other interfaces.
This board family can be identified by the 24c32 eeprom:
[aa 55 33 ee 01 37 00 10 2e 00 42 45 41 47 4c 45 |.U3..7....BEAGLE|]
[50 4c 41 59 2d 41 30 2d 00 00 30 32 30 30 37 38 |PLAY-A0-..020078|]
https://beagleplay.org/https://git.beagleboard.org/beagleplay/beagleplay
baseline of base device tree is v6.5-rc1.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Co-developed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
While boot partition support with EMMC boot is useful, it is
constrained by the size of boot hardware partition itself.
In the case of K3 devices, tispl images can contain OP-TEE images that
can substantially vary in size and the u-boot image itself can vary over
time as we enable various features.
So use the CSD information in the case of EMMC_BOOT configuration being
enabled to pick boot partition or UDA FS mode operation to pick.
If EMMC_BOOT is disabled, then depend on filesystem configuration to
pick data from UDA.
While at this, drop the extraneous whitespace.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
The erratum is called locally, make it static, drop the #ifdeffery since
it will only be called in R5 build and mark it potentially unused to
stop compiler screaming at us.
While at this, drop the redundant return for a void function.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Drop the #ifdeffery and use IS_ENABLED() inline check and let the compiler
do it's thing.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Clean the function up a bit further. Return immediately on match
and return ARRAY_SIZE() - 1 on failure. Add proper comment in that
case.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
This platform is behind on migrations (it is the sole user of the oldest
legacy version of the USB gadget stack and is long overdue for
migration) and with Pali no longer being a maintainer, we remove this
platform.
Signed-off-by: Tom Rini <trini@konsulko.com>
If dram_init_banksize() is called from SPL, the rom_pointer, at that
point, is not correctly initialized. This causes wrong calculation of
DRAM start and size in dram_init_banksize(). The issue became apparent
only in Falcon Mode. Added an extra condition to prevent using
rom_pointer in SPL.
Signed-off-by: Elena Popa <elena.popa@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Use the misc_init_f event instead, which is designed for this purpose.
All boards with CONFIG_VID already enable CONFIG_EVENT.
Signed-off-by: Simon Glass <sjg@chromium.org>
Very few of the existing event-spy records use the arguments they are
passed. Update them to use a simple spy instead, to simplify the code.
Where an adaptor function is currently used, remove it where possible.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Merge tag 'u-boot-at91-2023.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.10 cycle:
This feature set includes a new board sama5d29 Curiosity, and various
fixes and alignments for sam9x60 and sam9x60 curiosity board.
Add a newline at the end of the dts, without which the build fails
when including a dtsi file.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Copied as is from Linux Kernel release v6.4.
(dts file is still the same in Linux v6.5-rc7 but was moved to vendor
sub-directories with v6.5-rc1.)
Button works out of the box now if the following config options are
enabled: CONFIG_BUTTON, CONFIG_BUTTON_GPIO, CONFIG_CMD_BUTTON,
CONFIG_DM_GPIO.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
If CONFIG_LED and CONFIG_LED_GPIO are enabled, it is not necessary to
initialize the RGB LED on the board by manually setting hardcoded GPIOs
anymore. Everything is well defined in dts and can be used like on
boards of other vendors.
Keep the old behaviour as fallback, though.
With all this in place enabling CONFIG_CMD_LED gives us a working 'led'
command on the U-Boot shell.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Copied as is from Linux Kernel release v6.4.
(dts file is still the same in Linux v6.5-rc7 but was moved to vendor
sub-directories with v6.5-rc1.)
Signed-off-by: Alexander Dahl <ada@thorsis.com>
This reverts commit c5b68ef8af.
CONFIG_OPTEE_TZDRAM_SIZE is used by imx6-based SoCs as well. Move the
option back.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Adding a phandle to a template node is not allowed, since when the node is
instantiated multiple times, we end up with duplicate phandles.
Drop this invalid constructs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Ethernet on Bananapi-r3 is broken after
commit bd70f3cea3 ("net: mediatek: add support for SGMII 1Gbps auto-negotiation mode")
because changes from this commit were not applied to bpi-r3 devicetree too:
commit aef54ea16c ("arm: dts: medaitek: convert gmac link mode to 2500base-x")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
CFG_STM32MP1_SCMI_SHM_SYSRAM will be disabled by default for STM32MP13x
SoCs in next OP-TEE version and the OP-TEE SMCI server uses the OP-TEE
native shared memory registered by clients.
To be compatible by default with this configuration this patch removes
the shared memory in the SCMI configuration and the associated reserved
memory in SRAM.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Since OP-TEE commit 89ba3422ee80 ("plat-stm32mp1: scmi_server: default
use OP-TEE shared memory"), integrated in OP-TEE 3.22.0-rc1
the default configuration for STM32MP15x SoCs changes,
CFG_STM32MP1_SCMI_SHM_SYSRAM is disabled by default and the OP-TEE SMCI
server uses ithe OP-TEE native shared memory registered by clients.
To be compatible by default with this configuration and the next OP-TEE
version, this patch removes the SHMEM in the SCMI configuration and the
associated reserved memory in the last 4KByte page of SRAM,
in the STM32MP15 device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Commit 02be57caf7 ("riscv: qemu: Enable usb keyboard as an input
device") adds PCI xHCI support to QEMU RISC-V virtual machines and
enables using a USB keyboard as one of the input devices. Similarly,
enable those for ARM virtual machines as well.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Commit 608b80b5b8 ("riscv: qemu: Enable PRE_CONSOLE_BUFFER") enables
buffering console messages for QEMU RISC-V virtual machines so those
printed before the video console is available will still show up on the
display. Similarly, enable it for ARM virtual machines as well.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Commit 716161663e ("riscv: qemu: Enable Bochs video support") enables
a video console for QEMU RISC-V virtual machines using an emulated Bochs
VGA card. Similarly, enable it for ARM virtual machines as well.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
In rmobile_cpuinfo_idx() there is an off-by-one error in accessing the
rmobile_cpuinfo array.
At the end of the loop, i is equal to the array size, i.e.
rmobile_cpuinfo[i] accesses one entry past the end of the array. The
last entry in the array is a fallback value so the loop should count to
ARRAY_SIZE(rmobile_cpuinfo) - 1 instead, this will leave i equal to the
index of the fallback value if no match is found.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This adds support for various new Tegra30 boards (ASUS, LG and HTC) and
has some other minor enhancements, such as enabling the poweroff command
on several Tegra210 and Tegra186 boards.
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Merge tag 'tegra-for-2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-tegra
ARM: tegra: Changes for v2023.10-rc1
This adds support for various new Tegra30 boards (ASUS, LG and HTC) and
has some other minor enhancements, such as enabling the poweroff command
on several Tegra210 and Tegra186 boards.
MT7988 has a t-phy and an x-phy controller. There is already a driver for
t-phy so we can add USB support for this phy type.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Ethernet on Bananapi-r3 is broken after
commit bd70f3cea3 ("net: mediatek: add support for SGMII 1Gbps auto-negotiation mode")
because changes from this commit were not applied to bpi-r3 devicetree too:
commit aef54ea16c ("arm: dts: medaitek: convert gmac link mode to 2500base-x")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Builds for Raspberry Pi targets fail when CONFIG_DISPLAY_CPUINFO is
enabled and following error can be seen -
common/board_f.o:(.rodata.init_sequence_f+0x90):
undefined reference to `print_cpuinfo'
Added implementation of function "print_cpuinfo"
Signed-off-by: Naveen Kumar Chaudhary <naveenchaudhary2010@hotmail.com>
When PIE is enabled in start.S, u-boot/-spl use __rel_dyn_start
and _rel_dyn_end symbol to be loaded to and executed at a
different address than it was linked at.
u-boot-spl.lds is used in SPL build, but relocation information
section(.rela*) were discarded.
In line number 80 in arch/arm/cpu/armv8/u-boot-spl.lds
/DISCARD/ : { *(.rela*) }
If PIE enabled in SPL, __rel_dyn_start which is defined as
.rel_dyn_start in sections.c will be apended to the end of
.bss section.
In our ASPEED case, size of .bss section would let .rel_dyn_start
without 8-byte alignment, leading to alignment fault when
executing ldp instuction in pie_fix_loop.
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
Since ARMv5, the clz instruction allows for efficient implementation of
ffs/fls with builtins. Until ARMv7 (with Thumb-2), this instruction is
only available in ARM mode. LTO makes it difficult to force specific
functions to be in ARM mode, as it is effectively a form of very
aggressive inlining. To work around this, fls/ffs are implemented in
assembly for ARMv5 and ARMv6 when compiling U-Boot in Thumb mode.
Overall, this saves around 75 bytes per call.
This code is synced with v5.15 of the Linux kernel.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sync all am642-evm/am642-sk related DT files
with Linux v6.5-rc1.
- drop timer1 in favor of main_timer0 in am64-main.dtsi.
Need to delete clock & power domain properties of
main_timer1 in -r5.dts else won't boot. This is because
timer_init is done during rproc_start to start System Firmware,
but we can't do any clock/power-domain operations before
System Firmware starts.
- same constraint applies to main_uart0
- drop cpsw3g custom DT property 'mac_efuse' and custom
DT node cpsw-phy-sel as driver picks these from standard
property/node.
- include board dts file in -r5 dts file to avoid duplication
of nodes. Include -u-boot.dtsi on top.
- drop duplicate nodes in -r5 dts and -u-boot.dtsi
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
This reverts commit 28a4c31134.
This node should be in the board DT file and should come from upstream.
Moreover, this PMIC is no present on all variants of am642-sk
and will need a separate board DT file.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com> #SK-AM64B
The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
using external pad-to-pad connection.
Option (1) has two downsides. ETHCK_K is supplied directly from either
PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
since the same PLL output is also used to supply SDMMC blocks, the
performance of SD and eMMC access is affected. The second downside is
that using this option, the EMI of the SoM is higher.
Option (2) solves both of those problems, so implement it here. In this
case, the PLL4_P is no longer limited and can be operated faster, at
100 MHz, which improves SDMMC performance (read performance is improved
from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
count=1). The EMI interference also decreases.
Ported from Linux kernel commit
73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Device tree alignment with Linux kernel v6.4.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never
enter CStandby state and would always end up in CStop state. Clear
the PDDS bit, which indicates the CA cores can enter CStandby state
as it makes little sense to keep it set with CSTBYDIS also set.
This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR
PDDS bits are set, then the chip enters CStandby state even though the
PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that
from happening.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
As reported by the datasheet (DocID027590 Rev 4) for PG12:
- AF9 -> LCD_B4
- AF14 -> LCD_B1
So replace AF14 with AF9 for PG12 in the dts.
Fixes: fe63d3cfb7 ("ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
This is merely a dummy driver that makes sure the DWC3 XHCI driver
finds its reset and PHY controllers. We rely on iBoot to set up
the PHY for us.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Since srecord v1.60, option "-Little_Endian_CONSTant" is deprecated.
Fix the build warnings by updating little‐endian byte order option in
srec_cat command when generating loader header.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Make device tree complete and consistent for pre relocation phase. Some
nodes are missing, causing warnings to be issued on serial port probing
during pre relocation phase (uclass_get_device_by_phandle_id fails when
called by pinctrl_select_state_full: none of these failures is fatal
nor causing issues). Add to *-u-boot.dtsi all required nodes with the
'bootph-some-ram' attribute.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Debug uart is no more inited in board_init_f function: remove this
debug message from board_init_f. If an earliest-as-possible message
after debug uart initialization is needed, enable DEBUG_UART_ANNOUNCE
Kconfig option, instead.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Since commit 0dba45864b ("arm: Init the debug UART") function
debug_uart_init is called in crt files _main before calling
board_init_f. Therefore, there is no need to call it again
inside board_init_f implementation in arm/mach-rockchip/spl.c.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Most board device trees for RK356x set max-frequency = <200000000> in
the sdhci node, some boards like Quartz64 do not. This result in an
error message due to sdhci driver trying to set a clock rate of 0
instead of the max-frequency value.
rockchip_sdhci_probe clk set rate fail!
Fix this by setting a common max-frequency in rk356x-u-boot.dtsi. A
patch to set default max-frequency of sdhci node in linux is planned.
Also remove the forced status = "okay" for the sdhci and sdmmc0 nodes,
boards already set correct state for these nodes.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add cru structure definition in head file to support cpu_info driver.
Series-version: 2
Series-changes: 2
Format the patch header, add commit message and signature.
Signed-off-by: Anton <vao@asu-vei.ru>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
LubanCat2 is a rk3568 based SBC from EmbedFire.
Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header
The dts file is sync from linux mainline.
Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add fdtoverlay_addr_r and enable OF_LIBFDT_OVERLAY for the
use of DT overlay in RV1126.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Align the SPI flash entry with upstream. There's no need
to diverge here.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add the rk3328 rng details to the u-boot.dtsi and
enable the RNG on the Rock64 to be able to provide
a random seed via UEFI.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
(Fix typo message)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
An earlier commit makes the common SPL code call
regulators_enable_boot_on and regulators_enable_boot_off before
iterating over possible boot media for U-Boot proper. There is therefore
no need to do this in the rk3399-specific code, so let's remove it.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Now all linker symbols are declared as type char[]. Though we can
reference the address via both the array name 'var' and its address
'&var'. It's better to unify them to avoid confusing developers.
This patch converts all '&var' linker symbol refrences to the most
commonly used format 'var'.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
1. Convert all linker symbols to char[] type so that we can get the
corresponding address by calling array name 'var' or its address
'&var'. In this way, we can avoid some potential issues[1].
2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has
not been referenced by any source code.
3. Move '__data_end' to the arch x86's own sections header as it's
only used by x86 arch.
4. Remove some duplicate declared linker symbols. Now we use the
standard header file to declare them.
[1] This patch fixes the boot failure on MIPS target. Error log:
SPL: Image overlaps SPL
Fixes: 1b8a1be1a1 ("spl: spl_legacy: Fix spl_end address")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
It is not a parse error to have a default value of "0" for a "hex" type
entry, instead of "0x0". However, "0" and "0x0" are not treated the
same even by the tools themselves. Correct this by changing the default
value from "0" to "0x0" for all hex type questions that had the
incorrect default. Fix one instance (in two configs) of a default of "0"
being used on a hex question to be "0x0". Remove the cases where a
defconfig had set a value of "0x0" to be used as the default had been
"0".
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Function board_switch_core_volt has not been used since it was
defined
Signed-off-by: Shenlin Liang <liangshenlin@eswincomputing.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
add support for x0-x17 registers used by the SMC calls
In SMCCC v1.2 [1] arguments are passed in registers x1-x17.
Results are returned in x0-x17.
This work is inspired from the following kernel commit:
arm64: smccc: Add support for SMCCCv1.2 extended input/output registers
[1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token=
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
This adds initial support for the Toradex Verdin AM62 Quad 1GB WB IT
V1.0A module and subsequent V1.1 launch configuration SKUs. They are
strapped to boot from their on-module eMMC. U-Boot supports booting
from the on-module eMMC only, DFU support is disabled for now due to
missing AM62x USB support.
The device trees were taken straight from Linux v6.5-rc1.
Boot sequence is:
SYSFW ---> R5 SPL (both in tiboot3.bin) ---> ATF (TF-A) ---> OP-TEE
---> A53 SPL (part of tispl.bin) ---> U-boot proper (u-boot.img)
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Fix rcfg_yaml to really point to rm-cfg.yaml and pcfg_yaml to really
point to pm-cfg.yaml which likely is the intention.
While at it also add labels for the remaining items like custmpk_pem,
dkey_pem, bcfg_yaml_sysfw, scfg_yaml_sysfw, pcfg_yaml_sysfw and
rcfg_yaml_sysfw.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Fix second mux option of clkout0 which should really be
DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10
rather than twice the same according to [1].
[1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clocks-for-board0-device
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Allow individual Layerscape boards to opt-out of fsl_setenv_bootcmd
by declaring the original function as weak.
fsl_setenv_bootcmd is used to change the bootcmd based on the
TF-A boot source (e.g QSPI vs SD/MMC) for reasons including
secure boot / integrity measurements and DPAA2 configuration loading.
See previous discussion at [1].
On the Ten64 board, our bootcmd is the same across
all TF-A boot sources so we don't want this behaviour.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
[1] https://patchwork.ozlabs.org/project/uboot/patch/20211110044639.7070-3-matt@traverse.com.au/#2790037
Reviewed-by: Peng Fan <peng.fan@nxp.com>
On Ten64 boards, the "serial number" is the MAC address of the
first Gigabit Ethernet interface (labelled GE0 on the appliance),
and counted up from there.
The previous logic did not take into account U-Boot's ordering
of the network interfaces. By setting aliases/ethernetX in the device
tree we can ensure the U-Boot 'ethX' is the same as the labelled
port order on the unit, as well as the one adopted by Linux.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
This patch adds general board files based on MT7988 SoCs.
MT7988 uses one mmc controller for booting from both SD and eMMC,
and the pins of mmc controller booting from SD are also shared with
one of spi controllers.
So two configs are need for these boot types:
1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC
2. mt7988_sd_rfb_defconfig - SPI-NAND and SD
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds basic support for MediaTek MT7988 SoC.
This includes files that will initialize the SoC after boot and
its device tree.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Now that individual 2.5Gbps SGMII support has been added to
mtk-eth, all boards that use 2.5Gbps link with mt7531 must be
converted to use "2500base-x" instead of "sgmii".
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Now we use fdtdec_setup_mem_size_base() to get DRAM base from fdt ram node
and update gd->ram_base. CFG_SYS_SDRAM_BASE is unused and will be removed.
Also, since mt7622 always passes fdt to linux kernel, there's no need to
assign value to gd->bd->bi_boot_params.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Basically the same as on sam9x60-ek. Same as in Linux. NAND flash is
correctly detected when booting into U-Boot:
U-Boot 2023.07-rc6-00005-g12719f75dc-dirty (Jul 05 2023 - 13:06:35 +0000)
CPU: SAM9X60 128MiB DDR2 SiP
Crystal frequency: 24 MHz
CPU clock : 600 MHz
Master clock : 200 MHz
Model: Microchip SAM9X60 Curiosity
DRAM: 128 MiB
Core: 145 devices, 22 uclasses, devicetree: separate
NAND: 512 MiB
MMC: sdhci-host@80000000: 0, sdhci-host@90000000: 1
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
In: serial
Out: serial
Err: serial
Net: eth0: ethernet@f802c000
Hit any key to stop autoboot: 0
Signed-off-by: Alexander Dahl <ada@thorsis.com>
- nodes moved
- using node references by label instead of dulicating the node tree
Makes it easier to compare with the dts file from Linux kernel.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
The user guide says it's a Microchip 24AA025E48 serial EEPROM, which is
a 2-Kbit I2C Serial EEPROM with EUI-48™ Identity. This is the chip
actually populated on board EV40E67A rev 4.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
No functional changes, but this:
- reorder nodes (ordered by memory offset as in Linux)
- add label to pinctrl node name for easier reference in board files
- fix whitespace
Diff to sam9x60.dtsi in Linux is much better readable now.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Radxa E25 is a network application carrier board for the Radxa CM3I SoM
with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key,
USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header.
Features tested on a Radxa E25 v1.4:
- SD-card boot
- eMMC boot
- USB host
- PCIe/Ethernet adapters is detected
- SATA
Device tree is imported from linux next-20230728.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
rk3328-xhci has been added due to the fact that the upstream
dwc3 is unsupported. Moreover, the driver for rk3328-xhci is
not added to the code tree.
By considering these facts and unsupported rk3328-xhci this
patch is dropping all related code from DT. However, the DWC3
is fixed now in dwc3-generic and RK3328 USB 3.0 is functional
in upcoming patches.
Let's drop it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There is an Errata with the built-in I2C controller where various I2C
hardware errors cause a complete lockup of the CPU (which eventually
results in an watchdog reset).
Put the I2C MPP pins into GPIO mode and use the i2c-gpio driver instead.
This uses a bit-banged implementation of an I2C controller and avoids
triggering the Errata.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
ROCK 5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa.
There are tree variants depending on the DRAM size : 4G, 8G and 16G.
Specifications:
Rockchip Rk3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
4-lane MIPI DSI connector
Audio – 3.5mm earphone jack
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60
Gigabit Ethernet RJ45 with optional PoE support
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 56mm (Raspberry Pi 4 form factor)
Kernel commits:
d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board")
991f136c9f8d ("arm64: dts: rockchip: Update sdhci alias for rock-5a")
304c8a759953 ("arm64: dts: rockchip: Remove empty line from rock-5a")
cda0c2ea65a0 ("arm64: dts: rockchip: Fix RX delay for ethernet phy on rk3588s-rock5a")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Move bootph-all prop to common SoC dt file, because they are typically used
by multiple boards.
Unreferenced nodes are removed from the SPL device tree during a
normal build.
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The pcie pinctrl override added in the commit a76aa6ffa6 ("rockchip:
rk3568-rock-3a: Enable PCIe and NVMe support") is causing a pinmux issue
on linux when using a EFI boot flow.
The pcie reset-gpios must however be configured with gpio function, or
the device will freeze running pci enum and nothing is connected.
Adjust the pinctrl override in u-boot.dtsi to fix this issue. PCIe/NVMe
continues to work in both U-Boot and linux after this change.
Also revert disable of sdmmc2 and uart1 to fix use of wifi in linux when
using a EFI boot flow.
Fixes: a76aa6ffa6 ("rockchip: rk3568-rock-3a: Enable PCIe and NVMe support")
Fixes: 073d911ae6 ("rockchip: rk3568-rock-3a: Sync device tree from linux")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
The commit fd6e425be2 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") enabled SPI flash support by adding a spi0 alias.
Correct this by adding spi0-spi5 aliases in rk3588s-u-boot.dtsi and
SF_DEFAULT_BUS=5 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled
support for parsing and auto discovery of parameters, SFDP.
Fixes: fd6e425be2 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
