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https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
drivers: use devfdt_get_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
842fb5de42
commit
320a1938b6
10 changed files with 33 additions and 33 deletions
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@ -753,11 +753,11 @@ static int hsdk_cgu_clk_probe(struct udevice *dev)
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else
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hsdk_clk->map = hsdk_4xd_clk_map;
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hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
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hsdk_clk->cgu_regs = devfdt_get_addr_index_ptr(dev, 0);
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if (!hsdk_clk->cgu_regs)
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return -EINVAL;
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hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
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hsdk_clk->creg_regs = devfdt_get_addr_index_ptr(dev, 1);
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if (!hsdk_clk->creg_regs)
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return -EINVAL;
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@ -567,9 +567,9 @@ static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
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{
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struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
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plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
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plat->sdr = devfdt_get_addr_index_ptr(dev, 0);
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if (!plat->sdr)
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return -ENODEV;
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return -EINVAL;
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return 0;
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}
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@ -537,7 +537,7 @@ static int xenon_sdhci_of_to_plat(struct udevice *dev)
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host->ioaddr = dev_read_addr_ptr(dev);
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if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
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priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
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priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1);
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name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
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NULL);
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@ -5300,18 +5300,18 @@ static int mvpp2_base_probe(struct udevice *dev)
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}
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/* Save base addresses for later use */
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priv->base = (void *)devfdt_get_addr_index(dev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->base = devfdt_get_addr_index_ptr(dev, 0);
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if (!priv->base)
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return -EINVAL;
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if (priv->hw_version == MVPP21) {
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priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
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if (IS_ERR(priv->lms_base))
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return PTR_ERR(priv->lms_base);
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priv->lms_base = devfdt_get_addr_index_ptr(dev, 1);
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if (!priv->lms_base)
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return -EINVAL;
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} else {
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priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
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if (IS_ERR(priv->iface_base))
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return PTR_ERR(priv->iface_base);
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priv->iface_base = devfdt_get_addr_index_ptr(dev, 1);
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if (!priv->iface_base)
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return -EINVAL;
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/* Store common base addresses for all ports */
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priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
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@ -5350,10 +5350,10 @@ static int mvpp2_probe(struct udevice *dev)
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if (priv->hw_version == MVPP21) {
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int priv_common_regs_num = 2;
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port->base = (void __iomem *)devfdt_get_addr_index(
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port->base = devfdt_get_addr_index_ptr(
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dev->parent, priv_common_regs_num + port->id);
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if (IS_ERR(port->base))
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return PTR_ERR(port->base);
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if (!port->base)
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return -EINVAL;
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} else {
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port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"gop-port-id", -1);
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@ -564,8 +564,8 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
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struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
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/* Get the controller base address */
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pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
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if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
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pcie->ctrl_base = devfdt_get_addr_index_ptr(dev, 0);
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if (!pcie->ctrl_base)
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return -EINVAL;
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/* Get the config space base address and size */
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@ -751,8 +751,8 @@ static int imx_pcie_of_to_plat(struct udevice *dev)
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{
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struct imx_pcie_priv *priv = dev_get_priv(dev);
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priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
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priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
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priv->dbi_base = devfdt_get_addr_index_ptr(dev, 0);
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priv->cfg_base = devfdt_get_addr_index_ptr(dev, 1);
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if (!priv->dbi_base || !priv->cfg_base)
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return -EINVAL;
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@ -250,13 +250,13 @@ static int ls_pcie_ep_probe(struct udevice *dev)
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pcie_ep->pcie = pcie;
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pcie->dbi = (void __iomem *)devfdt_get_addr_index(dev, 0);
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pcie->dbi = devfdt_get_addr_index_ptr(dev, 0);
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if (!pcie->dbi)
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return -ENOMEM;
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return -EINVAL;
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pcie->ctrl = (void __iomem *)devfdt_get_addr_index(dev, 1);
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pcie->ctrl = devfdt_get_addr_index_ptr(dev, 1);
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if (!pcie->ctrl)
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return -ENOMEM;
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return -EINVAL;
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ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev),
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"reg", "reg-names",
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@ -88,13 +88,13 @@ static int comphy_probe(struct udevice *dev)
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int res;
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/* Save base addresses for later use */
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chip_cfg->comphy_base_addr = (void *)devfdt_get_addr_index(dev, 0);
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if (IS_ERR(chip_cfg->comphy_base_addr))
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return PTR_ERR(chip_cfg->comphy_base_addr);
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chip_cfg->comphy_base_addr = devfdt_get_addr_index_ptr(dev, 0);
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if (!chip_cfg->comphy_base_addr)
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return -EINVAL;
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chip_cfg->hpipe3_base_addr = (void *)devfdt_get_addr_index(dev, 1);
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if (IS_ERR(chip_cfg->hpipe3_base_addr))
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return PTR_ERR(chip_cfg->hpipe3_base_addr);
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chip_cfg->hpipe3_base_addr = devfdt_get_addr_index_ptr(dev, 1);
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if (!chip_cfg->hpipe3_base_addr)
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return -EINVAL;
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if (device_is_compatible(dev, "marvell,comphy-a3700")) {
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chip_cfg->comphy_init_map = comphy_a3700_init_serdes_map;
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@ -389,7 +389,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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ofnode subnode;
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plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
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plat->regbase = devfdt_get_addr_index_ptr(bus, 0);
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plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize);
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plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
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plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
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@ -88,7 +88,7 @@ static int ti_musb_of_to_plat(struct udevice *dev)
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int usb_index;
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struct musb_hdrc_config *musb_config;
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plat->base = (void *)devfdt_get_addr_index(dev, 1);
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plat->base = devfdt_get_addr_index_ptr(dev, 1);
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phys = fdtdec_lookup_phandle(fdt, node, "phys");
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ctrl_mod = fdtdec_lookup_phandle(fdt, phys, "ti,ctrl_mod");
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