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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
arm: mediatek: retrieve ram_base from dts node for armv8 platform
Now we use fdtdec_setup_mem_size_base() to get DRAM base from fdt ram node and update gd->ram_base. CFG_SYS_SDRAM_BASE is unused and will be removed. Also, since mt7622 always passes fdt to linux kernel, there's no need to assign value to gd->bd->bi_boot_params. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
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35e6c89b76
commit
5fd6d4c7b3
15 changed files with 68 additions and 37 deletions
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@ -18,6 +18,11 @@
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tick-timer = &timer0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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@ -17,6 +17,11 @@
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stdout-path = &uart0;
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tick-timer = &timer0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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};
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&uart0 {
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@ -18,6 +18,11 @@
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tick-timer = &timer0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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@ -19,6 +19,11 @@
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tick-timer = &timer0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x80000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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@ -18,6 +18,11 @@
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tick-timer = &timer0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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@ -19,6 +19,11 @@
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tick-timer = &timer0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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@ -18,6 +18,11 @@
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tick-timer = &timer0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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@ -19,6 +19,11 @@
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tick-timer = &timer0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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@ -4,11 +4,15 @@
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <asm/armv8/mmu.h>
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#include <asm/cache.h>
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#include <asm/system.h>
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#include <asm/global_data.h>
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#include <asm/u-boot.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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int print_cpuinfo(void)
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{
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@ -20,11 +24,13 @@ int dram_init(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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ret = fdtdec_setup_mem_size_base();
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if (ret)
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return ret;
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return fdtdec_setup_mem_size_base();
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gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
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return 0;
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}
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void reset_cpu(void)
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@ -4,18 +4,25 @@
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <cpu_func.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <asm/armv8/mmu.h>
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#include <asm/system.h>
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#include <asm/global_data.h>
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#include <asm/u-boot.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
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int ret;
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ret = fdtdec_setup_mem_size_base();
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if (ret)
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return ret;
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gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
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return 0;
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}
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <cpu_func.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <asm/armv8/mmu.h>
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#include <asm/system.h>
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#include <asm/global_data.h>
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#include <asm/u-boot.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
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int ret;
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ret = fdtdec_setup_mem_size_base();
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if (ret)
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return ret;
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gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
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return 0;
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}
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@ -14,7 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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@ -9,14 +9,4 @@
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#ifndef __MT7622_H
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#define __MT7622_H
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/* Uboot definition */
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#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
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/* SPL -> Uboot */
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#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
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/* DRAM */
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#define CFG_SYS_SDRAM_BASE 0x40000000
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/* Ethernet */
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#endif
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@ -9,13 +9,4 @@
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#ifndef __MT7981_H
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#define __MT7981_H
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/* Uboot definition */
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#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
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/* SPL -> Uboot */
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#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
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/* DRAM */
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#define CFG_SYS_SDRAM_BASE 0x40000000
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#endif
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#ifndef __MT7986_H
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#define __MT7986_H
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/* Uboot definition */
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#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
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/* SPL -> Uboot */
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#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
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/* DRAM */
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#define CFG_SYS_SDRAM_BASE 0x40000000
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#endif
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