arm64: zynqmp: Switch to amd.com emails

Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2025-03-13 21:36:57 +00:00 · 2023-07-10 14:35:49 +02:00 · 2023-07-10 14:35:49 +02:00 · 174d728471
commit 174d728471
parent 378f4eef09
101 changed files with 116 additions and 116 deletions
--- a/arch/arm/dts/avnet-ultra96-rev1.dts
+++ b/arch/arm/dts/avnet-ultra96-rev1.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2018 - 2020, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2018-2019, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2018-2019, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/versal-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2018-2019, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/versal-mini-qspi.dtsi
+++ b/arch/arm/dts/versal-mini-qspi.dtsi
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2018-2019, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/versal-mini.dts
+++ b/arch/arm/dts/versal-mini.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019, Xilinx, Inc.
 *
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynq-dlc20-rev1.0.dts
+++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts
@ -2,7 +2,7 @@
 /*
 * Copyright (C) 2018 Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;
 #include "zynq-7000.dtsi"
--- a/arch/arm/dts/zynq-minized.dts
+++ b/arch/arm/dts/zynq-minized.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2018, Xilinx, Inc.
 *
- * Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
+ * Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-a2197-revA.dts
+++ b/arch/arm/dts/zynqmp-a2197-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;

--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;

--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;

--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;

--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;

--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;

--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;

--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2018, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2018, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2018, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2015 - 2020, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-mini.dts
+++ b/arch/arm/dts/zynqmp-mini.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2019, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 /dts-v1/;

--- a/arch/arm/dts/zynqmp-r5.dts
+++ b/arch/arm/dts/zynqmp-r5.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2018, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <dt-bindings/gpio/gpio.h>
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2021 - 2022, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <dt-bindings/gpio/gpio.h>
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@ -9,7 +9,7 @@
 * "Y" – A01 board modified with legacy interposer (Nexperia)
 * "Z" – A01 board modified with Diode interposer
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <dt-bindings/gpio/gpio.h>
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <dt-bindings/gpio/gpio.h>
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-smk-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-sm-k26-revA.dts"
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2015 - 2020, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 * Nathalie Chan King Choy
 */

--- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2020, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-zcu102-revB.dts"
--- a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2020, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-zcu102-rev1.0.dts"
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2020, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-zcu102-revA.dts"
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2022, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-zcu106-revA.dts"
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2018 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2018 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2014 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
--- a/arch/arm/mach-tegra/arm64-mmu.c
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 * (This file derived from arch/arm/mach-zynqmp/cpu.c)
 *
 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
--- a/arch/arm/mach-versal/Makefile
+++ b/arch/arm/mach-versal/Makefile
@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2016 - 2018 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>
 #

 obj-y	+= clk.o
--- a/arch/arm/mach-versal/clk.c
+++ b/arch/arm/mach-versal/clk.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2016 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2016 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
 * (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
 */

 #include <common.h>
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2014 - 2015 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>

 obj-y	+= clk.o
 obj-y	+= cpu.o
--- a/arch/arm/mach-zynqmp/clk.c
+++ b/arch/arm/mach-zynqmp/clk.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@ -2,7 +2,7 @@
 /*
 * Copyright 2016 - 2017 Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/arch/arm/mach-zynqmp/include/mach/clk.h
+++ b/arch/arm/mach-zynqmp/include/mach/clk.h
@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #ifndef _ASM_ARCH_CLK_H_
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #ifndef _ASM_ARCH_HARDWARE_H
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #ifndef _ASM_ARCH_SYS_PROTO_H
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/arch/arm/mach-zynqmp/psu_spl_init.c
+++ b/arch/arm/mach-zynqmp/psu_spl_init.c
@ -2,7 +2,7 @@
 /*
 * Copyright 2018 Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 #include <common.h>
 #include <asm/io.h>
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@ -2,7 +2,7 @@
 /*
 * Copyright 2015 - 2016 Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@ -2,7 +2,7 @@
 /*
 * (C) Copyright 2013 - 2014 Xilinx, Inc
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/arch/microblaze/cpu/u-boot-spl.lds
+++ b/arch/microblaze/cpu/u-boot-spl.lds
@ -2,7 +2,7 @@
 /*
 * (C) Copyright 2013 - 2014 Xilinx, Inc
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <asm-offsets.h>
--- a/arch/microblaze/include/asm/spl.h
+++ b/arch/microblaze/include/asm/spl.h
@ -2,7 +2,7 @@
 /*
 * (C) Copyright 2013 - 2014 Xilinx, Inc
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #ifndef _ASM_MICROBLAZE_SPL_H_
--- a/board/xilinx/common/Makefile
+++ b/board/xilinx/common/Makefile
@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 # (C) Copyright 2020 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>
 #

 obj-y	+= board.o
--- a/board/xilinx/common/board.h
+++ b/board/xilinx/common/board.h
@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
 * (C) Copyright 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #ifndef _BOARD_XILINX_COMMON_BOARD_H
--- a/board/xilinx/common/cpu-info.c
+++ b/board/xilinx/common/cpu-info.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2014 - 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/board/xilinx/common/fru.h
+++ b/board/xilinx/common/fru.h
@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
 * (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 #ifndef __FRU_H
--- a/board/xilinx/versal/Makefile
+++ b/board/xilinx/versal/Makefile
@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2016 - 2018 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>
 #

 obj-y	:= board.o
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2014 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <command.h>
--- a/board/xilinx/versal/cmds.c
+++ b/board/xilinx/versal/cmds.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
 * (C) Copyright 2020 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <cpu_func.h>
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2014 - 2016 Xilinx, Inc.
-# Michal Simek <michal.simek@xilinx.com>
+# Michal Simek <michal.simek@amd.com>

 obj-y	:= zynqmp.o

--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
 * (C) Copyright 2018 Xilinx, Inc.
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 #include <common.h>
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <common.h>
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@ -6,7 +6,7 @@
 * (C) Copyright 2016
 * Toradex AG
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 * Stefan Agner <stefan.agner@toradex.com>
 */
 #include <common.h>
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2015 - 2016 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */
 #include <common.h>
 #include <dm.h>
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 #include <common.h>
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
 * (C) Copyright 2019, Xilinx, Inc,
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 #include <common.h>
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
 * (C) Copyright 2015 - 2016, Xilinx, Inc,
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
 */

 #include <console.h>
--- a/drivers/net/xilinx_axi_mrmac.c
+++ b/drivers/net/xilinx_axi_mrmac.c
@ -3,7 +3,7 @@
 * Xilinx Multirate Ethernet MAC(MRMAC) driver
 *
 * Author(s):   Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- *              Michal Simek <michal.simek@xilinx.com>
+ *              Michal Simek <michal.simek@amd.com>
 *
 * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
 */
--- a/drivers/net/xilinx_axi_mrmac.h
+++ b/drivers/net/xilinx_axi_mrmac.h
@ -3,7 +3,7 @@
 * Xilinx Multirate Ethernet MAC(MRMAC) driver
 *
 * Author(s):   Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- *              Michal Simek <michal.simek@xilinx.com>
+ *              Michal Simek <michal.simek@amd.com>
 *
 * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
 */
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@ -3,7 +3,7 @@
 * Xilinx pinctrl driver for ZynqMP
 *
 * Author(s):   Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
- *              Michal Simek <michal.simek@xilinx.com>
+ *              Michal Simek <michal.simek@amd.com>
 *
 * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
 */
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@ -3,7 +3,7 @@
 * Xilinx ZynqMP SOC driver
 *
 * Copyright (C) 2021 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 *
 * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
 * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
--- a/drivers/watchdog/xilinx_tb_wdt.c
+++ b/drivers/watchdog/xilinx_tb_wdt.c
@ -2,7 +2,7 @@
 /*
 * Xilinx AXI platforms watchdog timer driver.
 *
- * Author(s):	Michal Simek <michal.simek@xilinx.com>
+ * Author(s):	Michal Simek <michal.simek@amd.com>
 *		Shreenidhi Shedi <yesshedi@gmail.com>
 *
 * Copyright (c) 2011-2018 Xilinx Inc.
--- a/drivers/watchdog/xilinx_wwdt.c
+++ b/drivers/watchdog/xilinx_wwdt.c
@ -2,7 +2,7 @@
 /*
 * Xilinx window watchdog timer driver.
 *
- * Author(s):	Michal Simek <michal.simek@xilinx.com>
+ * Author(s):	Michal Simek <michal.simek@amd.com>
 *		Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
 *
 * Copyright (c) 2020, Xilinx Inc.
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@ -2,7 +2,7 @@
 /*
 * Configuration for Xilinx Versal
 * (C) Copyright 2016 - 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 *
 * Based on Configuration for Xilinx ZynqMP
 */
--- a/include/configs/xilinx_versal_mini.h
+++ b/include/configs/xilinx_versal_mini.h
@ -3,8 +3,8 @@
 * Configuration for Xilinx Versal MINI configuration
 *
 * (C) Copyright 2018-2019 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 #ifndef __CONFIG_VERSAL_MINI_H
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@ -2,7 +2,7 @@
 /*
 * Configuration for Xilinx ZynqMP
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 *
 * Based on Configuration for Versatile Express
 */
--- a/include/configs/xilinx_zynqmp_mini.h
+++ b/include/configs/xilinx_zynqmp_mini.h
@ -3,8 +3,8 @@
 * Configuration for Xilinx ZynqMP Flash utility
 *
 * (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 #ifndef __CONFIG_ZYNQMP_MINI_H
--- a/include/configs/xilinx_zynqmp_mini_nand.h
+++ b/include/configs/xilinx_zynqmp_mini_nand.h
@ -3,8 +3,8 @@
 * Configuration for Xilinx ZynqMP Nand Flash utility
 *
 * (C) Copyright 2018 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 #ifndef __CONFIG_ZYNQMP_MINI_NAND_H
--- a/include/versalpl.h
+++ b/include/versalpl.h
@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
 * (C) Copyright 2019 Xilinx, Inc,
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
 */

 #ifndef _VERSALPL_H_
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
 * (C) Copyright 2015 Xilinx, Inc,
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #ifndef _ZYNQMPPL_H_
--- a/tools/zynqmp_psu_init_minimize.sh
+++ b/tools/zynqmp_psu_init_minimize.sh
@ -1,6 +1,6 @@
 #!/bin/bash
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com>
+# Copyright (C) 2018 Michal Simek <michal.simek@amd.com>
 # Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
 # Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
 # Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
--- a/tools/zynqmpimage.c
+++ b/tools/zynqmpimage.c
@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2016 Michal Simek <michals@xilinx.com>
+ * Copyright (C) 2016 Michal Simek <michal.simek@amd.com>
 * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
 *
 * The following Boot Header format/structures and values are defined in the
--- a/Show more
+++ b/Show more