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rockchip: rk3568-rock-3a: Enable PCIe and NVMe support
Add missing pinctrl and defconfig options to enable PCIe and NVMe support on Radxa ROCK 3 Model A. Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1. The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is restored to the perstn pin, a workaround to avoid having to define a new rockchip,pins. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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2 changed files with 23 additions and 0 deletions
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@ -36,8 +36,22 @@
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bootph-all;
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};
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&pcie2x1 {
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pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>;
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};
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&pcie3x2 {
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pinctrl-0 = <&pcie30x2m1_pins &pcie3x2_reset_h>;
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};
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&pinctrl {
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bootph-all;
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pcie {
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pcie3x2_reset_h: pcie3x2-reset-h {
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rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pcfg_pull_none {
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@ -22,7 +22,9 @@ CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_SYS_LOAD_ADDR=0xc00800
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CONFIG_PCI=y
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CONFIG_DEBUG_UART=y
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CONFIG_AHCI=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_SIGNATURE=y
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@ -46,6 +48,7 @@ CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_PMIC=y
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@ -56,6 +59,8 @@ CONFIG_OF_LIVE=y
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CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_SPL_REGMAP=y
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CONFIG_SPL_SYSCON=y
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CONFIG_SCSI_AHCI=y
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CONFIG_AHCI_PCI=y
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CONFIG_SPL_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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@ -70,6 +75,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_XTX=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_NVME_PCI=y
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CONFIG_PCIE_DW_ROCKCHIP=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
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CONFIG_SPL_PINCTRL=y
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@ -78,6 +85,8 @@ CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_SPL_RAM=y
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CONFIG_SCSI=y
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CONFIG_DM_SCSI=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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