Add the TPM device found on the GW72xx revision F PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add the TPM device found on the GW72xx revision F PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Incorrect registers HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL
and HW_POWER_VDDDCTRL are used in the current code to disable/enable
brownout interrupts in 'mxs_power_set_vddx()'.
Change register to HW_POWER_CTRL which contains brownout interrupt
enable bits ENIRQ_VDDIO_BO, ENIRQ_VDDA_BO and ENIRQ_VDDD_BO.
Signed-off-by: Cody Green <cody@londelec.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmWCxMoACgkQd9zb2sjI
SdFG2A//Zc/bbiy8GPZ5Hi3hgB90H5xVjsivgMW2Riw5ZiMiC3v8klKlzbKprzNy
1Zf4002A/yn470YIDInUFEJVc1ZeGbyMj9u7HDId+/4FhtdXVWGjON+lINlShrWL
FX9ITBbxBKEfno6uoDD1Gy5xq1LFl3kXSeingGZnm3W+b9FJb9mo2X1UgUE70Pkp
Kw/dyL6ZVmvAGnuuonc55Kxgoc5m92Ww2wJxbLMCYmPwqHRveduGZfS6nQxJnJU7
XT8fOK5GsAbYWMnI63Nf5Bue6yTCKJH8CE7Kg1mJjMNm+Ictqo/aCQX3S1nZiBL0
CHvHOhrck3Db5+AfmKQDwYofb/Haaf97auf1sGCi/PVnmLn1c3BPON3qyK2Qvjbx
1WAvWea5I97Pv8hMGEPecTMACgTF3XOJIBGXMuAc5ScO3rlckeSZdb/m5/3nHEei
ZcwfxNMw8OqECnIG/13NoYkOGEWG22DtoNuD75ESztKGAz3YL5Rfr+siZniyGNsq
9ZdFVf7AQwDSRUmcpFN9ETawfU8Y9rK7fp5L6yUTTCKtQBL1+qUPyYb2KvH1LvfH
PKECA9D6XKpdgLHjyAJrMHlpaOQiqBDAUvZrdDGZWHMaKSL8XXZKPaj2a124RqtW
NZfri43xj5a/AeeMBAkRrz3BzFfXn5EGoGdbduq+HXnJTaMCrdI=
=aBS6
-----END PGP SIGNATURE-----
Merge tag 'u-boot-amlogic-next-20231220' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
- Add support for new GXL MDIO mux, with driver and Linux DT sync from v6.4
This PR contains 4 patchsets:
1. PMIC GPIO cells bringup. Created drivers for MAX7663 and Palmas
PMICs and gpio-uclass patch isolated behind configs for these 2
drivers. No unintentional size increase on any board. (proposed
2023-11-06 without any reaction)
2. Simple PLL clocks support in common tegra clock code which allows
use of simple PLL the same way main PLLs are used (before only
clock_start_pll was available). PLLD2 is an example of simple PLL, it
is used as a video subsystem parent clock and was used to test this
code. So far everything worked as expected. (proposed 2023-11-16
without any reaction)
3. A small patch for tegra emmc to allow pass max frequency from
device tree since some devices may not support full speed.
4. Pinmux DM conversion. Patchset consists of commit with DM wrapper
for existing pinmux code for t20/t30/t114, pinmux and funcmux files
relocation into a dedicated folder inside pinctrl, conversion of some
tegra boards to device tree pinmux setup.
Since implementation of pinctrl driver for T20 Paz00 can switch
to device tree pinmux setup along with remove of board pinmux
and some minor device tree and defconfig tweaks.
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Drop the pinmux setup in the board in favor of setting it up in
the device tree. Device tree nodes match nodes used for the Linux
device tree and are set according to the downstream kernel.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Drop the pinmux setup in the board in favor of setting it up in
the device tree. Device tree nodes match nodes used in the Linux
device tree.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Drop the pinmux setup in the board in favor of setting it up in
the device tree. Device tree nodes match nodes used for the Linux
device tree and are set according to the service manual.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Drop the pinmux setup in the board in favor of setting it up in
the device tree. Device tree nodes match nodes used in the Linux
device tree.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Move all existing pinmux and funcmux code into a dedicated folder in
pinctrl to simplify further maintenance.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The existing pinctrl driver available for Tegra SOC is well
designed, but it lacks DM support. Let's add a DM compatible
overlay, which allows use of the device tree, along with preserving
backward compatibility with all existing setups and the ability
to use it in SPL board configuration stage.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
SPL configs are used only by the ARMv7-based Tegra SOC's, so move
SPL_SYSRESET under TEGRA_ARMV7_COMMON selection and enable SPL_DM
since SPL_SYSRESET depends on it.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The driver currently hard-codes the max freqency for the sdhci
controllers. If the controller is unable to operate at the max
frequency, the mmc card will not be available on the first scan.
Subsequent scans will eventually find a working combination.
Fix this by allowing the driver to check for the max-frequency
property and default to the original value if it doesn't exist.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Simple PLL clocks like PLLD2 were omitted since they do not share common
4 register structure with main clocks. Such clocks are containd in simple
PLL group. Only clock_start_pll function supported them. This patch expands
this support on clock_set_rate and clock_get_rate which should make
simple PLL clocks equal to main PLL clocks.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
UCLASS_PMIC may have GPIO children without exposed fdt node,
in this case if requesting fails, check if uclass is PMIC.
Restrict build for supported devices only to save those precious
bytes on devices with no spare memory.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
MAXIM Semiconductor's PMIC, MAX77663 has 8 GPIO pins and 3 GPIO-like
pins. It also supports interrupts from these pins.
Add GPIO driver for these pins to control via GPIO APIs.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Julien Masson <jmasson@baylibre.com> says:
This patch series add the support for the MediaTek MT8365 EVK Board [1].
Most of the code have been copied/adapted from Linux tag v6.7-rc2.
For now we only enable/test these features:
Boot, UART, Watchdog and MMC.
[trini: This includes two clocks not listed in the Linux binding, which
needs resyncing later]
Previously, dynamic frequency scaling supported rates only through fixed
divison.
This virtual clock mux configuration enables more varied rates on A72
clock ID 202 by setting up the required register.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
In order for the Cortex-A72s to operate at different frequencies other
than the default 2GHz, add in a new 'virtual' mux (a mux that does not
physically exist in the clock tree) that can be selected.
CC: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
This adds support for the MT8365 EVK board with the following
features enabled/tested: Boot, UART, Watchdog and MMC.
Signed-off-by: Julien Masson <jmasson@baylibre.com>
This adds the pinctrl bindings for Mediatek MT8365 SoC based on the
dt-bindings in Linux tag v6.7-rc2.
(commit 8b4c397d88d97d4fd9c3f3527aa66688b1a3387a)
Signed-off-by: Julien Masson <jmasson@baylibre.com>
This patch adds basic support for MediaTek MT8365 SoC.
The dtsi has been copied from Linux source code tag v6.7-rc2.
(commit 9b5d64654ea8f51fe1e8e29ca1777b620be8fb7c)
Signed-off-by: Julien Masson <jmasson@baylibre.com>
This patch adds clock driver support for MediaTek MT8365 SoC.
The changes are based on the Linux source code tag v6.7-rc2.
clk-mt8365.c has been written based on these kernel files:
- clk-mt8365.c (a96cbb146a9736f501fe66ebda6a9018735e5e8a)
- clk-mt8365-apmixedsys.c (65c9ad77cbc0eed78db94d80041aba675cfbdfa9)
And adapted following the clk attributes supported by U-Boot.
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This adds the clock bindings for Mediatek MT8365 SoC based on the
dt-bindings in Linux tag v6.7-rc2.
(commit c61978175ac1337f028ac1f956666f16db84f4e5)
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
spl_mmc_emmc_boot_partition return a number different from 0
if the partition is a boot one. We can have the uboot img
for instance in a raw offset in emmc partition 0 so we would
like to continue to load the next stage. If the user want
to use EMMC as boot device allow him to use any part of the
emmc and not only boot partition
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The block count limit on MMC based devices should be set according to
CONFIG_SYS_MMC_MAX_BLK_COUNT instead of hardcoding value.
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Change optee driver service enumeration to not enumerate (and
allocate a zero sized shared memory buffer) when OP-TEE
reports that there is no service to enumerate.
This change fixes an existing issue that occurs when the such zero
sized shared memory buffer allocated from malloc() has a physical
address of offset 0 of a physical 4kB page. In such case, OP-TEE
secure world refuses to register the zero-sized shared memory
area and makes U-Boot optee service enumeration to fail.
Fixes: 94ccfb78a4 ("drivers: tee: optee: discover OP-TEE services")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Change optee probe function to only warn when service enumeration
sequence fails instead of reporting an optee driver probe failure.
Indeed U-Boot can still use OP-TEE even if some OP-TEE services are
not discovered.
Fixes: 94ccfb78a4 ("drivers: tee: optee: discover OP-TEE services")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
DSP core is going into abnormal state when load callback is called
after starting of DSP core.
Reload of firmware needs core to be stopped first, followed by
load.
So avoid loading of firmware, when core is started.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
The AEM and Juno FVPs (Fixed Virtual Platforms) support a VirtIO
disc interface. Adding VIRTIO to the list of boot devices allows
these FastModel platforms to boot from 'disc' in the same way
the hardware counterpart can boot from SATA or USB.
This is a NOP if CONFIG_CMD_VIRTIO is not enabled, so no impact
on Juno hardware (which is built with vexpress_aemv8a_juno_defconfig)
Signed-off-by: Robert Catherall <robert.catherall@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Sync Amlogic GXBB, GXL & GXM DTs from Linux v6.4, and also
switch to GXL MDIO MUX driver to adapt to DT change,
Most of the changes are only cosmetic or doesn't concern U-Boot,
the most important change for U-Boot is the GXL mdio mux compatible
switch to amlogic,gxl-mdio-mux.
Link: https://lore.kernel.org/r/20231213-u-boot-gxl-mdio-mux-v2-2-c56bb02a75ea@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Port the mdio-mux-meson-gxl.c Linux driver introduced in [1],
and adapt it to U-Boot.
This driver is needed to boot U-Boot with Linux DT since v6.4,
since it switched the MDIO mux from the mmio to a proper GXL driver.
[1] 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support")
Link: https://lore.kernel.org/r/20231213-u-boot-gxl-mdio-mux-v2-1-c56bb02a75ea@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Migrate to the new environment format and drop most of the config.h.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add timer driver in Starfive SoC. It is an timer that outside
of CPU core and inside Starfive SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Changes for v2:
- correct driver name, comment, variable
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
The patch contains initial wiring and configuration for initial HW design
with memory, cpu, interrupt controller, timers and uartlite console
(interrupt controller is listed but U-Boot is not using it).
Provided DT is just describing one configuration and should be taken only
as example.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Add gpio-restart node to do reset.
Before applied this patch, System Reset Extension doesn't appear with
sbi command.
OpenSBI 1.3
Machine:
Vendor ID 489
Architecture ID 8000000000000007
Implementation ID 4210427
Extensions:
sbi_set_timer
sbi_console_putchar
...[snip]...
IPI Extension
RFENCE Extension
Hart State Management Extension
Performance Monitoring Unit Extension
After applied this patch, System Reset Extension is supported from SBI.
OpenSBI 1.3
Machine:
Vendor ID 489
Architecture ID 8000000000000007
Implementation ID 4210427
Extensions:
sbi_set_timer
sbi_console_putchar
...[snip]...
IPI Extension
RFENCE Extension
Hart State Management Extension
System Reset Extension
Performance Monitoring Unit Extension
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Documentation:
* replace MD5 and SHA1 by SHA256 in examples
UEFI:
* Refactor boot manager and bootefi command to let the EFI boot method work
without shell.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEK7wKXt3/btL6/yA+hO4vgnE3U0sFAmV++kAACgkQhO4vgnE3
U0ufFBAAp05Dxh/f7/lHh5YB6SX6IVyxw69G+PZxY6w4stsm8OaS8YX0bgGptC/B
Wz3xh42PTUN8sc9mQeUV+Scl+hAiURibhk8RVxtL+zV+j+zPrRBNIGiz8Kel7iNi
6F4k+5grw9NncD9MPpTpthfHP7lTKL9RE+YRscGDyaWd4COn8JJfw8Phluv7dvFj
XgkHZ96yhKnxzRQcBZTNV5nujptID608yqgp/k22AxKr+8GjdJZ6VbS2jKXN1vV4
kOQJTP/naezmOaU53sF5Nj2WtU+PzaKGA1mD+mIKSjzbQ0VH0PvJ7z67nB1e1d4+
eYkyTz6HJQi/vtx1f1wJIj5D2c5ti/FxHOtLwdwoudzlOSd8cvAMGrnle1mXzgqZ
juH/aLxdLqNyXu3mnWH+bo8Jy1nFDDBg+V77pdcUr9LXd+doTAye+oZz+iYaN3DW
7E+8Cw+hViOcs/5x5Hs4nqJOyZhvZpdN1fsyLurPyA6hemgESRZKVWimBMejYuwl
yUZA+6nDopwm2DInrIS10WgO9ob0jjUx/mgiEtYIPp/zYsg+Sz8npiQnAOvo9qA2
DY0EIewBaSwW5krgBC3G1OV6Q1FehRhEqW2XsC5AuqwU1l7O5I1e86WUMMP/2dzM
BEMuTuZcfOY2bB/2az/9MIAiNrQDbAs+GHWsh41cE2eZFzYYxT8=
=hvkt
-----END PGP SIGNATURE-----
Merge tag 'efi-next-20231217' of https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request for efi-next-20231217
Documentation:
* replace MD5 and SHA1 by SHA256 in examples
UEFI:
* Refactor boot manager and bootefi command to let the EFI boot method work
without shell.
