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3d5e52bd97
As the code to switch an ARM core from secure to the non-secure state needs to know the base address of the Generic Interrupt Controller (GIC), we read an Arm Cortex defined system register that is supposed to hold that base address. However there are SoCs out there that get this wrong, and this CBAR register either reads as 0 or points to the wrong address. To accommodate those systems, so far we use a macro defined in some platform specific header files, for affected boards. To simplify future extensions, replace that macro with a Kconfig variable that holds this override address, and define a default value for SoCs that need it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> |
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| .. | ||
| cpu | ||
| dts | ||
| include | ||
| lib | ||
| mach-apple | ||
| mach-aspeed | ||
| mach-at91 | ||
| mach-bcm283x | ||
| mach-bcmbca | ||
| mach-bcmstb | ||
| mach-cortina | ||
| mach-davinci | ||
| mach-exynos | ||
| mach-highbank | ||
| mach-histb | ||
| mach-hpe | ||
| mach-imx | ||
| mach-integrator | ||
| mach-ipq40xx | ||
| mach-k3 | ||
| mach-keystone | ||
| mach-kirkwood | ||
| mach-lpc32xx | ||
| mach-mediatek | ||
| mach-meson | ||
| mach-mvebu | ||
| mach-nexell | ||
| mach-npcm | ||
| mach-octeontx | ||
| mach-octeontx2 | ||
| mach-omap2 | ||
| mach-orion5x | ||
| mach-owl | ||
| mach-qemu | ||
| mach-rmobile | ||
| mach-rockchip | ||
| mach-s5pc1xx | ||
| mach-snapdragon | ||
| mach-socfpga | ||
| mach-sti | ||
| mach-stm32 | ||
| mach-stm32mp | ||
| mach-sunxi | ||
| mach-tegra | ||
| mach-u8500 | ||
| mach-uniphier | ||
| mach-versal | ||
| mach-versal-net | ||
| mach-versatile | ||
| mach-zynq | ||
| mach-zynqmp | ||
| mach-zynqmp-r5 | ||
| thumb1/include/asm/proc-armv | ||
| config.mk | ||
| Kconfig | ||
| Kconfig.debug | ||
| Makefile | ||