Add sdhci node to SPL and u-boot,spl-boot-order. Also add more supported
mmc modes and pinctrl.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a node for the trng found on RK3588 SoCs.
Changes in V3:
- Added Reviewed-By tag.
Changes in V2:
- None
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Sync the sdmmc node from linux-next, include required nodes in SPL and
imply Kconfig options required for functional sdmmc clk in SPL and
U-Boot proper.
This make it possible for both SPL and U-Boot proper to configure sdmmc
clocks. In SPL, before TF-A is loaded, scru regs is configured, in
U-Boot proper a SCMI message is sent to TF-A.
Fixes: 95c8656b72 ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.
The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.
This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.
Fixes: 7a474df740 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of
OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay
and kernel compression.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf
v2.3. Mainline atf v2.3 contains an issue that could lead to a crash
when it fails to parse the fdt blob being passed as the platform param.
An issue that was fixed in atf v2.4.
The vendor TF-A seem to suffer from a similar issue, and this prevents
booting when fdt blob is large enough to trigger this condition.
Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a
NULL pointer instead of the fdt blob as the platform param.
This fixes booting Radxa ROCK 3A after recent sync of device tree.
Fixes: 073d911ae6 ("rockchip: rk3568-rock-3a: Sync device tree from linux")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Running U-Boot from a SD-card on ROCK 5 Model B fails to load atf using
DMA and prints debug_uart messages.
<debug_uart>
<debug_uart>
U-Boot SPL 2023.04-rc3 (Mar 12 2023 - 00:30:16 +0000)
Trying to boot from MMC1
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-1' image node
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Use fifo-mode to disable DMA in SPL, add same-as-spl to boot-order and
remove DEBUG_UART_ANNOUNCE option to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
misc_read() is documented to return the number of bytes read or a
negative error value. The Rockchip drivers currently do not implement
this correctly and instead return zero on success or a negative error
value.
In preparation for fixing the drivers, fix the condition here to only
error on negative values.
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync rk3066/rk3188 DT files from Linux.
This is the state as of linux-next v6.2-rc4.
New nfc node for MK808 rk3066a.
CRU nodes now have a clock property.
To prefend dtoc errors a fixed clock must also be
included for tpl/spl in the rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3188-u-boot.dtsi
for now till a better method is found.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3066a-u-boot.dtsi
for now till a better method is found.
Disable gpio6 as the driver gives an error code
on return as status.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the pwm nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the vop/lvds/mipi/hdmi nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to better compare the Linux rk3288.dtsi version
with the U-Boot version move the io-domains nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
ft_board_setup() should be availble for use in board files but using it
in the rk3288 machine file blocks this functionality.
ft_system_setup() is the more appropriate function to use in a machine
definition.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.
Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
rockchip and also a reference board for board vendors.
Hardware:
SoC: RK3588
DRAM: LPDDR4X 8GB
Debug: UART2 via USB
PCIe: 3x4 *1
SATA *2
HDMI out *2
HDMI IN *1
USB2.0 Host *2
USB3.0 Host *1
Type C *1
MIPI DSI panel
dts Sync from Linux v6.2.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
Some sections in the linker scripts are aligned to 4 bytes, which
may cause misaligned exception on some platforms, e.g.: clearing
the bss section on 64-bit hardware if __bss_start does not start
from a naturally 8 bytes aligned address.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
U-Boot SPL is not relocable. Drop these relocation sections.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
board_init_r does not return for U-Boot SPL hence there is no need
to update the link register when jumping to board_init_r.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The codes currently skip the very first relocation entry, and have
an inaccurate comment "skip first reserved entry" indicating that
the first entry is reserved, but later it references the elements
in the first relocation entry using a minus offset.
Change to use a positive offset so that there is no need to skip
the first relocation entry.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
't5' already contains relocation type so don't bother reloading it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
The __bss_start is the source end address hence load its address
directly into register 't2' for optimization.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Since commit 409e4b5478 ("Makefile: Enforce DWARF4 output") the
whole U-Boot build switched to enforce DWARF4 output, but RISC-V
is still on its own setting. Let's switch to use U-Boot's setting.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Add Kconfig to select the basic functions for StarFive JH7110 SoC.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Add StarFive JH7110 SoC to support RISC-V arch.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
In all these cases, the index on the LHS is immediately afterwards
used to access the array appearing in the ARRAY_SIZE() on the RHS - so
if that index is equal to the array size, we'll access
one-past-the-end of the array.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add QSPI support on STM32MP13x SoC family
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
- Spring Cleanup of Amlogic board documentation
- add support for BananaPi M2-Pro
- add support for BananaPi M2S
- add support for Radxa Zero2
- add support for WeTek Hub and WeTek Play2
- switch LibreTech-CC v2 and WeTek Core2 to EE powerdomain
- add support for Beelink GT1 Ultimate
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Merge tag 'u-boot-amlogic-20230417' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- Add initial support for BPI-CM4
- Spring Cleanup of Amlogic board documentation
- add support for BananaPi M2-Pro
- add support for BananaPi M2S
- add support for Radxa Zero2
- add support for WeTek Hub and WeTek Play2
- switch LibreTech-CC v2 and WeTek Core2 to EE powerdomain
- add support for Beelink GT1 Ultimate
Import the dts files from linux-amlogic/for-next (Linux 6.4-rc1) and
add the old PHY reset bindings for dwmac to the u-boot.dtsi until we
support the new bindings in the PHY node. Without this the PHY is not
functional in u-boot or Linux.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323143142.780306-13-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Import the device-tree from linux-amlogic/for-next (Linux 6.4-rc1)
to support the Radxa-Zero2 board.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323143142.780306-10-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Import the device-tree from linux-amlogic/for-next (Linux 6.4-rc1)
and omit the NPU node from the A311D board variant dts as this is
not supported under U-Boot.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323143142.780306-7-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Import the board dts from the linux-amlogic/for-next (6.4-rc1)
branch. This involves spliting the BPI-M5 dts into a dtsi and
then reusing this for the M2-Pro.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323143142.780306-4-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Add support for both the BananaPi BPI-CM4 module and the BananaPi
baseboard which is compatible with the RaspberryPi CM4IO baseboard.
The BananaPi BPI-CM4 module follows the CM4 specifications at [1],
but with a single HDMI port and a single DSI output.
The current CM4IO baseboard DT should work fine on the Raspberry CM4
baseboard and other derivatives baseboards, but proper DT should
be written for other baseboards.
[1] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf
Link: https://lore.kernel.org/r/20230307-u-boot-cm4-v1-2-43f5a393cd37@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
The QEMU emulation of m68k does not support RAMBAR accesses,
add Kconfig option which inhibits those accesses, so that
U-Boot can be started in m68k QEMU for CI testing purpopses
until QEMU emulation improves.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The QEMU emulation of m68k does not support DMA timer, the only
timer that is supported is the PIT timer. Implement trivial PIT
timer support for m68k.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
There is an existing CONFIG_MCFTMR Kconfig symbol,
use it and drop all other instances of CFG_MCFTMR.
This duality is likely a result of bogus conversion
to Kconfig.
Fixes: 7ff7b46e6c ("m68k: rename CONFIG_MCFTMR to CFG_MCFTMR")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add a new config option CONFIG_MVEBU_SPL_SATA_BLKSZ for specifying block
size of SATA disk. This information is used during building of SATA
kwbimage and must be correctly set, otherwise BootROM does not load SPL.
For 4K Native disks CONFIG_MVEBU_SPL_SATA_BLKSZ must be set to 4096.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Find SATA block device by blk_get_devnum_by_uclass_id() function and read
from it the real block size of the SATA disk.
Signed-off-by: Pali Rohár <pali@kernel.org>
Some SoCs of the H616 family use a die variant, that puts some CPU power
and reset control registers at a different address. There are examples
of two instances of the same board, using different die revisions of the
otherwise same H313 SoC. We need to write to a register in that block
*very* early in the SPL boot, to switch the core to AArch64.
Since the devices are otherwise indistinguishable, let the SPL code read
that die variant and use the respective RVBAR address based on that.
That is a bit tricky, since we need to do that in hand-coded AArch32
machine language, shared by all 64-bit SoCs. To avoid build dependencies
in this mess, we always provide two addresses to choose from, and just
give identical values for all other SoCs. This allows the same code to
run on all 64-bit SoCs, and controls this switch behaviour purely from
Kconfig.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need
to program the 64-bit start code address into an MMIO mapped register
that shadows the architectural RVBAR register.
This address is SoC specific, with just two versions out there so far.
Now a third address emerged, on a *variant* of an existing SoC (H616).
Change the boot0.h start code to make this address a Kconfig
selectable option, to allow easier maintenance.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
It turns out that some H616 and related SoCs (like H313) need TPR2
parameter for proper working. Add it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Currently twr2rd, trd2wr and twtp are constants, but according to
vendor driver they are calculated from other values. Do that here too,
in preparation for later introduction of new parameter.
While at it, introduce constant for t_wr_lat, which was incorrectly
calculated from tcl before.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Part of the code, previously known as "unknown feature", also doesn't
have constant values. They are derived from TPR0 parameter in vendor
DRAM code.
Let's move that code to separate function and introduce TPR0 parameter
here too, to ease adding new boards.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
These values are highly board specific and thus make sense to add
parameter for them. To ease adding support for new boards, let's make
them same as in vendor DRAM settings.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Mentioned function result is always true and result isn't checked
anyway. Let's make it void.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Vendor H616 DRAM code always configure part which we call ODT
configuration. Let's reflect that here too.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Vendor DRAM settings use TPR10 parameter to enable various features.
There are many mores features that just those that are currently
mentioned. Since new will be added later and most are not known, let's
reuse value from vendor DRAM driver as-is. This will also help adding
support for new boards.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
While ODT values for same memory type are similar, they are not
necessary the same. Let's parameterize them and make parameter same as
in vendor DRAM settings. That way it will be easy to introduce new board
support.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fix code style for pointer declaration. This is just cosmetic change to
avoid checkpatch errors in later commits.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Vendor DRAM code actually writes to whole CR register and not just sets
bit 31 in mctl_ctrl_init().
Just to be safe, do that here too.
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
regulator exists in its device tree. Add the regulator, so USB will
continue to work when the PHY driver switches to using the regulator
uclass instead of a GPIO.
Update the device tree here because it does not exist in Linux.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add all the i2c nodes for each family, and add specific i2c
overwrites in the related board-specific dts.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
This driver is actually used for powerpc and m68k/ColdFire.
On ColdFire SoC's, interrupt flag get not set if IIEN flag (mbcr bit6,
interrupt enabled) is not set appropriately before each transfert.
As a result, the transfert hangs forever waiting for IIEN.
This patch set IIEN before each transfert, while considering this fix
as not harming powerpc arch.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
- improve tegra DC driver to work with panel ops and implement
native 180 degree panel rotation support
- add T30 support to tegra DC driver
- add DSI driver (based on mainline Linux one with minor
adjustments, only T30 tested)
- add get_display_timing ops to simple panel driver
- extend simple panel driver to use it for MIPI DSI panels
which do not require additional DSI commands for setup
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Merge tag 'video-20230407' of https://source.denx.de/u-boot/custodians/u-boot-video
- fix building sandbox without SDL
- improve tegra DC driver to work with panel ops and implement
native 180 degree panel rotation support
- add T30 support to tegra DC driver
- add DSI driver (based on mainline Linux one with minor
adjustments, only T30 tested)
- add get_display_timing ops to simple panel driver
- extend simple panel driver to use it for MIPI DSI panels
which do not require additional DSI commands for setup
Adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features
like ganged mode won't work. Driver is heavily based on
mainline Tegra DSI and re-uses much of its features.
Only T30 is supported for now but T20 support can be added
if any supported devices will be found.
Driver is wrapped as panel driver since Tegra DC driver supports
only panel drivers calls.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Internal video devices like DSI and HDMI controllers
require sending commands into DC register field.
To make this available, lets create platform data,
which is restricted to pass DC regmap only to
pre-defined devices.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
On popular request make the display driver from T20 work on T30 as
well. Turned out to be quite straight forward. However a few notes
about some things encountered during porting: Of course the T30 device
tree was completely missing host1x as well as PWM support but it turns
out this can simply be copied from T20. The only trouble compiling the
Tegra video driver for T30 had to do with some hard-coded PWM pin
muxing for T20 which is quite ugly anyway. On T30 this gets handled by
a board specific complete pin muxing table. The older Chromium U-Boot
2011.06 which to my knowledge was the only prior attempt at enabling a
display driver for T30 for whatever reason got some clocking stuff
mixed up. Turns out at least for a single display controller T20 and
T30 can be clocked quite similar. Enjoy.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This is currently broken. If SDL is not installed, SANDBOX_SDL becomes
false and build errors are generated, e.g.:
test/dm/video.c:424: undefined reference to `sandbox_sdl_set_bpp'
Fix it by making the function return an error in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add board code for R8A779G0 V4H White Hawk board.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Synchronize configuration symbols which are now switched to Kconfig
Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
Sort headers, use clrbits_le32(), use BIT macros where appropriate
Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
Add Kconfig entry and PRR ID to support R8A779G0 V4H SoC.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update commit message]
Add DTs for R8A779G0 V4H White Hawk CPU and BreakOut boards.
Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message
Rename DTs to match Linux, which has dash between white-hawk]
Add R8A779G0 V4H DT extras for U-Boot.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update compatible string to match latest upstream]
Add initial DT support for R8A779G0 (R-Car V4H). Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message]
Add board code for R8A779F0 S4 Spider board.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Synchronize configuration symbols which are now switched to Kconfig
Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
Sort headers, use clrbits_le32(), use BIT macros where appropriate
Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
Add Kconfig entry and PRR ID to support R8A779F0 S4 SoC.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update commit message]
Add DTs for R8A779F0 S4 Spider CPU boards and Breakout boards.
Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message]
Add R8A779F0 S4 DT extras for U-Boot.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update compatible string to match latest upstream]
Add initial DT for R8A779F0 S4 SoC. Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message]
This adds R-Car Generation 4 (Gen4) support as Renesas ARM64 SoC.
In this version, reusing R-Car Gen3 lowlevel initialize routine [1]
and R-Car Gen3 memory map tables [2] .
[1] arch/arm/mach-rmobile/lowlevel_init_gen3.S
[2] arch/arm/mach-rmobile/memmap-gen3.c
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: - Enable DTO support by default
- Sort the Kconfig lists
- Select RCAR_64 Kconfig option to pull in all the shared
Kconfig options with Gen3, and use where applicable to
deduplicate entries.
- Fix reference [2] typo in commit message
- Drop config options moved to Kconfig, rename rest to CFG_
accordingly to synchronize with upstream changes. Drop
removed CONFIG_VERY_BIG_RAM.
- Move board size limit to arch/Kconfig
- Move GICR_BASE to headers instead of common config]
The assembly for __gnu_thumb1_case_si was taken from upstream gcc and adapted
as width suffix was removed for the add instruction [1].
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Tested-by: Tony Dinh <mibodhi@gmail.com>
[1] 4f181f9c7e/libgcc/config/arm/lib1funcs.S (L2156)
Acked-by: Pali Rohár <pali@kernel.org>
Acked-by: Tony Dinh <mibodhi@gmail.com>
On mpc832x, SPI can be either handled by CPU or QE.
In order to work in CPU mode, bit 17 of SPMODE has to
be set to 1, that bit is called OP.
Also, data is located at a different place than the one expected
by the driver today. In 8 bits mode with REV set, data to be
transmitted is located in the most significant byte while
received data is located in second byte. So perform the
necessary shifts.
In order to differentiate with other CPUs, a new compatible is
added for mpc832x: fsl,mpc832x-spi
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The mpc832x has GPIOs handled by the QUICC Engine.
The registers are different from the one for the
non QE mpc83xx GPIOs.
Implement a GPIO driver for those.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
At startup, some RAM is needed (for instance for stack) before
DRAM is initialised.
One way to offer such RAM, used by mpc83xx, is to lock some entries
in the cache. To do that, MMU needs to be activated.
On mpc83xx having a QUICC Engine an alternative is to user some
part of from the Multi User RAM, like done on mpc8xx for instance.
For that, the MMU is not needed.
Activating the MMU is problematic because exception vectors are not
setup yet so in case of ISI or DSI that CPU will crash and reboot.
At the time being, MMU is activated regardless.
Only activate it when locking cache entries to provide initial RAM.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
There are helpers included in soc.h
Declare them static inline so that soc.h can be
included in several places.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
According to the reference manual, the Reset Configuration
Word Low Register bits 2-3 must be set to 0b10.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Introduce a new compatible "fsl,pq2pro-wdt"
On mpc83xx, the prescaling factor is 0x10000.
Don't write the watchdog configuration register in
start.S as it can be written only once.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
mpc8xx, mpc83xx and mpc86xx have similar watchdog with almost same
memory registers.
Refactor the driver to get the register addresses from the
device tree and use the compatible to know the prescale factor.
Calculate the watchdog setup value from the provided timeout.
Don't declare it anymore as an HW_WATCHDOG, u-boot will start
servicing the watchdog early enough.
On mpc8xx the watchdog configuration register is also used for
configuring the bus monitor. So add it as an option to the watchdog
when it is mpc8xx. When watchdog is not selected, leave the
configuration of the initial SYPCR from Kconfig.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
mpc8xx, mpc83xx and mpc86xx have similar watchdog with almost same
memory registers.
Rename it mpc8xxx which is the generic name used for drivers supporting
several mpc families.
The driver will be made more generic in following patch.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
8xx has CONFIG_8xx_GCLK_FREQ which is similar to
CONFIG_SYS_CLK_FREQ, and doesn't set CONFIG_SYS_CLK_FREQ.
Due to that, get_board_sys_clk() returns 0.
Remove CONFIG_8xx_GCLK_FREQ and use CONFIG_SYS_CLK_FREQ instead.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the serial nodes of the LX2160A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the serial nodes of the LS1088A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Beacon Embedded has an i.MX8M Plus development kit which consists
of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC,
and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual
Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet
PHY. The device trees are already queued for inclusion in Linux 6.3.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for Data Modul i.MX8M Plus eDM SBC board. This is an
evaluation board for various custom display units. Currently
supported are serial console, ethernet, eMMC, SD, SPI NOR, USB.
Signed-off-by: Marek Vasut <marex@denx.de>
Add WDT reboot bindings on DH i.MX6 DHSOM to permit the platform
to reboot via WDT in U-Boot. These are custom U-Boot bindings,
hence they are placed in -u-boot.dtsi .
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
U-Boot can be booted from NAND without SPL by prepending the DCD header to
the actual U-Boot binary. However this requires prepending 1024 bytes to
u-boot.imx (DCD + u-boot.bin).
There is already a similar target to build spl/u-boot-nand-spl.imx, add the
same option for no-SPL boot.
Tested on i.MX6ULL.
The resulting layout of u-boot-nand.imx is:
- Offset 0x0000 (0 KiB): padding
- Offset 0x0400 (1 KiB): DCD header
- Offset 0x1000 (4 KiB): u-boot.bin
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
J721e SK has been broken since at least March 2022.
The main-navss and mcu-navss nodes were renamed and this caused the
A72 SPL to fail early in the boot even before the serial port was
enabled. Fix this.
A later patch series between v2022.07 and v2022.10 additionally broke
boot on this board by introducing hbmc nodes which are not present on
this board. The right fix is to disable these by default in the SOC
dtsi file, but for now we can also disable them in the u-boot dtsi.
With both these fixed, we can now boot the j721e SK board fully from
mainline u-boot.
Fixes: 58d61fb5a7 ("arm: dts: k3-j721e-sk: Add initial A72 specific dts support")
Fixes: 297daac43a ("arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node")
Reported-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
[gadiyar@ti.com: update commit description]
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Cc: Bryan Brattlof <bb@ti.com>
Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.
After the sync with Linux in commit d0399a46e7 ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a boot regression in which the eMMC card cannot be found anymore.
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the eMMC (esdhc3) was
mapped to mmc0.
Fixes: d0399a46e7 ("imx6dl/imx6qdl: synchronise device trees with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
The image size was increased but the firmware-update part was not
updated. Correct this so that VBE firmware update can succeed with
sandbox_vpl.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 85c66dc95c ("sandbox: Expand size for VPL image")
---------------------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
i.MX patches queued for next:
- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
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Merge tag 'u-boot-imx-next-20230331' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
u-boot-imx-next-20230331 for next
---------------------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
i.MX patches queued for next:
- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
The FEC interface mode is now configured in common board_interface_eth_init()
and called by FEC MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
The assigned-clock no longer have to be dropped, the clock are now
defined in clk-imx8mp.c and used by DWMAC driver to configure the
DWMAC clock. Drop the workarounds from U-Boot specific DT extras.
Signed-off-by: Marek Vasut <marex@denx.de>
In order for i2c_num==4 and 5 to stay invalid for non-imx8mp SOCs, the
i2c_ccgr[] array must be sized by the number of initializers present,
not with a hard-coded 6 which would implicitly initialize the last two
elements with zeroes.
Also, the bounds check is off-by-one.
Fixes: c92c3a4453 "ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP"
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.
The adjustment here is modeled after STM32MP15xx clock handling
in this driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK3 carrier board.
Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD,
SPI NOR and USB 3.0 host.
Signed-off-by: Marek Vasut <marex@denx.de>
The PHY nodes may be activated via DTO in case another SoM variant
is populated into the development kit. Do not delete the nodes.
Signed-off-by: Marek Vasut <marex@denx.de>
The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.
Signed-off-by: Marek Vasut <marex@denx.de>
The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux settings for both options, so that DT overlay can override
these settings on SoM variant with the LAN8740Ai PHY.
Signed-off-by: Marek Vasut <marex@denx.de>
The current variant of the SoM has LAN8740Ai PHY connected to EQoS
strapped to MDIO address 0 , adjust the MDIO address to match the
hardware.
Signed-off-by: Marek Vasut <marex@denx.de>
Definitions are according to the MV78460 Hardware Specifications.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value,
which represents in which state BootROM currently is. BootROM fills one
of the possible values: 0x2 (CPU initialization), 0x3 (UART detection),
0x6 (UART booting), 0x8 (PCI Express booting), 0x9 (parallel or SPI NOR
booting), 0xA (parallel or SPI NAND booting), 0xB (SATA booting) and 0xE
(SD / eMMC booting).
Meaning of these values matches TRACE_* macros from Marvell soc_spec.h file:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2013.01-armada-18.06/tools/marvell/doimage_mv/soc_spec.h
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
macro. And also allows to extend other BOOT_FROM_* macros for other
variants.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
A385 BootROM treats strapping configuration 0x22 as SPI-NAND. So remove
incorrect definition 0x22 as SATA. SATA on A385 has configuration 0x2A.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
A385 BootROM treats strapping configuration 0x3f as invalid. When booting
fails (e.g. because of invalid configuration) then BootROM fallbacks to
UART booting.
Detecting BootROM fallback to UART booting is implemented in U-Boot since
commit 2fd4284051 ("ARM: mach-mvebu: handle fall-back to UART boot").
So there is no need to define BOOT_FROM_UART_ALT constant and special
handling for it anymore, remove it.
This change effectively revers commit f3a88e2ca1 ("arm: mvebu: fix boot
from UART on ClearFog Base").
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Show correct information in debug() output and use correct names for variables.
No functional change.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
[upstream of vendor commit 19a96f7c40a8fc1d0a6546ac2418d966e5840a99]
The Clearfog devices have only one SDHC device. This is either eMMC if
it is populated on the SOM or SDHC if not. The Linux device tree assumes
the SDHC case. Detect if the device is an eMMC and fixup the device-tree
so it will be detected by Linux.
Ported from vendor repo at https://github.com/SolidRun/u-boot
Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
A388 Clearfog MMC is either SD Card or eMMC with different behaviour for
both. Setting the device to non-removable in the u-boot.dtsi allows both
to correctly detect the device.
Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.
After the sync with Linux in commit d0399a46e7 ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a boot regression in which the eMMC card cannot be found anymore.
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the eMMC (esdhc3) was
mapped to mmc0.
Fixes: d0399a46e7 ("imx6dl/imx6qdl: synchronise device trees with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
The OEM Secure World Closed is not a valid lifecycle on iMX8ULP/iMX9.
So remove it from lifecycle print.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Before moving the lifecycle to OEM closed, confirm the lifecycle is
OEM open, otherwise cancel to move forward the lifecycle.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Remove legacy command definitions, change to use new ELE_xxx command
request.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since
both of them use same sentinel ELE APIs
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add get_events API to retrieve any singular events that has occurred
since the FW has started from sentinel
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting. So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.
We have to configure necessary PDAC and MSC for SPL before DDR
initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To clean the upower codes by aligning codes format, check err_code
and add detail bits list for the memory magic number
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The swton indicates the logic switch, magic number 0xfff80 is hard
to understand, so use macro.
Some board design may not have MIPI_CSI voltage input connected per
data sheet. In that case, the upower power on API may dead loop mu to wait
response, however there is no response. So remove MIPI_CSI here, let
linux power domain driver to runtime enable the power domain.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Need to add DRAM access permission for S400, as S400 needs to access
it When SPL calls image authentication
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.
The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.
The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
As M33 is responsible for TRDC configuration, the settings for A35
nonsecure world access and DMA0 access are moved to M33 image.
So remove the codes to release TRDC and configure it. Just keep
the configurations for reference.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since A1 ROM has fixed the ROM API eMMC issue, we should only use
the workaround for A0.1 part. Add a SOC revision check.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since latest DTS has added multiple MU nodes, using compatible
string to find the device node is not proper. It finds the first
node with the compatible string matched even the node is disabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
Last use of CONFIG_SYS_GPIO1_PRELIM was removed by
commit fae2ea5951 ("ppc: Remove MPC8349EMDS board and ARCH_MPC8349
support").
Last use of CONFIG_SYS_GPIO2_PRELIM was removed even before by
commit 6843862342 ("ppc: Remove caddy2 / vme8349 boards")
Those two items were removed from whitelist by
commit 8cca60a2cb ("Kconfig: Remove some symbols from the whitelist")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Fixes: fae2ea5951 ("ppc: Remove MPC8349EMDS board and ARCH_MPC8349 support")
Last (incorrect) use of those CONFIG items was removed by
commit 9fd9abedcc ("TQM834x: remove defines causing gcc4.4 warnings")
Those items are invalid and should have been removed at the
same time because lblaw[] has only 4 elements.
And they were removed from the whitelist by
commit 9c5df7a2a9 ("mpc83xx: Migrate LBLAW_* to Kconfig")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Fixes: 9fd9abedcc ("TQM834x: remove defines causing gcc4.4 warnings")
For non TI boards it is not possible to enable the do_board_detect()
call as TI_I2C_BOARD_DETECT is defined in board/ti/common/Kconfig.
I want to use do_board_detect() to dectect boards and properties based
on some SPI communication with a FPGA.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The M.2 slots of the related IOT2050 variant need to be configured
according to the plugged cards. This tries to detect the card using the
M.2 configuration pins of the B-key slot. If that fails, a U-Boot
environment variable can be set to configure manually. This variable is
write-permitted also in secure boot mode as it is not able to undermine
the integrity of the booted system.
The configuration is then applied to mux the serdes and to fix up the
device tree passed to or loaded by the bootloader. The fix-ups are
coming from device tree overlays that are embedded into the firmware
image and there also integrity protected. The OS remains free to load
a device tree to which they do not apply: U-Boot will not fail to boot
in that case.
Based on original patch by Chao Zeng.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Add support for the M.2 board based on the iot2050 advanced board.
The board has two m.2 connectors, one is B-keyed, the other E-keyed.
The B-key slot can connect 5G/SSD devices, and E-key can be used for
WIFI/BT devices.
This variant is covered by PG2 firmware image.
Signed-off-by: chao zeng <chao.zeng@siemens.com>
[Jan: align DT to kernel, polish wording]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Use external blob otpcmd.bin to replace the 0xff filled OTP programming
command block to create a firmware image that provisions the OTP on
first boot. This otpcmd.bin is generated from the customer keys using
steps described in the meta-iot2050 integration layer for the device.
Based on original patch by Baocheng Su.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Add hashes and configuration signature stubs to prepare verified boot
of main U-Boot by SPL.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The latest version of the binary-only firmware parts come in a combined
form of FSBL and sysfw containers. This implies some layout changes to
the generated firmware image but also makes handling of artifacts much
simpler (4 files less). The env locations will not change, just the
space reserved for U-Boot will shrink from 4 to 3 MB - still plenty of
space left in practice.
Adjust configuration and documentation accordingly.
Along this change, add a new reservation for update commands of the
user-controlled OTP part. A specific userspace tool will fill it, and
the FSBL will evaluate it during boot. This reservation will use 64K of
the former sysfw section.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Refactor according to the entry `fit: Entry containing a FIT` of
document tools/binman/README.entries.
As the generator uses the device tree name for the config description,
board_fit_config_name_match requires a small adjustment as well.
Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[Jan: re-add now required CONFIG_OF_LIST, update config matching]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Due to different signature keys, the PG1 and the PG2 boards can no
longer use the same FSBL (tiboot3). This makes it impossible anyway to
maintaine a single flash.bin for both variants, so we can also split the
build.
A new target is added to indicates the build is for PG1 vs. PG2 boards.
Hence now the variants have separated defconfig files.
The runtime board_is_sr1() check does make no sense anymore, so remove
it and replace with build time check.
Documentation is updated accordingly. New binary artifacts are already
available via meta-iot2050.
Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[Jan: refactor config option into targets, tweak some wordings]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
After the conversion to DM_SERIAL in commit 01f372d8d6 ("udoo_neo:
Select DM_SERIAL and drop iomux board level init") the SPL log is gone
and the U-Boot proper log becomes incomplete:
Core: 80 devices, 18 uclasses, devicetree: separate
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial@2020000
Out: serial@2020000
Err: serial@2020000
Net: eth0: ethernet@2188000
Hit any key to stop autoboot: 0
Introduce the u-boot.dtsi file that passes the u-boot,dm-pre-reloc
properties to the relevant nodes so that UART can be used early in SPL.
With this change, the complete SPL and U-Boot messages are seen again.
Signed-off-by: Fabio Estevam <festevam@denx.de>
While this change is correct for v2023.04 it is not correct for next
(where this is right now) nor post-v2023.04.
This reverts commit 8653e5d3b7.
Signed-off-by: Tom Rini <trini@konsulko.com>
When we do not enable DISTRO_DEFAULTS (generally, to get distro_bootcmd)
we instea do want to imply BOOTSTD_DEFAULTS so that when using bootstd
the general distro boot functionality will still work.
Signed-off-by: Tom Rini <trini@konsulko.com>
These board have moved to standard boot but the old 'distro_bootcmd'
command is still active. Disable DISTRO_DEFAULTS to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: e23cae3080 ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: 5d1c8342ae ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: 388f93f963 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: f38be30868 ("x86: bayleybay: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Add documentation on how to make this change safely.
Fixes: 66e2c665f3 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Documenation:
* add man-page for efi command
UEFI:
* Let EFI app call ExitBootServices() before legacy booting kernel
* Support zboot and bootm in the EFI app
* Let efi command show configuration tables
* Support booting a 64-bit kernel from 64-bit EFI app
* Allocate device-tree copy from high memory
* simplify efi_str_to_u16()
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Merge tag 'efi-next-20230325' of https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request for efi-next-20230325
Documenation:
* add man-page for efi command
UEFI:
* Let EFI app call ExitBootServices() before legacy booting kernel
* Support zboot and bootm in the EFI app
* Let efi command show configuration tables
* Support booting a 64-bit kernel from 64-bit EFI app
* Allocate device-tree copy from high memory
* simplify efi_str_to_u16()
When running the EFI app, we need to exit boot services before jumping
to Linux.
At some point it may be possible to jump to Linux and pass on the system
table, and:
* install the device-tree as configuration table
* use LoadImage() to load the kernel image (e.g. from memory)
* start the image with StartImage()
This should allow the Linux efistub to be used. For now, this is not
implemented.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add the missing code to handle this. For a 64-bit kernel the entry
address is 0x200 bytes after the normal entry.
Rename the parameter to boot_linux_kernel() accordingly. Update the
comments to indicate that these are addresses, not pointers.
Signed-off-by: Simon Glass <sjg@chromium.org>
The U-Boot EFI app can run as a 64-bit program, so set the Kconfig
correctly in that case. Make sure it doesn't build SPL, since there is
no need to switch from 32 to 64 bit when running.
Signed-off-by: Simon Glass <sjg@chromium.org>
- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.
Leverage this ability if the firmware supports it.
Adapted from the following raspberrypi Linux kernel commit:
bcm2835-sdhost: Firmware manages the clock divisor
08532d242d
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
In rpi-firmware 25e2b597ebfb2495eab4816a276758dcc6ea21f1,
the GET_CLOCK_RATE mailbox property was changed to return the last
value set by SET_CLOCK_RATE.
https://github.com/raspberrypi/firmware/issues/1619#issuecomment-917025502
Due to this change in firmware behavior, bcm2835_get_mmc_clock now
returns a clock rate of zero since we do not issue SET_CLOCK_RATE.
This results in degraded MMC performance.
SET_CLOCK_RATE fixes the clock to a specific value and disables scaling
so is not an ideal solution.
Instead, fallback to GET_MAX_CLOCK_RATE in bcm2835_get_mmc_clock if
GET_CLOCK_RATE returns zero.
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Same change as was done for mvebu in commit 5bb2c550b1 ("arm: mvebu: Move
internal registers in arch_very_early_init() function") but for kirkwood.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
CONFIG_SF_DEFAULT_SPEED is used in SPL SPI to configure and probe the
flash device during DM SPI uclass probing process, if the
spi-max-frequency is not available in the DTB. Currently the max
frequency is not available, because of the probing mechanism in SPI
uclass has not been fully updated to DM.
The CONFIG_SF_DEFAULT_SPEED is set to 1Mhz if a board defconfig
does not specify it. This speed is too slow and result in a few
seconds delay while the u-boot image is loaded from flash. Based on a
survey of the device tree specifications for MVEBU boards, a sane default
value should be 10Mhz. The default of 10Mhz enables an almost
instantaneously loading of the u-boot image.
Note that this patch depends on this patch series (has been merged to
u-boot-marvell/next):
https://lists.denx.de/pipermail/u-boot/2023-March/511038.html
- RESEND: correct spelling of SF_DEFAULT_MODE
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
We did not add a prototype for spl_mmc_get_uboot_raw_sector to
include/spl.h before, so add and document one now. Correct the incorrect
prototype in board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c and
ensure that we have spl.h where we define a non-weak
spl_mmc_get_uboot_raw_sector as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Some platforms were not including <cpu_func.h> which sets the prototype
for reset_cpu, and in turn had it set wrong. Correct these cases.
Signed-off-by: Tom Rini <trini@konsulko.com>
On high security devices, ROM enables firewalls to protect the OCSRAM
region access during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.
So, move scratch board area to HSM RAM.
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
To make sure the panic and the reset messages will go out, console flush() should be used.
Sleep periods do not work in early u-boot phase when timer driver is not initialized yet.
Reference: https://lists.denx.de/pipermail/u-boot/2023-March/512233.html
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
The Rockchip timer driver has been renamed after the fall back compatible.
There's no need to replace the timer compatible in rk3188-radxarock-u-boot.dtsi
anymore, so remove.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
