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arch: m68k: Use existing CONFIG_MCFTMR instead of CFG_MCFTMR

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There is an existing CONFIG_MCFTMR Kconfig symbol,
use it and drop all other instances of CFG_MCFTMR.
This duality is likely a result of bogus conversion
to Kconfig.

Fixes: 7ff7b46e6c ("m68k: rename CONFIG_MCFTMR to CFG_MCFTMR")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2023-03-23 01:20:39 +01:00 committed by Angelo Dureghello
parent 12c1e57824
commit 35d48ea8c0
24 changed files with 26 additions and 40 deletions
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1
arch/m68k/Kconfig
View file

@ -200,5 +200,6 @@ source "board/sysam/stmark2/Kconfig"
config MCFTMR
bool "Use DMA timer"
default y
endmenu

2
arch/m68k/cpu/mcf523x/interrupts.c
View file

@ -22,7 +22,7 @@ int interrupt_init(void)
return 0;
}
#if defined(CFG_MCFTMR)
#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

12
arch/m68k/cpu/mcf52x2/interrupts.c
View file

@ -34,7 +34,7 @@ int interrupt_init(void)
return 0;
}
#if defined(CFG_MCFTMR)
#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
@ -42,7 +42,7 @@ void dtimer_intr_setup(void)
clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
}
#endif /* CFG_MCFTMR */
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
@ -63,7 +63,7 @@ int interrupt_init(void)
return 0;
}
#if defined(CFG_MCFTMR)
#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
@ -72,7 +72,7 @@ void dtimer_intr_setup(void)
clrbits_be32(&intp->imrl0, 0x00000001);
clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
}
#endif /* CFG_MCFTMR */
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@ -83,11 +83,11 @@ int interrupt_init(void)
return 0;
}
#if defined(CFG_MCFTMR)
#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
}
#endif /* CFG_MCFTMR */
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5249 || CONFIG_M5253 */

2
arch/m68k/cpu/mcf532x/interrupts.c
View file

@ -23,7 +23,7 @@ int interrupt_init(void)
return 0;
}
#if defined(CFG_MCFTMR)
#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

2
arch/m68k/cpu/mcf5445x/interrupts.c
View file

@ -26,7 +26,7 @@ int interrupt_init(void)
return 0;
}
#if defined(CFG_MCFTMR)
#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

24
arch/m68k/include/asm/immap.h
View file

@ -16,7 +16,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@ -38,7 +38,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@ -63,7 +63,7 @@
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
@ -86,7 +86,7 @@
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
@ -105,7 +105,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@ -130,7 +130,7 @@
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
#define CFG_SYS_TMR_BASE (MMAP_TMR3)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
@ -152,7 +152,7 @@
#define CFG_SYS_NUM_IRQS (192)
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@ -174,7 +174,7 @@
#define CFG_SYS_NUM_IRQS (128)
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@ -196,7 +196,7 @@
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
@ -217,7 +217,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@ -239,7 +239,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@ -269,7 +269,7 @@
#define MMAP_DSPI MMAP_DSPI0
/* Timer */
#ifdef CFG_MCFTMR
#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)

4
arch/m68k/lib/time.c
View file

@ -25,7 +25,7 @@ static volatile ulong timestamp = 0;
#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif
#if defined(CFG_MCFTMR)
#if CONFIG_IS_ENABLED(MCFTMR)
#ifndef CFG_SYS_UDELAY_BASE
# error "uDelay base not defined!"
#endif
@ -111,7 +111,7 @@ ulong get_timer(ulong base)
return (timestamp - base);
}
#endif /* CFG_MCFTMR */
#endif /* CONFIG_MCFTMR */
/*
* This function is derived from PowerPC code (read timebase as long long).

2
board/freescale/m53017evb/README
View file

@ -87,7 +87,7 @@ CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CFG_MCFTMR -- define to use DMA timer
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged

2
board/freescale/m5373evb/README
View file

@ -86,7 +86,7 @@ CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CFG_MCFTMR -- define to use DMA timer
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged

1
include/configs/M5208EVBE.h
View file

@ -111,6 +111,5 @@
#define CFG_SYS_CS0_MASK 0x007F0001
#define CFG_SYS_CS0_CTRL 0x00001FA0
#define CFG_MCFTMR
#endif /* _M5208EVBE_H */

1
include/configs/M5235EVB.h
View file

@ -130,6 +130,5 @@
# define CFG_SYS_CS0_CTRL 0x00001D80
#endif
#define CFG_MCFTMR
#endif /* _M5329EVB_H */

1
include/configs/M5249EVB.h
View file

@ -120,6 +120,5 @@
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_MCFTMR
#endif /* M5249 */

1
include/configs/M5253DEMO.h
View file

@ -132,6 +132,5 @@
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_MCFTMR
#endif /* _M5253DEMO_H */

1
include/configs/M5272C3.h
View file

@ -107,6 +107,5 @@
#define CFG_SYS_PBDAT 0x0000
#define CFG_SYS_PDCNT 0x00000000
#define CFG_MCFTMR
#endif /* _M5272C3_H */

1
include/configs/M5275EVB.h
View file

@ -116,6 +116,5 @@
#define CFG_SYS_CS1_CTRL 0x00001900
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_MCFTMR
#endif /* _M5275EVB_H */

1
include/configs/M5282EVB.h
View file

@ -127,6 +127,5 @@
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
#define CFG_MCFTMR
#endif /* _CONFIG_M5282EVB_H */

1
include/configs/M53017EVB.h
View file

@ -132,6 +132,5 @@
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x00001FA0
#define CFG_MCFTMR
#endif /* _M53017EVB_H */

1
include/configs/M5329EVB.h
View file

@ -138,6 +138,5 @@
#define CFG_SYS_CS2_CTRL 0x00001f60
#endif
#define CFG_MCFTMR
#endif /* _M5329EVB_H */

1
include/configs/M5373EVB.h
View file

@ -136,6 +136,5 @@
#define CFG_SYS_CS2_MASK (16 << 20)
#define CFG_SYS_CS2_CTRL 0x00001f60
#define CFG_MCFTMR
#endif /* _M5373EVB_H */

1
include/configs/amcore.h
View file

@ -10,7 +10,6 @@
#define CFG_SYS_UART_PORT 0
#define CFG_MCFTMR
#define CFG_SYS_UART_PORT 0
#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }

1
include/configs/astro_mcf5373l.h
View file

@ -184,6 +184,5 @@
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
#define CFG_MCFTMR
#endif /* _CONFIG_ASTRO_MCF5373L_H */

1
include/configs/cobra5272.h
View file

@ -184,6 +184,5 @@ configuration */
#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
#define CFG_MCFTMR
#endif /* _CONFIG_COBRA5272_H */

1
include/configs/eb_cpu5282.h
View file

@ -138,7 +138,6 @@
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
#define CFG_MCFTMR
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/

1
include/configs/stmark2.h
View file

@ -95,7 +95,6 @@
#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 12)
#define CFG_MCFTMR
#define CFG_SYS_I2C_0