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On mpc832x, SPI can be either handled by CPU or QE. In order to work in CPU mode, bit 17 of SPMODE has to be set to 1, that bit is called OP. Also, data is located at a different place than the one expected by the driver today. In 8 bits mode with REV set, data to be transmitted is located in the most significant byte while received data is located in second byte. So perform the necessary shifts. In order to differentiate with other CPUs, a new compatible is added for mpc832x: fsl,mpc832x-spi Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk> |
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| arc | ||
| arm | ||
| m68k | ||
| microblaze | ||
| mips | ||
| nios2 | ||
| powerpc | ||
| riscv | ||
| sandbox | ||
| sh | ||
| x86 | ||
| xtensa | ||
| .gitignore | ||
| Kconfig | ||
| Kconfig.nxp | ||
| u-boot-elf.lds | ||