Current u-boot top of tree builds with warnings/errors for
the following boards:
ads5121 cpci5200 mecp5200 v38b IAD210 MBX MBX860T NX823
RPXClassic debris PN62
following patch solves this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
On boards which have the environment in eeprom, i2c_init() is called
before the console and RAM are initialized.
Suppress printfs until the console is initialized.
Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
When initializing the core clocks, stick external memory into self-refresh.
This gains us a few cool things:
- support suspend-to-RAM with Linux
- reprogram clocks automatically when doing "go" on u-boot.bin in RAM
- make sure settings are stable before flashing new version
- finally fully unify initialize startup code path between LDR/non-LDR
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some newer Blackfins (like the BF51x) do not have an on-chip voltage
regulator, so do not attempt to program the memory as if it does.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If the board config does not specify an explicit EBIU_SDBCTL value, set it
up with sane values based on other configuration options.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Workaround anomaly 432:
The bfrom_SysControl() firmware function does not clear the SIC_IWR1
register before executing the PLL programming sequence. Therefore, any
interrupt enabled in the SIC_IWR1 register prior to the call to
bfrom_SysControl() can prematurely terminate the idle sequence required
for the PLL to relock properly. SIC_IWR0 is properly handled.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Boot ROM uses EVT1 as the entry point so set that rather than having
to use a tiny jump block in the default EVT1 location.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The jtag tstc operation was checking the hardware to see if data is
available from it (which is fine for the jtag getc operation), but the
higher layers need to know whether any data is available. Since we have
to read up to 4 bytes at a time from the hardware, the higher layers need
to know they can consume the cached bytes as well.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed.
The AT91SAM9G20-EK board is an updated revision of the AT91SAM9260-EK board.
It is essentially the same, with a few minor differences.
Here is the chip page on Atmel website:
http://www.atmel.com/dyn/products/product_card.asp?part_id=4337
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Remove this code. It's not needed. The 4xx EMAC driver stores the MAC
addresses into the SoC registers instead.
Signed-off-by: Stefan Roese <sr@denx.de>
Moved sub-features of the SC520 code which is currently selectively compiled
using #ifdef out of sc520.c into individual files selectively compiled via
the makefile
Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
Rewrite interrupt handling functionality for the i386 port. Separated
functionality into separate CPU and Architecture components.
It appears as if the i386 interrupt handler functionality was intended
to allow multiple handlers to be installed for a given interrupt.
Unfortunately, this functionality was not fully implemented and also
had the problem that irq_free_handler() does not allow the passing
of the handler function pointer and therefore could never be used to
free specific handlers that had been installed for a given IRQ.
There were also various issues with array bounds not being fully
tested.
I had two objectives in mind for the new implementation:
1) Keep the implementation as similar as possible to existing
implementations. To that end, I have used the leon2/3
implementations as the reference
2) Seperate CPU and Architecture specific elements. All specific i386
interrupt functionality is now in cpu/i386/ with the high level
API and architecture specific code in lib_i386. Functionality
specific to the PC/AT architecture (i.e. cascaded i8259 PICs) has
been further split out into an individual file to allow for the
implementation of the PIC architecture of the SC520 CPU (supports
more IRQs)
Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script. Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.
However, '*(.rodata*)' by itself will result in sub-optimal section
ordering. The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file. This is easy to fix by using the
SORT_BY_ALIGNMENT command.
This patch has not be tested one most of the boards modified. Some boards
have a linker script that looks something like this:
*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)
I change this to:
*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.
The resulting code can also be simplified even further.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Stefan Roese <sr@denx.de>
CC: Ben Warren <biggerbadderben@gmail.com>
The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.
The cpus that get converted here:
at91rm9200
mpc512x
mpc5xxx
mpc8260
mpc8xx
ppc4xx
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: John Rigby <jrigby@freescale.com>
CC: Stefan Roese <sr@denx.de>
PCI outbound address map configuration doesn't match the
PCI memory address range covered by appropriate TLB entry
configuration for canyonlands causing machine check
exceptions while accessing PCI memory regions. This patch
provides a fix for this issue.
Kazuaki Ichinohe observed and reported this issue while
testing display output with PCI ATI video card on canyonlands.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Total5200 and digsy MTC use I2C port 2 pins as a ATA chip select.
To avoid adding board-specific ifdefs to cpu/mpc5xxx/ide.c new
define CONFIG_SYS_ATA_CS_ON_I2C2 was introduced. It is used by
Total5200 and will be used by digsy MTC and other boards with
ATA CS on I2C pins.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
The serial boot dram extended/standard mode register was not
setup and was using default DRAM setup causing the U-boot was
unstable to boot up in serial mode.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
According to coldfire manual data timeout > address time out
also use correct macro to program XARB_CFG
Signed-off-by: Arun C <arunedarath@mistralsolutions.com>
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.
Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU.
The bootcounter uses 8 bytes from the muram,
because no other memory was found on this
CPU for the bootcount feature. So we must
correct the muram size in DTS before booting
Linux.
This feature is actual only implemented for
MPC8360, because not all 83xx CPU have qe,
and therefore no muram, which this feature
uses.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
1. RD_TO_PRE missed to add the AL, and need min 2 clocks for
tRTP according to DDR2 JEDEC spec.
2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec.
3. add the support of DDR2-533,667,800 DIMMs
4. cpo
5. make the AL to min to gain better performance.
The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.
items 1, 2 and 5:
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
We should use pci_last_busno() in pci_init_bus(), otherwise we'll
erroneously re-use PCI0's first_busno for PCI1 hoses.
NOTE: The patch is untested. All MPC83xx FSL boards I have have
PCI1 in miniPCI form, for which I don't have any cards handy.
But looking in cpu/mpc85xx/pci.c:
...
#ifdef CONFIG_MPC85XX_PCI2
hose = &pci_hose[1];
hose->first_busno = pci_hose[0].last_busno + 1;
And considering that we do the same for MPC83xx PCI-E support,
I think this patch is correct.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fixes copy-paste issue: pci_hose[0]'s first and last
busnos were used to fixup pci1's nodes.
We don't see this bug triggering only because Linux reenumerate
buses anyway.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fixes an issue in config space read accessors: we should
fill-in the value even if we fail (e.g. skipping devices), otherwise
CONFIG_PCI_SCAN_SHOW reports bogus values during boot up.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Currently we assign first_busno = 0 for the first PCIe hose, but this
scheme won't work if we have ordinary PCI hose already registered (its
first_busno value is 0 too).
The old code worked fine only because we have PCI disabled on
MPC837XEMDS boards in stand-alone mode (see commit 00f7bbae92
"mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards").
But on MPC837XERDB boards we have PCI and PCIe, so the bug actually
triggers.
So, to fix the issue, we should use pci_last_busno() + 1 for the
first_busno (i.e. last available busno).
Reported-by: Huang Changming <Chang-Ming.Huang@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The AT32UC3A series of processors doesn't contain any cache, and issuing
cache control instructions on those will cause an exception. This commit
makes cacheflush.h arch-dependent in preparation for the AT32UC3A-support.
Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com>
Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com>
Signed-off-by: Olav Morken <olavmrk@gmail.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This patch adds OMAP3 cpu type auto detection based on OMAP3 register
and removes hardcoded values.
Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Looks like the initcode updates fell out of order during my merges. The
patch that really fixes up this code is part of power-on overhaul and so
is too large for merging at this point. Instead, we can disable the code
as no currently in-tree board depends on it. The next merge window will
fix things up properly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
In the commit 79b51ff820 ([MIPS] cpu/mips/
Makefile: Split [CS]OBJS onto separate lines), I wrongly deleted a START
line. This patch puts it back.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Fixing the get_timer function to return time in miliseconds instead of
ticks. Also fixed PXA boards to use the conventional value of 1000 for
CONFIG_SYS_HZ.
Signed-off-by: Micha Kalfon <smichak.uv@gmail.com>
The current MMC infrastructure relies on the existence of an
arch-specific header file. This isn't necessary, and a couple
drivers were forced to implement dummy files to meet this requirement.
Instead, we move the stuff in those header files into a more appropriate
place, and eliminate the stubs and the #include of asm/arch/mmc.h
Signed-off-by: Andy Fleming <afleming@freescale.com>
This errata fix is required for 32 bit DDR2 controller on 8572.
May also be required for P10XX20XX platforms
Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
Update the 86xx reset sequence to try executing a board-specific reset
function. If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report
an error and hang. Instead of doing that since DDR is mapped in the
lowest priority LAWs we setup the DDR controller and the max amount
of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If we only have one controller we can completely ignore how
memctl_intlv_ctl is set. Otherwise other levels of code get confused
and think we have twice as much memory.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2
initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END
and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits.
Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The criteria of the AMCC SDRAM Controller DDR autocalibration
U-Boot code is to pick the largest passing write/read/compare
window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
Cycle Select value.
On some Kilauea boards the DDR autocalibration algorithm can
find a large passing write/read/compare window with a small
SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
value "T1 Sample".
This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
"T1 Sample" proves to be to aggressive when later on U-Boot
relocates into DDR memory and executes.
The memory traces on the Kilauea board are short so on some
Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
value of "T1 Sample" shows up as a potentially valid value for
the DDR autocalibratiion algorithm.
The fix is to define a weak default function which provides
the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
to accept for DDR autocalibration. The default will be the
"T2 Sample" value. A board developer who has a well defined
board and chooses to be more aggressive can always provide
their own board specific string function with the more
aggressive "T1 Sample" value or stick with the default
minimum SDRAM_RDCC.[RDSS] value of "T2".
Also put in a autocalibration loop fix for case where current
write/read/compare passing window size is the same as a prior
window size, then in this case choose the write/read/compare
result that has the associated smallest RDCC T-Sample value.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
With this option it is possible to allow the receive
buffer for the SMC on 8xx to be greater then 1. In case
CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
old version.
When defining CONFIG_SYS_SMC_RXBUFLEN also
CONFIG_SYS_MAXIDLE must be defined to setup the maximum
idle timeout for the SMC.
Signed-off-by: Heiko Schocher <hs@denx.de>
This fixes MPC8260 compilation with ethernet on SCC. Probably was a
typo or something...
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
With this option it is possible to allow the receive
buffer for the SMC on 82xx to be greater then 1. In case
CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
old version.
When defining CONFIG_SYS_SMC_RXBUFLEN also
CONFIG_SYS_MAXIDLE must be defined to setup the maximum
idle timeout for the SMC.
Signed-off-by: Heiko Schocher <hs@denx.de>
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent
between the two current users (lib_ppc/board.c, 44x SPD DDR2).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
can be confusing when reading the code.
Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
for system memory mapping purposes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
M5271 dynamic clock multiplier. It is currently fixed at 100MHz.
Allow the board header file to set their own multiplier and divider.
Added the #define for the multiplier and divider to the cpu header file.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Discontinue the use of CONFIG_SYS_FECI2C (only used by M5271EVB).
Use read-modify-write to activate the FEC pins without disabling I2C.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Added the CONFIG_M5271 to the list of Coldfire V2 processor. This
was causing the bus clock (not CPU clock) to be declared twice as
fast as it actually is. This causes UARTS to operate at half the
specified baudrate.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
On some platforms PCIE support is not required, but would be included
because the cpu supports it. To reduce fooprint it is now configurable
via CONFIG_PCI_DISABLE_PCIE.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch updates the fdt UART clock fixup code to
only touch CPU internal UARTs on 4xx systems.
Only these UARTs are definitely clocked by gd->uart_clk.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Previously, booting over the UART required the baud rate to be known ahead
of time. Using a bit of tricky simple math, we can calculate the new board
rate based on the old divisors.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Newer Blackfin boot roms support using the fast SPI read command rather than
just the slow one. If the functionality is available, then use it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some bits of the DDR MMRs should not be set. If they do, bad things may
happen (like random failures or hardware destruction).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Newer Blackfin's have an on-chip rom with a syscontrol() function that needs
to be used to properly program the memory and voltage settings as it will
include (possibly critical) factory tested bias values.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
IIM (IC Identification Module) is the fusebox for the mpc5121.
Use #define CONFIG_IIM to turn on the clock for this module
use #define CONFIG_CMD_FUSE to add fusebox commands.
Fusebox commands include the ability to read
the status, read the register cache, override the register cache,
program the fuses and sense them.
Signed-off-by: Martha Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
Take the cache flush functions from the kernel as they use hardware loops in
order to get optimal performance.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Start building all Blackfin boards with -ffunction-sections/-fdata-sections
and linking with --gc-sections.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
instead the board will have to load it from flash or ram
which will be specified by npe_ucode env var
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Rather than forcing people to define a custom "LITTLEENDIAN", just use the
__LITTLE_ENDIAN one from the Linux byteorder headers that every arch is
already setting up.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Some devices have no UART device pulled out, so allow people to disable the
driver completely in favor of other methods (like JTAG-console).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin JTAG has the ability to pass data via a back-channel without
halting the processor. Utilize that channel to emulate a console.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Make sure we save the value of RETX at power on and then pass it on to the
kernel so that it can nicely debug a "double-fault-caused-a-reset" crash.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
People often ask questions about the init process and when things go
from flash to relocated base, so clarify the comments a bit.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
As pointed out by Ivan Koryakovskiy, the initialization code was not
actually respecting the CONFIG_CLKIN_HALF option when configuring the
PLL_CTL register.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current Blackfin i2c driver does not work properly with certain devices
due to it breaking up transfers incorrectly. This is a rewrite of the
driver and relocates it to the newer place in the source tree.
Also remove duplicated I2C speed defines in Blackfin board configs and
disable I2C slave address usage since it isn't implemented.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Our dcache invalidate function doesn't just invalidate, it also flushes.
So rename the function accordingly and fix the dma_memcpy() function so it
doesn't inadvertently corrupt the data destination.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Remove command name from all command "usage" fields and update
common/command.c to display "name - usage" instead of
just "usage". Also remove newlines from command usage fields.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This patch adds flush_/invalidate_dcache_range() to the MIPS architecture.
Those functions are needed for the upcoming dcache support for the USB
EHCI driver. I chose this API because those cache handling functions are
already present in the PPC architecture.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Added support for a second memory bank to DDR autodetection for 440
platforms.
Made hardcoded values configurable.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This change is needed for mgcoge because it uses two ethernet drivers.
Add a check for the presence of the PIGGY board on mgcoge. Without this
board networking cannot work and the initialization must be aborted.
Only allocate rtx once to prevent DPRAM exhaustion.
Initialize ether_scc.c and the keymile-specific HDLC driver (to be added
soon) in eth.c.
Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
sh_eth used old network API. This patch changed new API.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The NMDK8815 board is distributed by ST Microelectornics.
Other (proprietary) code must be run to unlock the CPU before
U-Boot runs. doc/README.nmdk8815 outlines the boot sequence.
This is the initial port, with basic infrastructure and
a working serial port.
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reset function specific to AMD SC520 microcontroller - Is more of a
'hard reset' that the triple fault.
Requires CONFIG_SYS_RESET_SC520 to be defined in config
I would have liked to add this to a new file (cpu/i386/sc520/reset.c)
but ld requires that a object file in a library arhive MUST contain
at least one function which does not override a weak function (and is
called from outside the object file) in order for that object file to
be extracted from the archive. This would be the only function on the
new file, and hence, will never get linked in.
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Moved from interrupts.c to cpu.c and made into a weak function to
allow vendor specific override
Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be
added to the vendor specific code without the need to remember to
#undef usage of the generic method and if you forget to include your
custom reset method, you will always get the default.
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Brings i386 in line with other CPUs with a reset vector and frees up reset.c
for CPU reset functions
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.
If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
This ensures that subsequent accesses properly hit the new window.
The dcbi during the NAND loop was accidentally working around this;
it's no longer necessary, as the cache is not enabled.
Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch adds support for MPC83xx PCI-E controllers in Root Complex
mode.
The patch is based on Tony Li and Dave Liu work[1].
Though unlike the original patch, by default we don't register PCI-E
buses for use in U-Boot, we only configure the controllers for future
use in other OSes (Linux). This is done because we don't have enough
of spare BATs to map all the PCI-E regions.
To actually use PCI-E in U-Boot, users should explicitly define
CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And
only then U-Boot will able to access PCI-E, but at the cost of disabled
address translation.
[1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html
Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
When running a system with 2 or more MPC8349EMDS boards in PCI agent mode,
the boards will lock up the PCI bus by scanning against each other.
The boards lock against each other by trying to access the PCI bus before
clearing their configuration lock bit. Both boards end up in a loop,
sending and receiving "Target Not Ready" messages forever.
When running in PCI agent mode, the scanning now takes place after the
boards have cleared their configuration lock bit.
Also, add a missing declaration to the mpc83xx.h header file, fixing a
build warning.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Currently there are in excess of 100 bytes located at the beginning of the image
built by start.S that are not being utilized. This patch moves a few functions
into this part of the image. This will create a greater number of *available*
bytes that can be used by board specific code in NAND builds and will decrease
the size of the assembled code in other builds.
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Parallel builds would occasionally issue this build warning:
ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists
Use "ln -sf" as quick work around for the issue.
Signed-off-by: Wolfgang Denk <wd@denx.de>
So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
The local bus clock divider should be doubled for both 8610 and 8641.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
The clock divider for the MPC8568 local bus should be doubled, like the
other newer MPC85xx chips.
Since there are now more chips with a 2x divider than a 1x, and any new
85xx chips will probably be 2x, invert the sense of the #if so that it
lists the 1x chips instead of the 2x ones.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
If one custom board is using the 8MB flash, it is set
as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000.
The current start.S code will be broken at switch_as.
It is because the TLB1[15] is set as 16MB page size,
EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000.
For the 8MB flash case, the EPN = 0xefxxxxxx,
RPN = 0xffxxxxxx. Assume the virt address of switch_as
is 0xef7ff18c, the real address of the instruction at
switch_as should be 0xff7ff18c. the 0xff7ff18c is out
of the range of the default 8MB boot LAW window
0xff800000 - 0xffffffff.
So when we switch to AS1 address space at switch_as,
the core can't fetch the instruction at switch_as any
more. It will cause broken issue.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Assuming the OSes exception vectors start from the base of kernel address, and
the kernel physical starting address can be relocated to an non-zero address.
This patch enables the second core to have a valid IVPR for debugger before
kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
Export the localbus frequency in the device tree, the same way the CPU, TB,
CCB, and various other frequencies are exported in their respective device
tree nodes.
Some localbus devices need this information to be programed correctly, so
it makes sense to export it along with the other frequencies.
Unfortunately, when someone wrote the localbus dts bindings, they didn't
bother to define what the "compatible" property should be. So it seems no
one was quite sure what to put in their dts files.
Based on current existing dts files in the kernel source, I've used
"fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all
of the 85xx devices, and are looked for by the Linux code. The eLBC is
apparently not entirely backward compatible with the pq3 LBC and so eLBC
equipped platforms like 8572 won't use pq3-localbus.
For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems
and is also looked for by the Linux code. On MPC8641, I've also used
"fsl,mpc8641-localbus" as it is also commonly used in dts files, some of
which don't use "fsl,elbc" or any other acceptable name to match on.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
All implementations of the functions i2c_reg_read() and
i2c_reg_write() are identical. We can save space and simplify the
code by converting these functions into inlines and putting them in
i2c.h.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This warning is issued by modern ARM-EABI GCC on non-thumb targets.
Signed-off-by: Vladimir Panfilov <pvr@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
This patch now adds a flush to the data cache upon relocation. The
current implementation is missing this. Only a comment states that it
should be done. So let's really do it now.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This patch adds the CONFIG_SKIP_LOWLEVEL_INIT option to start.S. This
enables support for boards where the lowlevel initialization is
already done when U-Boot runs (e.g. via OnChip ROM).
This will be used in the upcoming VCTH board support.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Since commit 561858ee building for FADS823 and RRvision
doesn't work. Let's include version.h and timestamp.h
unconditionally to fix the problem.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Currently the arm926ejs tree has the armv4 option set during compilation.
This flag does not belong here because a arm926 CPU is always a armv5 CPU.
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Moved up the initialization of GD so C code like set_tlb() can use
gd->flags to determine if we've relocated or not in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
If the virtual address for CCSRBAR is the same after relocation but
the physical address is changing we'd end up having two TLB entries with
the same VA. Instead we new us the new CCSRBAR virt address + 4k as a
temp virt address to access the old CCSRBAR to relocate it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Add define used to determine if PCI1 interface is in PCI or PCIX mode.
Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Removed while(1) hang if memctl_intlv_ctl is set wrong.
Remove embedded tabs from strings.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if
CONFIG_AT91RM9200 is defined and nor preloader is used.
Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.
Adjusted internal SRAM initialization to match updated user
manual recommendation.
OCM & ISRAM are now mapped as follows:
physical virtual size
ISRAM 0x4_0000_0000 0xE300_0000 256k
OCM 0x4_0004_0000 0xE304_0000 64k
A single TLB was used for this mapping.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.
Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
At least some (old ?) versions of the AT91Bootstrap do not set up the
PLLB correctly to 48 MHz in order to make USB host function correctly.
This patch sets up the PLLB to the same values Linux uses, and makes USB
work ok on the following CPUs:
- AT91CAP9
- AT91SAM9260
- AT91SAM9263
This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all
the relevant AT91CAP9/AT91SAM9 atmel boards.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This is needed on Canyonlands which still has an exception pending
while running relocate_code(). This leads to a failure after trap_init()
is moved to the top of board_init_r().
Signed-off-by: Stefan Roese <sr@denx.de>
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.
Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch creates a memory map with all the devices
in 36-bit physical space, in addition to the 32-bit map.
The CCSR relocation is moved (again, sorry) to
allow for the physical address to be 36 bits - this
requires translation to be enabled. With 36-bit physical
addressing enabled, we are no longer running with VA=PA
translations. This means we have to distinguish between
the two in the config file. The existing region name is
used to indicate the virtual address, and a _PHYS variety
is created to represent the physical address.
Large physical addressing is not enabled by default.
Set CONFIG_PHYS_64BIT in the config file to turn this on.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.
The regions for some of the mappings were far larger than they
needed to be. I have reduced the mappings to match the
actual sizes supported by the hardware.
In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them. These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.
Documentation has been changed to reflect the new map, as this
change is user visible, and affects the OS which runs post-uboot.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
We define CONFIG_MONITOR_BASE_EARLY to define the initial location
of the bootpage in flash. Use this to create an early mapping
definition for the FLASH, and change the early_bats code to use this.
This change facilitates the relocation of the flash since the early
mappings are no longer tied to the final location of the flash.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Using a mtmsr/blr means that you have to be executing at the
same virtual address once you enable translation. This is
unnecessarily restrictive, and is not really how this is
usually done. Change it to use the more common mtspr SRR0/SRR1
and rfi method.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
In order to later allow for a physical relocation of the
flash, setup_bats, which sets up the final BAT mapping
for the board, needs to happen *after* init_laws().
Otherwise, there will be no window programmed for the flash
at the new physical location at the point when we change
the mmu translation.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Also changed path in all linker scripts that reference this driver
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Affected boards:
Several MPC8xx boards
Several MPC8260/MPC8272 boards
Several MPC85xx boards
Removed initialization of the driver from net/eth.c
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init
as a part of ongoing eth_initialize cleanup work. The function ret value
is also fixed as it should be negative on fail.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
OMAP identification is implemented in 'cpuinfo.c' and located in ARM926EJ-S directory.
It makes sense to place this file in OMAP specific subdirectory, i.e. cpu/arm926ejs/omap
Signed-off-by: Roman Mashak <romez777@gmail.com>
We put the bootpg for the secondary cpus into memory and use
BPTR to get to it. This is a step towards converting to the
ePAPR boot methodology. Also, the code is written to
deal properly with more than 4GB of RAM.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Currently, the CCSR gets relocated while translation is
enabled, meaning we need 2 BAT translations to get to both the
old location and the new location. Also, the DEFAULT
CCSR location has a dependency on the BAT that maps the
FLASH region. Moving the relocation removes this unnecessary
dependency. This makes it easier and more intutive to
modify the board's memory map.
Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same
BAT for CCSR space.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
The error was caused by the change for strmhz() in cpu.c.
A few of them were one extra close parenthesis.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
MDHA, SKHA, INTC, and FlexBus structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
SSI cleanup. Remove USB Host structure from immap_539.h.
Apply changes to use FlexBus structures in mcf52x2's
cpu_init.c and platform configuration files.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
The patch is following the commit 3924384060
mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.
lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
also, the r2 is used as global data pointer.
Signed-off-by: Dave Liu <daveliu@freescale.com>
The current calculation will fail to cover all memory if
its size is not a power of two.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The commit 67256678f0 add
the another global data pointer save, but in fact the
global data pointer will be initialized in the board_init_r,
so remove it such as the 85xx/83xx family.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Kumar Gala <kumar.gala@freescale.com>
I believe these code was copied from 74xx family, but for
86xx, it is unused.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Kumar Gala <kumar.gala@freescale.com>
We must invalidate TLBs before MMU turn on, but
currently the code is not, if there are some stale
TLB entry valid in the TLBs, it will cause strange
issue.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
85xx can share them.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Renamed show_boot_progress in assembler init phase to
show_boot_progress_asm to avoid link conflicts with C version
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.
Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
This forces the DDR controller to use 4-beat bursts when
communicating to the DRAMs. However, an issue exists that
could lead to data corruption when the DDR controller is
in 32-bit bus mode while using 4-beat bursts.
Projected Impact:
If the DDR controller is operating in 32-bit bus mode with
4-beat bursts, then the controller may enter into a bad state.
All subsequent reads from memory is corrupted.
Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
Therefore, this erratum does not affect DDR3 mode.
Work Arounds:
To work around this issue, software must set DEBUG_1[31] in
DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).
Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.
* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
e500mc's 64-byte cacheline properly when it gets added.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.
Any custom xilinx ppc405 board can be added very easily with no code
duplicity.
This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h
This patch is prepared to work with the latest version of EDK (10.1)
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
Some Blackfin UARTs are read-to-clear while others are write-to-clear.
This can cause problems when we poll the LSR and then later try and handle
any errors detected.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Use the sti instruction to set the initial interrupt mask rather than
banging on the core IMASK MMR to save both space and time.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We should use the algorithm in the Linux kernel so that the UART divisor
calculation is more accurate. It also fixes problems on some picky UARTs
that have sampling anomalies.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
During cpu init, make sure we initialize the CEC properly so that
interrupts can fire and be handled while U-Boot is running.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This is done to allow other 83XX based platforms which also have UPM
(e.g. 8360) to configure and use their UPM in u-boot.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).
Though, for SGMII we'll need 125MHz clocks.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.
Signed-off-by: Stefan Roese <sr@denx.de>
Provide a weak defined routine to retrieve the CPU number for
reference boards that have multiple CPU's. Default behavior
is the existing single CPU print output. Reference boards with
multiple CPU's need to provide a board specific routine.
See board/amcc/arches/arches.c for an example.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch add the capability to configure a PPC440 based IBM SDRAM
Controller with static, compiled-in, values. PPC440 memory subsystem
includes a Memory Queue core.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Some cores don't support ethernet stashing at all, and some
instances have errata. Adds 3 properties to gianfar nodes
which support stashing. For now, just add this support to
85xx SoCs.
Signed-off-by: Andy Fleming <afleming@freescale.com>
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.
* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Added the ability for C code to invalidate the i/d-cache's and
to flush the d-cache. This allows us to more efficient change mappings
from cache-able to cache-inhibited.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
With this Command it is possible to add new I2C Busses,
which are behind 1 .. n I2C Muxes. Details see README.
Signed-off-by: Heiko Schocher <hs@denx.de>
Added as a convenience for other platforms that uses MPC8360 (has 8 UCC).
Six eth interface is chosen because the platform I am using combines
UCC1&2 and UCC3&4 as 1000 Eth and the other four UCCs as 10/100 Eth.
Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
At least some revisions of the 8313, and possibly other chips, do not
wait for all pages of the initial 4K NAND region to be loaded before
beginning execution; thus, we wait for it before branching out of the
first NAND page.
This fixes warm reset problems when booting from NAND on 8313erdb.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.
Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This reverts commit dffd2446fb.
The fix introduced by this patch is not correct. The problem is
that the documentation is not correct for the MPC8544 with regards
to which bit in PORDEVSR2 is for the SEC_CFG.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Reference manual states that MxMR[MAD] increment is the indication
of write to UPM array is complete. Honour that. Also, make the dummy
write explicit.
also fix the comment.
Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
At a lot of places in the code the PIPE_INTERRUPT flags and friends
are used wrong. The wrong bits are compared to this flag resulting
in wrong conditions. Also there are macros that should be used for
PIPE_* flags.
This patch tries to fix them all, however, I was not able to test the
changes, because I do not have any of these boards.
Review required!
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.
lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
For some reason we duplicated the majority of code in lib_ppc/interrupts.c
Not know how that happened, but there is no good reason for it.
Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the
MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
correct. There seems to be an error in the 8544 RM.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Switch to the standard CFG_HZ=1000 value, while at it, minor white-space
cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads,
provides 2% or 0.4% precision depending on the
CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s
boot-delay.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
ePAPR says if the *cache-block-size is the same as *cache-line-size
than we don't need the *cache-line-size property.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The spd_dram code shifts the base address, then masks 20 bits, but
forgets to shift the base address back. Fix this by just masking the
base address correctly.
Found this bug while trying to relocate a DDR memory at the base != 0.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
eventually leads to a machine check. This change assures that DPRAM
is allocated only once in that case.
Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].
The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus
Signed-off-by: Stefan Roese <sr@denx.de>
This patch prevents linker error on AT91RM9200 boards, if
CONFIG_CMD_I2_TREE is set.
It implements i2c_set_bus_speed and i2c_get_bus_speed as a dummy function.
Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
This patch changes get_timer() for i.MX to return the time since
'base' instead of the time since the counter was at zero.
Symptom seen is flash timeout errors when erasing or programming a
sector using the common cfi flash code.
Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
1) Change the i.MX serial driver to use the baud rate set in the
u-boot environment
2) don't assume a 16MHz value for PERCLK1 in baud rate calculations
3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write
one to clear" like other status bits in the reg.)
Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
Code in cpu/arm920t/start.S will die with a compilation error if
CONFIG_STACKSIZE + CFG_MALLOC_LEN works out to an invalid constant for
the ARM sub instruction. Change the code so that each is subtracted
independently to avoid the error.
Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
This patch adds the reset_timer() function (needed by nand_base.c) and
modifies the get_timer_masked() to work in the same way as the omap24xx
function.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Based on original patch by Bernard Blackham <bernard@largestprime.net>
U-boot's HW ECC support for large page NAND on Davinci is completely
broken. Some kernels, such as the 2.6.10 one supported by
MontaVista for DaVinci, rely upon this broken behaviour as they
share the same code for ECCs. In the existing scheme, error
detection *might* work on large page, but error correction
definitely does not. Small page ECC correction works, but the
format is not compatible with the mainline git kernel.
This patch adds ECC code that matches what is currently in the
Davinci git repository (since NAND support was added in 2.6.24).
This makes the ECC and OOB layout written by u-boot compatible with
Linux for both small page and large page devices and fixes ECC
correction for large page devices.
The old behaviour can be restored by defining the macro
CFG_DAVINCI_BROKEN_ECC, which is undefined by default.
Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Acked-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Fix printf format-string/arg mismatches under -DDEBUG.
These warnings occur with DEBUG defined for a platform using
cpu/mpc85xx. Users of other architectures can unearth similar
problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right
after "CFLAGS += $(call cc-option,-fno-stack-protector)".
Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The e500um says the timebase is volatile out of reset. To ensure
TB sync works we need to make sure its zero.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch fixes warnings like this:
start.S:0: warning: target CPU does not support interworking
which come from some ARM cross compilers and are caused by hard-coded
(with "--with-cpu=arm9" configuration option) ARM targets (which
support ARM Thumb instructions), while the ARM target selected from
the command line (with "-march=armv4") doesn't support Thumb
instructions.
This warning is issued by the compiler regardless of the real use of
the Thumb instructions in code.
To fix this problem, we use options according to compiler version
being used.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes a compilation warning for the PIP405 board. It moves the
#ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
occur anymore. I am a little unsure if this #ifdef is at the correct
place now or if it could be removed completely. This needs to get
tested on the PIP405 board.
Signed-off-by: Stefan Roese <sr@denx.de>
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function
ctrl_regs.c:523: note: 'caslat' was declared here
Add a warning in DDR1 case if cas_latency isn't a value we know about.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Alternate SDRAM DDR autocalibration routine that can be generically used
for any PPC4xx chips that have the IBM SDRAM Controller core allowing for
support of more DIMM/memory chip vendors and gets the DDR autocalibration
values which give the best read latency performance (SDRAM0_RDCC.[RDSS]).
Two alternate SDRAM DDR autocalibration algoritm are provided in this patch,
"Method_A" and "Method_B". DDR autocalibration Method_A scans the full range
of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a
lot longer to run than Method_B. Method_B executes in the same amount of time
as the currently existing DDR autocalibration routine, i.e. 1 second or so.
Normally Method_B is used and it is set as the default method.
The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM
Controller registers.[bit-field]:
1) SDRAM0_RQDC.[RQFD]
2) SDRAM0_RFDC.[RFFD]
This alternate PPC4xx DDR autocalibration code calibrates the following
IBM SDRAM Controller registers.[bit-field]:
1) SDRAM0_WRDTR.[WDTR]
2) SDRAM0_CLKTR.[CKTR]
3) SDRAM0_RQDC.[RQFD]
4) SDRAM0_RFDC.[RFFD]
and will also use the calibrated settings of the above four registers that
produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS]
register.[bit-field].
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cleans up some latent issues with the data cache control so that
dcache_enable() and dcache_disable() will work reliably (after
unlock_ram_in_cache() has been called)
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Record the Arbiter Event Register values and optionally display them.
The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.
Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
#define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
and type register values
#define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter
event register values
Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
#define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
only events, so that it can still capture
other real problems.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.
lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Set DAT value before DIR values to avoid creating glitches on the
GPIO signals.
Set gpio level register before direction register to inhibit
glitches on high level output pins.
Dir and data gets cleared at powerup, so high level output lines see
a short low pulse between setting the direction and level registers.
Issue was seen on a new board with the nReset line of the NOR flash
connected to a GPIO. Setting the direction register puts the NOR flash
in reset so the next instruction to set the level cannot get executed.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Modified board_eth_init() functions of boards that have this FEC in addition
to other Ethernet controllers.
Affected boards:
bc3450
icecube
mvbc_p
o2dnt
pm520
total5200
tq5200
Removed initialization of controller from net/eth.c
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This addresses all drivers whose initializers have already
been moved to board_eth_init()/cpu_eth_init().
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers. We create a default function that works
for most tsecs, and allow that to be overridden by board code. It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration. Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The "GPIO" port mux is used on AVR32 UC3 parts as well as AT32AP7200 and
all later AVR32 chips. This patch adds a driver for it, implementing the
same API as the existing portmux-pio driver but with more functionality.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Replace the avr32-specific gclk_init() board hook with the standard
board_postclk_init() hook which is supposed to run at the same point
during initialization.
Provide a dummy weak alias for boards not implementing this hook. The
cost of this is:
- 2 bytes for the dummy function (retal 0)
- 2 bytes for each unnecessary function call (short rcall)
which is a pretty small price to pay for avoiding lots of #ifdef
clutter. In this particular case, all boards probably end up slightly
smaller because we avoid the conditional checking if the gclk_init
symbol is NULL.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Add two helper functions for configuring and enabling generic clocks:
- gclk_enable_output: Enables output on a GCLKx pin
- gclk_set_rate: Configures a gclk to run at a specific rate
This should eliminate any reason to go mucking about with PM registers
from board code.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
- Separate the portmux configuration functionality from the GPIO pin
control API.
- Separate the controller-specific code from the chip-specific code.
- Allow "ganged" port configuration (multiple pins at once).
- Add more flexibility to the "canned" peripheral select functions:
- Allow using more than 23 address bits, more chip selects, as
well as NAND- and CF-specific pins.
- Make the MACB SPEED pin optional, and choose between MII/RMII
using a parameter instead of an #ifdef.
- Make it possible to use other MMC slots than slot 0, and support
different MMC/SDCard data bus widths.
- Use more reasonable pull-up defaults; floating pins may consume a
lot of power.
- Get rid of some custom portmux code from the mimc200 board code. The
old gpio/portmux API couldn't really handle its requirements, but
the new one can.
- Add documentation.
The end result is slightly smaller code for all boards. Which isn't
really the point, but at least it isn't any larger.
This has been verified on ATSTK1002 and ATNGW100. I'd appreciate if
the board maintainers could help me test this on their boards. In
particular, the mimc200 port has lost a lot of code, so I'm hoping Mark
can help me out.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Cc: Mark Jackson <mpfj@mimc.co.uk>
Cc: Alex Raimondi <alex.raimondi@miromico.ch>
Cc: Julien May <julien.may@miromico.ch>
Changes since v1:
* Enable pullup on NWAIT
* Add missing include to portmux-pio.h
* Rename CONFIG_PIO2 -> CONFIG_PORTMUX_PIO to match docs
Notice: USB on S3C6400 currently works _only_ with switched off MMU. One could
try to enable the MMU, but map addresses 1-to-1, and disable data cache, then
it should work too and we could still profit from instruction cache.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
DM644x is just one of a series of DaVinci chips that use the EMAC driver.
By replacing all the function names that start with dm644x_* to davinci_*
we make these function more portable. I have tested this change on my EVM.
DM6467 is another DaVinci SOC which uses the EMAC driver and i will
be sending patches that add DaVinci DM6467 support to the list soon.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This function is needed for the new NAND infrastructure. We only need
a dummy implementation though for the NDFC.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes a UIC external_interrupt hang if critical or non-critical
interrupt is set at the same time as a normal interrupt is set on UIC0.
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Removed Magic numbers from Initialization preload registers
Tested with Kilauea, Glacier, Canyonlands and Katmai boards
About 5-7% improvement seen for LMBench memtests
Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
For some reason we duplicated the majority of code in lib_ppc/interrupts.c
not show how that happened, but there is no good reason for it.
Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We
also have SERDES init code for the 8536.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Compute DIMM parameters based upon the SPD information.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Compute DIMM parameters based upon the SPD information in spd.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The main purpose of this rewrite it to be able to share the same
initialization code on all FSL PowerPC products that have DDR
controllers. (83xx, 85xx, 86xx).
The code is broken up into the following steps:
GET_SPD
COMPUTE_DIMM_PARMS
COMPUTE_COMMON_PARMS
GATHER_OPTS
ASSIGN_ADDRESSES
COMPUTE_REGS
PROGRAM_REGS
This allows us to share more code an easily allow for board specific code
overrides.
Additionally this code base adds support for >4G of DDR and provides a
foundation for supporting interleaving on processors with more than one
controller.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This adds a helper function to unlock the PCI configuration bit, so that
any extra PCI setup (such as outbound windows, etc.) can be done after
using the 83XX_GENERIC_PCI code to set up the PCI bus.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
- According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271),
-- Timer Value Register @ TIMER Base + 4 is Read-only.
-- Prescale Value (Bits 3-2 of TIMER Control register)
can only be one of 00,01,10. 11 is undefined.
-- CFG_HZ for Versatile board is set to
#define CFG_HZ (1000000 / 256)
So Prescale bits is set to indicate
- 8 Stages of Prescale, Clock divided by 256
- The Timer Control Register has one Undefined/Shouldn't Use Bit
So we should do read/modify/write Operation
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
During recent PCI-E tests it has been found that current
driverl level and de-emphasis values are not set correctly.
After sweeping throgh all de-ephasis values, it was found that
0x130 is a right value. Where 0x13 is driver level and 0 is
de-emphasis.
Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes some minor issues introduced with the patch:
ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika:
- Rework memory-queue and PLB arbiter optimization code, that the
local variable is not needed anymore. This removes one #ifdef.
- Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead
of XXX+ 0x01). This was not introduced by Prodyut, just a
copy-paste problem.
Signed-off-by: Stefan Roese <sr@denx.de>
PPC405EX and PPC460EX/GT/SX
- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
processors
- Add register bit definitions for Memory Queue Configuration registers
Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Move to using the environment variables 'ethaddr', 'eth1addr', etc..
instead of bd->bi_enetaddr, bi_enet1addr, etc.
This makes the code a bit more flexible to the number of ethernet
interfaces.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There is no point in disabling the icache on 7xx/74xx/86xx parts and not
also flushing the icache. All callers of invalidate_l1_instruction_cache()
call icache_disable() right after. Make it so icache_disable() calls
invalidate_l1_instruction_cache() for us.
Also, dcache_disable() already calls dcache_flush() so there is no point
in the explicit calls of dcache_flush().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Incorrect CFG_HZ value, change 1000000 to 1000.
Rename #waring to #warning. RAMBAR1 uses twice
in start.S, rename the later to FLASHBAR. Insert
nop for DRAM setup. And, env_offset in linker file.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Note that with older board revisions, NAND boot may only work after a
power-on reset, and not after a warm reset. I don't have a newer board
to test on; if you have a board with a 33MHz crystal, please let me know
if it works after a warm reset.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Here comes a trivial patch to cpu/arm926ejs/davinci/nand.c. Unfortunately I
don't have hardware handy so I can not test it at the moment but changes are
rather trivial so it should work. It would be nice if somebody with a
hardware checked it anyways.
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
This patch changes the 4xx NAND driver ndfc.c to match the new
infrastructure from the updated NAND subsystem. This NAND
subsystem was recently synced again with the Linux 2.6.22 MTD/NAND
subsystem.
Tested successfully on AMCC Sequoia and Bamboo.
Signed-off-by: Stefan Roese <sr@denx.de>
- Fixing leading white spaces
- Fixing indentation where 4 spaces are used instead of tab
- Removing C++ comments (//), wherever I introduced them
Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
A lot changed in the Linux MTD code, since it was last ported from
Linux to U-Boot. This patch takes U-Boot NAND support to the level
of Linux 2.6.22.1 and will enable support for very large NAND devices
(4KB pages) and ease the compatibility between U-Boot and Linux
filesystems.
This patch is tested on two custom boards with PPC and ARM
processors running YAFFS in U-Boot and Linux using gcc-4.1.2
cross compilers.
MAKEALL ppc/arm has some issues:
* DOC/OneNand/nand_spl is not building (I have not tried porting
these parts, and since I do not have any HW and I am not familiar
with this code/HW I think its best left to someone else.)
Except for the issues mentioned above, I have ported all drivers
necessary to run MAKEALL ppc/arm without errors and warnings. Many
drivers were trivial to port, but some were not so trivial. The
following drivers must be examined carefully and maybe rewritten to
some degree:
cpu/ppc4xx/ndfc.c
cpu/arm926ejs/davinci/nand.c
board/delta/nand.c
board/zylonite/nand.c
Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Stig Olsen <stig.olsen@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use CONFIG_NUM_CPUS to match existing define used by 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
This is needed because we will be possibly be locating
devices at physical addresses above 32bits, and the asm
preprocessing does not appear to deal with ULL constants
properly. We now call write_bat in lib_ppc/bat_rw.c.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX
contacts instead of only the first 256 ones as is the case prior to
this patch.
Add missing MUX_* macros and update board files to use the new macros.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
On ADS5121 when booting linux the following errors are seen:
Unable to update property /soc5121@80000000:bus-frequency, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:local-mac-address, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:address, err=FDT_ERR_NOTFOUND
This is caused by ft_cpu_setup trying to deal with
both old and new soc node naming. This patch
fixes this by being smarter about what to
fixup.
Also do soc node fixups by compatible instead of by path.
A new board config called OF_SOC_COMPAT defined
to be "fsl,mpc5121-immr" replaces the old
OF_SOC node path that was defined to be "soc@80000000".
Old device trees still work, but the compatiblity
is conditional on CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
which is on by default in include/configs/ads5121.h.
Signed-off-by: John Rigby <jrigby@freescale.com>
The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
For more information see: http:///www.miromico.com/hammerhead
Signed-off-by: Julien May <mailinglist@miromico.ch>
[haavard.skinnemoen@atmel.com: various small fixes and adaptions]
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Support for the adsvix was originally provided by Applied Data
Systems (ADS), inc., now EuroTech, Inc.
The board never shipped aside from some sample boards.
Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor
on alchemy cpus.
Signed-off-by: Wolfgang Ocker <weo@reccoware.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This patch fixes a problem with incorrect MODTx (On Die Termination)
setup for a configuration with multiple DIMM's and multiple ranks.
Without this change Katmai was unable to boot Linux with DDR2 frequency
>= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux
with DDR2 frequency = 640MHz and mem=4GB.
Signed-off-by: Stefan Roese <sr@denx.de>
-This patchs gives support for the embbedded ppc440
on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by Stefan Roese
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: Stefan Roese <sr@denx.de>
The L2 size detection code was a bit confusing and we kept having to add
code to it to handle new processors. Change the sense of detection so we
look for the older processors that aren't changing.
Also added support for 1M cache size on 8572.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some boards that have external 16550 UARTs don't have a direct
tie between bi_busfreq and the clock used for the UARTs. Boards
that do have such a tie should set CFG_NS16550_CLK to be
get_bus_freq(0) -- which most of them do already.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
With a page size of BOOKE_PAGESZ_16M, both the real and effective
addresses must be multiples of 16MB. The hardware silently truncates
them so the code happens to work. This patch clarifies the situation
by establishing addresses that the hardware doesn't need to truncate.
Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Delete the crypto node if not on an E-processor. If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
