mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
This commit is contained in:
Wolfgang Denk
commit
d459516188
5 changed files with 192 additions and 30 deletions
2
MAKEALL
2
MAKEALL
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@ -320,7 +320,7 @@ LIST_8260=" \
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LIST_83xx=" \
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MPC8313ERDB_33 \
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MPC8313ERDB_66 \
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MPC8313ERDB_NAND_66 \
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MPC8315ERDB \
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MPC8323ERDB \
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MPC832XEMDS \
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3
Makefile
3
Makefile
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@ -2083,6 +2083,9 @@ MPC8313ERDB_NAND_66_config: unconfig
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echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
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fi ;
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@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
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@if [ "$(findstring _NAND_,$@)" ] ; then \
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echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
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fi ;
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MPC8315ERDB_config: unconfig
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@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
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@ -167,6 +167,10 @@ void cpu_init_f (volatile immap_t * im)
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gd->reset_status = im->reset.rsr;
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im->reset.rsr = ~(RSR_RES);
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/* AER - Arbiter Event Register - store status */
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gd->arbiter_event_attributes = im->arbiter.aeatr;
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gd->arbiter_event_address = im->arbiter.aeadr;
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/*
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* RMR - Reset Mode Register
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* contains checkstop reset enable (4.6.1.4)
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@ -283,12 +287,12 @@ void cpu_init_f (volatile immap_t * im)
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im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
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#endif
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#ifdef CFG_GPIO1_PRELIM
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im->gpio[0].dir = CFG_GPIO1_DIR;
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im->gpio[0].dat = CFG_GPIO1_DAT;
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im->gpio[0].dir = CFG_GPIO1_DIR;
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#endif
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#ifdef CFG_GPIO2_PRELIM
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im->gpio[1].dir = CFG_GPIO2_DIR;
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im->gpio[1].dat = CFG_GPIO2_DAT;
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im->gpio[1].dir = CFG_GPIO2_DIR;
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#endif
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}
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@ -302,6 +306,130 @@ int cpu_init_r (void)
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return 0;
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}
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/*
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* Print out the bus arbiter event
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*/
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#if defined(CONFIG_DISPLAY_AER_FULL)
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static int print_83xx_arb_event(int force)
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{
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static char* event[] = {
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"Address Time Out",
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"Data Time Out",
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"Address Only Transfer Type",
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"External Control Word Transfer Type",
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"Reserved Transfer Type",
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"Transfer Error",
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"reserved",
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"reserved"
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};
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static char* master[] = {
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"e300 Core Data Transaction",
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"reserved",
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"e300 Core Instruction Fetch",
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"reserved",
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"TSEC1",
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"TSEC2",
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"USB MPH",
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"USB DR",
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"Encryption Core",
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"I2C Boot Sequencer",
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"JTAG",
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"reserved",
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"eSDHC",
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"PCI1",
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"PCI2",
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"DMA",
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"QUICC Engine 00",
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"QUICC Engine 01",
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"QUICC Engine 10",
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"QUICC Engine 11",
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"reserved",
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"reserved",
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"reserved",
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"reserved",
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"SATA1",
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"SATA2",
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"SATA3",
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"SATA4",
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"reserved",
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"PCI Express 1",
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"PCI Express 2",
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"TDM-DMAC"
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};
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static char *transfer[] = {
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"Address-only, Clean Block",
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"Address-only, lwarx reservation set",
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"Single-beat or Burst write",
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"reserved",
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"Address-only, Flush Block",
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"reserved",
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"Burst write",
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"reserved",
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"Address-only, sync",
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"Address-only, tlbsync",
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"Single-beat or Burst read",
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"Single-beat or Burst read",
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"Address-only, Kill Block",
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"Address-only, icbi",
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"Burst read",
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"reserved",
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"Address-only, eieio",
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"reserved",
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"Single-beat write",
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"reserved",
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"ecowx - Illegal single-beat write",
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"reserved",
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"reserved",
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"reserved",
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"Address-only, TLB Invalidate",
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"reserved",
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"Single-beat or Burst read",
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"reserved",
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"eciwx - Illegal single-beat read",
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"reserved",
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"Burst read",
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"reserved"
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};
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int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
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>> AEATR_EVENT_SHIFT;
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int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
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>> AEATR_MSTR_ID_SHIFT;
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int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
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>> AEATR_TBST_SHIFT;
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int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
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>> AEATR_TSIZE_SHIFT;
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int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
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>> AEATR_TTYPE_SHIFT;
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if (!force && !gd->arbiter_event_address)
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return 0;
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puts("Arbiter Event Status:\n");
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printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
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printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
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printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
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printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
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tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
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printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
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return gd->arbiter_event_address;
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}
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#elif defined(CONFIG_DISPLAY_AER_BRIEF)
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static int print_83xx_arb_event(int force)
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{
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if (!force && !gd->arbiter_event_address)
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return 0;
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printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
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gd->arbiter_event_attributes, gd->arbiter_event_address);
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return gd->arbiter_event_address;
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}
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#endif /* CONFIG_DISPLAY_AER_xxxx */
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/*
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* Figure out the cause of the reset
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*/
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@ -334,6 +462,12 @@ int prt_83xx_rsr(void)
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printf("%s%s", sep, bits[i].desc);
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sep = ", ";
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}
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puts("\n\n");
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puts("\n");
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#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
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print_83xx_arb_event(rsr & RSR_BMRS);
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#endif
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puts("\n");
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return 0;
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}
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@ -208,7 +208,7 @@ in_flash:
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bl enable_addr_trans
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sync
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/* enable and invalidate the data cache */
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/* enable the data cache */
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bl dcache_enable
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sync
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#ifdef CFG_INIT_RAM_LOCK
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@ -483,17 +483,29 @@ init_e300_core: /* time t 10 */
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1:
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_MASK_AER_AO)
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/* Write the Arbiter Event Enable to mask Address Only traps. */
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/* This prevents the dcbz instruction from being trapped when */
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/* HID0_ABE Address Broadcast Enable is set and the MEMORY */
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/* COHERENCY bit is set in the WIMG bits, which is often */
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/* needed for PCI operation. */
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lwz r4, 0x0808(r3)
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rlwinm r0, r4, 0, ~AER_AO
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stw r0, 0x0808(r3)
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#endif /* CONFIG_MASK_AER_AO */
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/* Initialize the Hardware Implementation-dependent Registers */
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/* HID0 also contains cache control */
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/* - force invalidation of data and instruction caches */
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/*------------------------------------------------------*/
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lis r3, CFG_HID0_INIT@h
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ori r3, r3, CFG_HID0_INIT@l
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ori r3, r3, (CFG_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
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SYNC
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mtspr HID0, r3
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lis r3, CFG_HID0_FINAL@h
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ori r3, r3, CFG_HID0_FINAL@l
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ori r3, r3, (CFG_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
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SYNC
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mtspr HID0, r3
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@ -703,8 +715,7 @@ disable_addr_trans:
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icache_enable:
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mfspr r3, HID0
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ori r3, r3, HID0_ICE
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lis r4, 0
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ori r4, r4, HID0_ILOCK
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li r4, HID0_ICFI|HID0_ILOCK
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andc r3, r3, r4
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ori r4, r3, HID0_ICFI
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isync
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@ -717,13 +728,10 @@ icache_enable:
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icache_disable:
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mfspr r3, HID0
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lis r4, 0
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ori r4, r4, HID0_ICE|HID0_ILOCK
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ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
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andc r3, r3, r4
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ori r4, r3, HID0_ICFI
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isync
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mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
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isync
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mtspr HID0, r3 /* clears invalidate */
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mtspr HID0, r3 /* clears invalidate, enable and lock */
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blr
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.globl icache_status
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@ -737,25 +745,24 @@ dcache_enable:
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mfspr r3, HID0
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li r5, HID0_DCFI|HID0_DLOCK
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andc r3, r3, r5
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mtspr HID0, r3 /* no invalidate, unlock */
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ori r3, r3, HID0_DCE
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ori r5, r3, HID0_DCFI
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mtspr HID0, r5 /* enable + invalidate */
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mtspr HID0, r3 /* enable */
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sync
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mtspr HID0, r3 /* enable, no invalidate */
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blr
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.globl dcache_disable
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dcache_disable:
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mflr r4
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bl flush_dcache /* uses r3 and r5 */
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mfspr r3, HID0
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lis r4, 0
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ori r4, r4, HID0_DCE|HID0_DLOCK
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andc r3, r3, r4
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ori r4, r3, HID0_DCI
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li r5, HID0_DCE|HID0_DLOCK
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andc r3, r3, r5
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ori r5, r3, HID0_DCFI
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sync
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mtspr HID0, r4 /* sets invalidate, clears enable and lock */
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mtspr HID0, r5 /* sets invalidate, clears enable and lock */
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sync
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mtspr HID0, r3 /* clears invalidate */
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mtlr r4
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blr
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.globl dcache_status
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@ -764,6 +771,18 @@ dcache_status:
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rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
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blr
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.globl flush_dcache
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flush_dcache:
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lis r3, 0
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lis r5, CFG_CACHELINE_SIZE
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1: cmp 0, 1, r3, r5
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bge 2f
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lwz r5, 0(r3)
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lis r5, CFG_CACHELINE_SIZE
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addi r3, r3, 0x4
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b 1b
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2: blr
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.globl get_pvr
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get_pvr:
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mfspr r3, PVR
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@ -1060,9 +1079,9 @@ lock_ram_in_cache:
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*/
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lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
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ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
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li r2, ((CFG_INIT_RAM_END & ~31) + \
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li r4, ((CFG_INIT_RAM_END & ~31) + \
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(CFG_INIT_RAM_ADDR & 31) + 31) / 32
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mtctr r2
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mtctr r4
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1:
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dcbz r0, r3
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addi r3, r3, 32
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@ -1070,7 +1089,7 @@ lock_ram_in_cache:
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/* Lock the data cache */
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mfspr r0, HID0
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ori r0, r0, 0x1000
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ori r0, r0, HID0_DLOCK
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sync
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mtspr HID0, r0
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sync
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@ -1082,8 +1101,9 @@ unlock_ram_in_cache:
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/* invalidate the INIT_RAM section */
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lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
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ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
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li r2,512
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mtctr r2
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li r4, ((CFG_INIT_RAM_END & ~31) + \
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(CFG_INIT_RAM_ADDR & 31) + 31) / 32
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mtctr r4
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1: icbi r0, r3
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dcbi r0, r3
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addi r3, r3, 32
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@ -1096,9 +1116,10 @@ unlock_ram_in_cache:
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li r5, HID0_DLOCK|HID0_DCFI
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andc r3, r3, r5 /* no invalidate, unlock */
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ori r5, r3, HID0_DCFI /* invalidate, unlock */
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mtspr HID0, r5 /* invalidate, unlock */
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mtspr HID0, r3 /* no invalidate, unlock */
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sync
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mtspr HID0, r5 /* invalidate, unlock */
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sync
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mtspr HID0, r3 /* no invalidate, unlock */
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blr
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#endif /* !CONFIG_NAND_SPL */
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#endif /* CFG_INIT_RAM_LOCK */
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@ -122,6 +122,10 @@ typedef struct global_data {
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phys_size_t ram_size; /* RAM size */
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unsigned long reloc_off; /* Relocation Offset */
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unsigned long reset_status; /* reset status register at boot */
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#if defined(CONFIG_MPC83XX)
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unsigned long arbiter_event_attributes;
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unsigned long arbiter_event_address;
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#endif
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unsigned long env_addr; /* Address of Environment struct */
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unsigned long env_valid; /* Checksum of Environment valid? */
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unsigned long have_console; /* serial_init() was called */
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