mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
ColdFire: Add SBF support for M52277EVB
Add serial boot support Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChung Liew
John Rigby
parent
b202816c61
commit
a21d0c2cc9
12 changed files with 842 additions and 61 deletions
22
Makefile
22
Makefile
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@ -1932,7 +1932,27 @@ ZPC1900_config: unconfig
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## Coldfire
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#########################################################################
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M52277EVB_config: unconfig
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M52277EVB_config \
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M52277EVB_spansion_config \
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M52277EVB_stmicro_config : unconfig
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@case "$@" in \
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M52277EVB_config) FLASH=SPANSION;; \
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M52277EVB_spansion_config) FLASH=SPANSION;; \
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M52277EVB_stmicro_config) FLASH=STMICRO;; \
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esac; \
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if [ "$${FLASH}" = "SPANSION" ] ; then \
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echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
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echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
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cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
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$(XECHO) "... with SPANSION boot..." ; \
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fi; \
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if [ "$${FLASH}" = "STMICRO" ] ; then \
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echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
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echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
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echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
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cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \
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$(XECHO) "... with ST Micro boot..." ; \
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fi
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@$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale
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M5235EVB_config \
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@ -22,4 +22,6 @@
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
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@ -38,8 +38,18 @@ int checkboard(void)
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phys_size_t initdram(int board_type)
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{
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u32 dramsize;
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#ifdef CONFIG_CF_SBF
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/*
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* Serial Boot: The dram is already initialized in start.S
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* only require to return DRAM size
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*/
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
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#else
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volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
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u32 dramsize, i;
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volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
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u32 i;
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
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@ -49,6 +59,8 @@ phys_size_t initdram(int board_type)
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}
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i--;
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gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
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sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
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sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
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@ -56,24 +68,30 @@ phys_size_t initdram(int board_type)
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/* Issue PALL */
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sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
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__asm__("nop");
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/* Issue LEMR */
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/*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
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sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
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__asm__("nop");
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sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
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__asm__("nop");
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udelay(1000);
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/* Issue PALL */
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sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
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__asm__("nop");
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/* Perform two refresh cycles */
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sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
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__asm__("nop");
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sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
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__asm__("nop");
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sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
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sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
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udelay(100);
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#endif
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return (dramsize);
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};
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136
board/freescale/m52277evb/u-boot.stm
Normal file
136
board/freescale/m52277evb/u-boot.stm
Normal file
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@ -0,0 +1,136 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_ARCH(m68k)
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
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.interp : { *(.interp) }
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.rel.text : { *(.rel.text) }
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.rela.text : { *(.rela.text) }
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.rel.data : { *(.rel.data) }
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.rela.data : { *(.rela.data) }
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||||
.rel.rodata : { *(.rel.rodata) }
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.rela.rodata : { *(.rela.rodata) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) }
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.plt : { *(.plt) }
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.text :
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{
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/* WARNING - the following is hand-optimized to fit within */
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/* the sector layout of our flash chips! XXX FIXME XXX */
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cpu/mcf5227x/start.o (.text)
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*(.text)
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*(.fixup)
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*(.got1)
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}
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_etext = .;
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rodata)
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*(.rodata1)
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}
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.fini : { *(.fini) } =0
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.ctors : { *(.ctors) }
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.dtors : { *(.dtors) }
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/* Read-write section, merged into data segment: */
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. = (. + 0x00FF) & 0xFFFFFF00;
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_erotext = .;
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PROVIDE (erotext = .);
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.reloc :
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{
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__got_start = .;
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*(.got)
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__got_end = .;
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_GOT2_TABLE_ = .;
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*(.got2)
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_FIXUP_TABLE_ = .;
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*(.fixup)
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}
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
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__fixup_entries = (. - _FIXUP_TABLE_)>>2;
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.data :
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{
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*(.data)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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}
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_edata = .;
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PROVIDE (edata = .);
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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. = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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. = ALIGN(256);
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__init_begin = .;
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.text.init : { *(.text.init) }
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.data.init : { *(.data.init) }
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. = ALIGN(256);
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__init_end = .;
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__bss_start = .;
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.bss :
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{
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_sbss = .;
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*(.sbss) *(.scommon)
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*(.dynbss)
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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}
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_end = . ;
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PROVIDE (end = .);
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}
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@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(CPU).a
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START = start.o
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COBJS = cpu.o speed.o cpu_init.o interrupts.o
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COBJS = cpu.o speed.o cpu_init.o interrupts.o dspi.o
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -45,6 +45,7 @@ void cpu_init_f(void)
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
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#if !defined(CONFIG_CF_SBF)
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/* Workaround, must place before fbcs */
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pll->psr = 0x12;
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@ -58,37 +59,44 @@ void cpu_init_f(void)
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scm1->pacrg = 0;
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scm1->pacri = 0;
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
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&& defined(CONFIG_SYS_CS0_CTRL))
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fbcs->csar0 = CONFIG_SYS_CS0_BASE;
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fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
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fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
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#endif
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#endif /* CONFIG_CF_SBF */
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
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&& defined(CONFIG_SYS_CS1_CTRL))
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fbcs->csar1 = CONFIG_SYS_CS1_BASE;
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fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
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fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
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&& defined(CONFIG_SYS_CS2_CTRL))
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fbcs->csar2 = CONFIG_SYS_CS2_BASE;
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fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
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fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
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&& defined(CONFIG_SYS_CS3_CTRL))
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fbcs->csar3 = CONFIG_SYS_CS3_BASE;
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fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
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fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
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&& defined(CONFIG_SYS_CS4_CTRL))
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fbcs->csar4 = CONFIG_SYS_CS4_BASE;
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fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
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fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
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&& defined(CONFIG_SYS_CS5_CTRL))
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fbcs->csar5 = CONFIG_SYS_CS5_BASE;
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fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
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fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
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261
cpu/mcf5227x/dspi.c
Normal file
261
cpu/mcf5227x/dspi.c
Normal file
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@ -0,0 +1,261 @@
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/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
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*/
|
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#if defined(CONFIG_CF_DSPI)
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#include <asm/immap.h>
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void dspi_init(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
|
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gpio->par_dspi =
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GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
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GPIO_PAR_DSPI_SCK_SCK;
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dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
|
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DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
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DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
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DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
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#ifdef CONFIG_SYS_DSPI_DCTAR0
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dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
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#endif
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#ifdef CONFIG_SYS_DSPI_DCTAR1
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dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR2
|
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dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR3
|
||||
dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR4
|
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dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
|
||||
#endif
|
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#ifdef CONFIG_SYS_DSPI_DCTAR5
|
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dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
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#endif
|
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#ifdef CONFIG_SYS_DSPI_DCTAR6
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dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR7
|
||||
dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
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||||
#endif
|
||||
}
|
||||
|
||||
void dspi_tx(int chipsel, u8 attrib, u16 data)
|
||||
{
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||||
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
|
||||
|
||||
while ((dspi->dsr & 0x0000F000) >= 4) ;
|
||||
|
||||
dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
|
||||
}
|
||||
|
||||
u16 dspi_rx(void)
|
||||
{
|
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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|
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while ((dspi->dsr & 0x000000F0) == 0) ;
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return (dspi->drfr & 0xFFFF);
|
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}
|
||||
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#if defined(CONFIG_CMD_SPI)
|
||||
void spi_init_f(void)
|
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{
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}
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void spi_init_r(void)
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{
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}
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void spi_init(void)
|
||||
{
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dspi_init();
|
||||
}
|
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||||
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
||||
unsigned int max_hz, unsigned int mode)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
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struct spi_slave *slave;
|
||||
|
||||
slave = malloc(sizeof(struct spi_slave));
|
||||
if (!slave)
|
||||
return NULL;
|
||||
|
||||
switch (cs) {
|
||||
case 0:
|
||||
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
|
||||
gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
|
||||
break;
|
||||
case 2:
|
||||
gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
|
||||
gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
|
||||
break;
|
||||
}
|
||||
|
||||
slave->bus = bus;
|
||||
slave->cs = cs;
|
||||
|
||||
return slave;
|
||||
}
|
||||
|
||||
void spi_free_slave(struct spi_slave *slave)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
switch (slave->cs) {
|
||||
case 0:
|
||||
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
|
||||
break;
|
||||
case 2:
|
||||
gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
|
||||
break;
|
||||
}
|
||||
|
||||
free(slave);
|
||||
}
|
||||
|
||||
int spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
}
|
||||
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
|
||||
void *din, unsigned long flags)
|
||||
{
|
||||
static int bWrite = 0;
|
||||
u8 *spi_rd, *spi_wr;
|
||||
int len = bitlen >> 3;
|
||||
|
||||
spi_rd = (u8 *) din;
|
||||
spi_wr = (u8 *) dout;
|
||||
|
||||
/* command handling */
|
||||
if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
|
||||
switch (*spi_wr) {
|
||||
case 0x02: /* Page Prog */
|
||||
bWrite = 1;
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[0]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[1]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[2]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[3]);
|
||||
dspi_rx();
|
||||
return 0;
|
||||
case 0x05: /* Read Status */
|
||||
if (len == 4)
|
||||
if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
|
||||
&& (spi_wr[3] == 0xFF)) {
|
||||
dspi_tx(slave->cs, 0x80, *spi_wr);
|
||||
dspi_rx();
|
||||
}
|
||||
return 0;
|
||||
case 0x06: /* WREN */
|
||||
dspi_tx(slave->cs, 0x00, *spi_wr);
|
||||
dspi_rx();
|
||||
return 0;
|
||||
case 0x0B: /* Fast read */
|
||||
if ((len == 5) && (spi_wr[4] == 0)) {
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[0]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[1]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[2]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[3]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[4]);
|
||||
dspi_rx();
|
||||
}
|
||||
return 0;
|
||||
case 0x9F: /* RDID */
|
||||
dspi_tx(slave->cs, 0x80, *spi_wr);
|
||||
dspi_rx();
|
||||
return 0;
|
||||
case 0xD8: /* Sector erase */
|
||||
if (len == 4)
|
||||
if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[0]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[1]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[2]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x00, spi_wr[3]);
|
||||
dspi_rx();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (bWrite)
|
||||
len--;
|
||||
|
||||
while (len--) {
|
||||
if (dout != NULL) {
|
||||
dspi_tx(slave->cs, 0x80, *spi_wr);
|
||||
dspi_rx();
|
||||
spi_wr++;
|
||||
}
|
||||
|
||||
if (din != NULL) {
|
||||
dspi_tx(slave->cs, 0x80, 0);
|
||||
*spi_rd = dspi_rx();
|
||||
spi_rd++;
|
||||
}
|
||||
}
|
||||
|
||||
if (flags == SPI_XFER_END) {
|
||||
if (bWrite) {
|
||||
dspi_tx(slave->cs, 0x00, *spi_wr);
|
||||
dspi_rx();
|
||||
bWrite = 0;
|
||||
} else {
|
||||
dspi_tx(slave->cs, 0x00, 0);
|
||||
dspi_rx();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_SPI */
|
||||
|
||||
#endif /* CONFIG_CF_DSPI */
|
||||
|
|
@ -90,17 +90,33 @@ int get_clocks(void)
|
|||
int vco, temp, pcrvalue, pfdr;
|
||||
u8 bootmode;
|
||||
|
||||
bootmode = (ccm->ccr & 0x000C) >> 2;
|
||||
|
||||
pcrvalue = pll->pcr & 0xFF0F0FFF;
|
||||
pfdr = pcrvalue >> 24;
|
||||
|
||||
if (pfdr != 0x1E) {
|
||||
if (pfdr == 0x1E)
|
||||
bootmode = 0; /* Normal Mode */
|
||||
|
||||
#ifdef CONFIG_CF_SBF
|
||||
bootmode = 3; /* Serial Mode */
|
||||
#endif
|
||||
|
||||
if (bootmode == 0) {
|
||||
/* Normal mode */
|
||||
vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
|
||||
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
|
||||
/* Default value */
|
||||
pcrvalue = (pll->pcr & 0x00FFFFFF);
|
||||
pcrvalue |= 0x1E << 24;
|
||||
pll->pcr = pcrvalue;
|
||||
vco =
|
||||
((pll->pcr & 0xFF000000) >> 24) *
|
||||
CONFIG_SYS_INPUT_CLKSRC;
|
||||
}
|
||||
gd->vco_clk = vco; /* Vco clock */
|
||||
} else if (bootmode == 3) {
|
||||
/* serial mode */
|
||||
} else {
|
||||
/* Normal Mode */
|
||||
vco = pfdr * CONFIG_SYS_INPUT_CLKSRC;
|
||||
gd->vco_clk = vco;
|
||||
vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
|
||||
gd->vco_clk = vco; /* Vco clock */
|
||||
}
|
||||
|
||||
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
|
||||
|
|
|
|||
|
|
@ -46,6 +46,11 @@
|
|||
addl #60,%sp; /* space for 15 regs */ \
|
||||
rte;
|
||||
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
|
||||
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
|
||||
#endif
|
||||
|
||||
.text
|
||||
/*
|
||||
* Vector table. This is used for initial platform startup.
|
||||
|
|
@ -53,8 +58,14 @@
|
|||
*/
|
||||
_vectors:
|
||||
|
||||
INITSP: .long 0x00000000 /* Initial SP */
|
||||
INITPC: .long _START /* Initial PC */
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
INITSP: .long 0 /* Initial SP */
|
||||
INITPC: .long ASM_DRAMINIT /* Initial PC */
|
||||
#else
|
||||
INITSP: .long 0 /* Initial SP */
|
||||
INITPC: .long _START /* Initial PC */
|
||||
#endif
|
||||
|
||||
vector02: .long _FAULT /* Access Error */
|
||||
vector03: .long _FAULT /* Address Error */
|
||||
vector04: .long _FAULT /* Illegal Instruction */
|
||||
|
|
@ -83,6 +94,7 @@ vector1D: .long _FAULT /* Autovector Level 5 */
|
|||
vector1E: .long _FAULT /* Autovector Level 6 */
|
||||
vector1F: .long _FAULT /* Autovector Level 7 */
|
||||
|
||||
#if !defined(CONFIG_CF_SBF)
|
||||
/* TRAP #0 - #15 */
|
||||
vector20_2F:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
|
|
@ -122,9 +134,231 @@ vector192_255:
|
|||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
|
||||
asm_sbf_img_hdr:
|
||||
.long 0x00000000 /* checksum, not yet implemented */
|
||||
.long 0x00020000 /* image length */
|
||||
.long TEXT_BASE /* image to be relocated at */
|
||||
|
||||
asm_dram_init:
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR1 /* init Rambar */
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
|
||||
clr.l %sp@-
|
||||
|
||||
/* Must disable global address */
|
||||
move.l #0xFC008000, %a1
|
||||
move.l #(CONFIG_SYS_CS0_BASE), (%a1)
|
||||
move.l #0xFC008008, %a1
|
||||
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
|
||||
move.l #0xFC008004, %a1
|
||||
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
|
||||
|
||||
/*
|
||||
* Dram Initialization
|
||||
* a1, a2, and d0
|
||||
*/
|
||||
/* mscr sdram */
|
||||
move.l #0xFC0A4074, %a1
|
||||
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
|
||||
nop
|
||||
|
||||
/* SDRAM Chip 0 and 1 */
|
||||
move.l #0xFC0B8110, %a1
|
||||
move.l #0xFC0B8114, %a2
|
||||
|
||||
/* calculate the size */
|
||||
move.l #0x13, %d1
|
||||
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
|
||||
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||
lsr.l #1, %d2
|
||||
#endif
|
||||
|
||||
dramsz_loop:
|
||||
lsr.l #1, %d2
|
||||
add.l #1, %d1
|
||||
cmp.l #1, %d2
|
||||
bne dramsz_loop
|
||||
|
||||
/* SDRAM Chip 0 and 1 */
|
||||
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
|
||||
or.l %d1, (%a1)
|
||||
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
|
||||
or.l %d1, (%a2)
|
||||
#endif
|
||||
nop
|
||||
|
||||
/* dram cfg1 and cfg2 */
|
||||
move.l #0xFC0B8008, %a1
|
||||
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
|
||||
nop
|
||||
move.l #0xFC0B800C, %a2
|
||||
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
|
||||
nop
|
||||
|
||||
move.l #0xFC0B8000, %a1 /* Mode */
|
||||
move.l #0xFC0B8004, %a2 /* Ctrl */
|
||||
|
||||
/* Issue PALL */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||
nop
|
||||
|
||||
/* Issue LEMR */
|
||||
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
|
||||
nop
|
||||
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
|
||||
nop
|
||||
|
||||
move.l #1000, %d0
|
||||
wait1000:
|
||||
nop
|
||||
subq.l #1, %d0
|
||||
bne wait1000
|
||||
|
||||
/* Issue PALL */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||
nop
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
|
||||
nop
|
||||
move.l %d0, (%a2)
|
||||
move.l %d0, (%a2)
|
||||
nop
|
||||
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
|
||||
and.l #0x7FFFFFFF, %d0
|
||||
or.l #0x10000c00, %d0
|
||||
move.l %d0, (%a2)
|
||||
nop
|
||||
|
||||
/*
|
||||
* DSPI Initialization
|
||||
* a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
|
||||
* a1 - dspi status
|
||||
* a2 - dtfr
|
||||
* a3 - drfr
|
||||
* a4 - Dst addr
|
||||
*/
|
||||
|
||||
/* Enable pins for DSPI mode - chip-selects are enabled later */
|
||||
move.l #0xFC0A4036, %a0
|
||||
move.b #0x3F, %d0
|
||||
move.b %d0, (%a0)
|
||||
|
||||
/* DSPI CS */
|
||||
#ifdef CONFIG_SYS_DSPI_CS0
|
||||
move.b (%a0), %d0
|
||||
or.l #0xC0, %d0
|
||||
move.b %d0, (%a0)
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_CS2
|
||||
move.l #0xFC0A4037, %a0
|
||||
move.b (%a0), %d0
|
||||
or.l #0x10, %d0
|
||||
move.b %d0, (%a0)
|
||||
#endif
|
||||
nop
|
||||
|
||||
/* Configure DSPI module */
|
||||
move.l #0xFC05C000, %a0
|
||||
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
|
||||
|
||||
move.l #0xFC05C00C, %a0
|
||||
move.l #0x3E000011, (%a0)
|
||||
|
||||
move.l #0xFC05C034, %a2 /* dtfr */
|
||||
move.l #0xFC05C03B, %a3 /* drfr */
|
||||
|
||||
move.l #(ASM_SBF_IMG_HDR + 4), %a1
|
||||
move.l (%a1)+, %d5
|
||||
move.l (%a1), %a4
|
||||
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
|
||||
move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
|
||||
|
||||
move.l #0xFC05C02C, %a1 /* dspi status */
|
||||
|
||||
/* Issue commands and address */
|
||||
move.l #0x8004000B, %d2 /* Fast Read Cmd */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80040000, %d2 /* Address byte 2 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80040000, %d2 /* Address byte 1 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80040000, %d2 /* Address byte 0 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80040000, %d2 /* Dummy Wr and Rd */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
/* Transfer serial boot header to sram */
|
||||
asm_dspi_rd_loop1:
|
||||
move.l #0x80040000, %d2
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.b %d1, (%a0) /* read, copy to dst */
|
||||
|
||||
add.l #1, %a0 /* inc dst by 1 */
|
||||
sub.l #1, %d4 /* dec cnt by 1 */
|
||||
bne asm_dspi_rd_loop1
|
||||
|
||||
/* Transfer u-boot from serial flash to memory */
|
||||
asm_dspi_rd_loop2:
|
||||
move.l #0x80040000, %d2
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.b %d1, (%a4) /* read, copy to dst */
|
||||
|
||||
add.l #1, %a4 /* inc dst by 1 */
|
||||
sub.l #1, %d5 /* dec cnt by 1 */
|
||||
bne asm_dspi_rd_loop2
|
||||
|
||||
move.l #0x00040000, %d2 /* Terminate */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
/* jump to memory and execute */
|
||||
move.l #(TEXT_BASE + 0x400), %a0
|
||||
move.l %a0, (%a1)
|
||||
jmp (%a0)
|
||||
|
||||
asm_dspi_wr_status:
|
||||
move.l (%a1), %d0 /* status */
|
||||
and.l #0x0000F000, %d0
|
||||
cmp.l #0x00003000, %d0
|
||||
bgt asm_dspi_wr_status
|
||||
|
||||
move.l %d2, (%a2)
|
||||
rts
|
||||
|
||||
asm_dspi_rd_status:
|
||||
move.l (%a1), %d0 /* status */
|
||||
and.l #0x000000F0, %d0
|
||||
lsr.l #4, %d0
|
||||
cmp.l #0, %d0
|
||||
beq asm_dspi_rd_status
|
||||
|
||||
move.b (%a3), %d1
|
||||
rts
|
||||
#endif /* CONFIG_CF_SBF */
|
||||
|
||||
.text
|
||||
|
||||
. = 0x400
|
||||
.globl _start
|
||||
_start:
|
||||
nop
|
||||
|
|
@ -132,11 +366,16 @@ _start:
|
|||
move.w #0x2700,%sr /* Mask off Interrupt */
|
||||
|
||||
/* Set vector base register at the beginning of the Flash */
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
move.l #TEXT_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
#else
|
||||
move.l #CONFIG_SYS_FLASH_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR1
|
||||
#endif
|
||||
|
||||
/* initialize general use internal ram */
|
||||
move.l #0, %d0
|
||||
|
|
|
|||
|
|
@ -282,8 +282,8 @@
|
|||
|
||||
/* Bit definitions and macros for PAR_DSPI */
|
||||
#define GPIO_PAR_DSPI_PCS0_MASK (0x3F)
|
||||
#define GPIO_PAR_DSPI_PCS0_PCS0 (0x80)
|
||||
#define GPIO_PAR_DSPI_PCS0_U2RTS (0x40)
|
||||
#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
|
||||
#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
|
||||
#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
|
||||
#define GPIO_PAR_DSPI_SIN_MASK (0xCF)
|
||||
#define GPIO_PAR_DSPI_SIN_SIN (0x30)
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
|
||||
#define CONFIG_MCFUART
|
||||
#define CONFIG_SYS_UART_PORT (0)
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
|
|
@ -72,21 +72,50 @@
|
|||
#define CONFIG_CMD_REGINFO
|
||||
#undef CONFIG_CMD_USB
|
||||
#undef CONFIG_CMD_BMP
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
|
||||
#define CONFIG_HOSTNAME M52277EVB
|
||||
#define CONFIG_HOSTNAME M52277EVB
|
||||
#define CONFIG_SYS_UBOOT_END 0x3FFFF
|
||||
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
|
||||
#ifdef CONFIG_SYS_STMICRO_BOOT
|
||||
/* ST Micro serial flash */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"loadaddr=0x40010000\0" \
|
||||
"uboot=u-boot.bin\0" \
|
||||
"load=loadb ${loadaddr} ${baudrate};" \
|
||||
"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off 0 0x3ffff;" \
|
||||
"era 0 3ffff;" \
|
||||
"cp.b ${loadaddr} 0 ${filesize};" \
|
||||
"prog=sf probe 0:2 10000 1;" \
|
||||
"sf erase 0 30000;" \
|
||||
"sf write ${loadaddr} 0 30000;" \
|
||||
"save\0" \
|
||||
""
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPANSION_BOOT
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=0x40010000\0" \
|
||||
"uboot=u-boot.bin\0" \
|
||||
"load=loadb ${loadaddr} ${baudrate}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
|
||||
" " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
|
||||
"era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
|
||||
MK_STR(CONFIG_SYS_UBOOT_END) ";" \
|
||||
"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
|
||||
" ${filesize}; save\0" \
|
||||
"updsbf=run loadsbf; run progsbf\0" \
|
||||
"loadsbf=loadb ${loadaddr} ${baudrate};" \
|
||||
"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
|
||||
"progsbf=sf probe 0:2 10000 1;" \
|
||||
"sf erase 0 30000;" \
|
||||
"sf write ${loadaddr} 0 30000;" \
|
||||
""
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
|
||||
/* LCD */
|
||||
#ifdef CONFIG_CMD_BMP
|
||||
#define CONFIG_LCD
|
||||
|
|
@ -102,7 +131,7 @@
|
|||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
|
||||
#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
|
||||
#define CONFIG_SYS_USB_EHCI_CPU_INIT
|
||||
#endif
|
||||
|
||||
|
|
@ -122,30 +151,53 @@
|
|||
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
/* DSPI and Serial Flash */
|
||||
#define CONFIG_CF_DSPI
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CONFIG_SYS_SER_FLASH_BASE 0x01000000
|
||||
#define CONFIG_SYS_SBFHDR_SIZE 0x7
|
||||
#ifdef CONFIG_CMD_SPI
|
||||
# define CONFIG_SYS_DSPI_CS2
|
||||
# define CONFIG_SPI_FLASH
|
||||
# define CONFIG_SPI_FLASH_STMICRO
|
||||
|
||||
# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
|
||||
DSPI_DCTAR_CPOL | \
|
||||
DSPI_DCTAR_CPHA | \
|
||||
DSPI_DCTAR_PCSSCK_1CLK | \
|
||||
DSPI_DCTAR_PASC(0) | \
|
||||
DSPI_DCTAR_PDT(0) | \
|
||||
DSPI_DCTAR_CSSCK(0) | \
|
||||
DSPI_DCTAR_ASC(0) | \
|
||||
DSPI_DCTAR_PBR(0) | \
|
||||
DSPI_DCTAR_DT(1) | \
|
||||
DSPI_DCTAR_BR(1))
|
||||
#endif
|
||||
|
||||
/* Input, PCI, Flexbus, and VCO */
|
||||
#define CONFIG_EXTRA_CLOCK
|
||||
|
||||
#define CONFIG_SYS_INPUT_CLKSRC 16000000
|
||||
|
||||
#define CONFIG_PRAM 512 /* 512 KB */
|
||||
#define CONFIG_PRAM 2048 /* 2048 KB */
|
||||
|
||||
#define CONFIG_SYS_PROMPT "-> "
|
||||
#define CONFIG_SYS_PROMPT "-> "
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_SYS_MBAR 0xFC000000
|
||||
|
||||
|
|
@ -155,17 +207,18 @@
|
|||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 16)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
|
||||
#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
|
|
@ -177,11 +230,16 @@
|
|||
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
|
||||
#define CONFIG_SYS_SDRAM_EMOD 0x81810000
|
||||
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
|
||||
#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
|
||||
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
|
||||
#ifdef CONFIG_CF_SBF
|
||||
# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
|
||||
#else
|
||||
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
|
||||
#endif
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
|
@ -189,24 +247,40 @@
|
|||
/* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
|
||||
|
||||
/* Configuration for environment
|
||||
/*
|
||||
* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#ifdef CONFIG_CF_SBF
|
||||
# define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
# define CONFIG_ENV_SPI_CS 2
|
||||
#else
|
||||
# define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#endif
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#undef CONFIG_ENV_IS_EMBEDDED
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
|
||||
#define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x8000
|
||||
#ifdef CONFIG_SYS_STMICRO_BOOT
|
||||
# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
|
||||
# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
|
||||
# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
|
||||
# define CONFIG_ENV_OFFSET 0x30000
|
||||
# define CONFIG_ENV_SIZE 0x1000
|
||||
# define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPANSION_BOOT
|
||||
# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
|
||||
# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
|
||||
# define CONFIG_ENV_SIZE 0x1000
|
||||
# define CONFIG_ENV_SECT_SIZE 0x8000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#ifdef CONFIG_SYS_FLASH_CFI
|
||||
|
||||
# define CONFIG_FLASH_CFI_DRIVER 1
|
||||
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
|
||||
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
|
|
@ -214,6 +288,7 @@
|
|||
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
|
||||
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
||||
# define CONFIG_SYS_FLASH_CHECKSUM
|
||||
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -229,7 +304,7 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory bank definitions
|
||||
|
|
@ -243,8 +318,14 @@
|
|||
* CS5 - Available
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CF_SBF
|
||||
#define CONFIG_SYS_CS0_BASE 0x04000000
|
||||
#define CONFIG_SYS_CS0_MASK 0x00FF0001
|
||||
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
|
||||
#else
|
||||
#define CONFIG_SYS_CS0_BASE 0x00000000
|
||||
#define CONFIG_SYS_CS0_MASK 0x00FF0001
|
||||
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
|
||||
#endif
|
||||
|
||||
#endif /* _M52277EVB_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue