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https://github.com/AsahiLinux/u-boot
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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
commit
e70ef33b6b
3 changed files with 26 additions and 5 deletions
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@ -588,8 +588,9 @@ void pci_init_board(void)
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int busno;
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busno = pci_440_init (&ppc440_hose);
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#if defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#if (defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
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!defined(CONFIG_PCI_DISABLE_PCIE)
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pcie_setup_hoses(busno + 1);
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#endif
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}
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@ -33,7 +33,7 @@
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#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
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defined(CONFIG_PCI)
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defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
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#include <asm/4xx_pcie.h>
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@ -113,6 +113,7 @@ void fdt_pcie_setup(void *blob)
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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sys_info_t sys_info;
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int off, ndepth = 0;
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get_sys_info(&sys_info);
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@ -133,9 +134,28 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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/*
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* Setup all baudrates for the UARTs
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* Fixup all UART clocks for CPU internal UARTs
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* (only these UARTs are definitely clocked by gd->uart_clk)
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*
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* These UARTs are direct childs of /plb/opb. This code
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* does not touch any UARTs that are connected to the ebc.
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*/
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do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1);
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off = fdt_path_offset(blob, "/plb/opb");
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while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
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/*
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* process all sub nodes and stop when we are back
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* at the starting depth
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*/
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if (ndepth <= 0)
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break;
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/* only update direct childs */
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if ((ndepth == 1) &&
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(fdt_node_check_compatible(blob, off, "ns16550") == 0))
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fdt_setprop(blob, off,
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"clock-frequency",
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(void*)&(gd->uart_clk), 4);
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}
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/*
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* Fixup all ethernet nodes
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