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Merge branch 'master' of /home/stefan/git/u-boot/u-boot

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Stefan Roese 2008-10-13 11:17:31 +02:00
commit 1f6aa622e3
41 changed files with 202 additions and 129 deletions
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13
README.imx31
View file

@ -1,13 +0,0 @@
i.MX31 specific Configuration Options:
--------------------------------------
- Timer precision:
CONFIG_MX31_TIMER_HIGH_PRECISION
Enable higher precision timer. The low-precision timer
(default) provides approximately 4% error, whereas the
high-precision timer is about 0.4% accurate. The extra
accuracy is achieved at the cost of higher computational
overhead, which, in places where time is measured, should
not be critical, so, it should be safe to enable this
option.

2
board/freescale/common/sys_eeprom.c
View file

@ -463,6 +463,6 @@ unsigned int get_cpu_board_revision(void)
if ((be.major == 0xff) && (be.minor == 0xff))
return MPC85XX_CPU_BOARD_REV(0, 0);
return MPC85XX_CPU_BOARD_REV(e.major, e.minor);
return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
}
#endif

2
board/freescale/mpc8313erdb/sdram.c
View file

@ -64,7 +64,7 @@ static long fixed_sdram(void)
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;

2
board/freescale/mpc8315erdb/sdram.c
View file

@ -60,7 +60,7 @@ static long fixed_sdram(void)
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;

2
board/freescale/mpc8349emds/mpc8349emds.c
View file

@ -109,7 +109,7 @@ int fixed_sdram(void)
return -1;
}
}
im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CFG_DDR_SIZE != 256)

2
board/freescale/mpc8349itx/mpc8349itx.c
View file

@ -55,7 +55,7 @@ int fixed_sdram(void)
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff;
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
/* Only one CS0 for DDR */
im->ddr.csbnds[0].csbnds = 0x0000000f;

2
board/freescale/mpc837xemds/mpc837xemds.c
View file

@ -108,7 +108,7 @@ int fixed_sdram(void)
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
#if (CFG_DDR_SIZE != 512)

2
board/freescale/mpc837xerdb/mpc837xerdb.c
View file

@ -96,7 +96,7 @@ int fixed_sdram(void)
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;

2
board/matrix_vision/mvblm7/mvblm7.c
View file

@ -50,7 +50,7 @@ int fixed_sdram(void)
if (ddr_size & 1)
return -1;
}
im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
LAWAR_SIZE);

2
board/sbc8349/sbc8349.c
View file

@ -101,7 +101,7 @@ int fixed_sdram(void)
return -1;
}
}
im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CFG_DDR_SIZE != 256)

75
cpu/arm1136/mx31/interrupts.c
View file

@ -27,30 +27,49 @@
#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
/* General purpose timers registers */
#define GPTCR __REG(TIMER_BASE) /* Control register */
#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
#define GPTCR __REG(TIMER_BASE) /* Control register */
#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
/* "time" is measured in 1 / CFG_HZ seconds, "tick" is internal timer period */
#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
#define TICK_TO_TIME(t) ((t) * CFG_HZ / CONFIG_MX31_CLK32)
#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CFG_HZ)
#define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \
999999) / 1000000)
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CFG_HZ / 2) / CFG_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
#define TICK_TO_TIME(t) ((t) / TICK_PER_TIME)
#define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME)
#define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK)
#endif
static ulong timestamp;
static ulong lastinc;
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int interrupt_init (void)
{
int i;
/* setup GP Timer 1 */
GPTCR = GPTCR_SWR;
for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */
for (i = 0; i < 100; i++)
GPTCR = 0; /* We have no udelay by now */
GPTPR = 0; /* 32Khz */
GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
/* Freerun Mode, PERCLK1 input */
GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
return 0;
}
@ -67,7 +86,7 @@ void reset_timer(void)
reset_timer_masked();
}
ulong get_timer_masked (void)
unsigned long long get_ticks (void)
{
ulong now = GPTCNT; /* current tick value */
@ -80,6 +99,17 @@ ulong get_timer_masked (void)
return timestamp;
}
ulong get_timer_masked (void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CFG_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return TICK_TO_TIME(get_ticks());
}
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
@ -87,29 +117,20 @@ ulong get_timer (ulong base)
void set_timer (ulong t)
{
timestamp = TIME_TO_TICK(t);
}
/* delay x useconds AND perserve advance timstamp value */
void udelay (unsigned long usec)
{
ulong tmo, tmp;
unsigned long long tmp;
ulong tmo;
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo /= (1000*1000);
}
tmo = US_TO_TICK(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
tmp = get_timer (0); /* get current timestamp */
if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
else
tmo += tmp; /* else, set advancing stamp wake up time */
while (get_timer_masked () < tmo)/* loop till event */
/*NOP*/;
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
void reset_cpu (ulong addr)

2
cpu/mpc83xx/spd_sdram.c
View file

@ -274,7 +274,7 @@ long int spd_sdram()
/*
* Set up LAWBAR for all of DDR.
*/
ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:bar=0x%08x\n", ecm->bar);
debug("DDR:ar=0x%08x\n", ecm->ar);

3
cpu/mpc85xx/cpu.c
View file

@ -85,7 +85,8 @@ int checkcpu (void)
struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
#endif

3
cpu/mpc85xx/fdt.c
View file

@ -152,7 +152,6 @@ static inline void ft_fixup_l2cache(void *blob)
}
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
fdt_setprop_cell(blob, off, "cache-line-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
fdt_setprop_cell(blob, off, "cache-level", 2);
@ -181,7 +180,6 @@ static inline void ft_fixup_cache(void *blob)
dnum_sets = dsize / (dline_size * dnum_ways);
fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
@ -192,7 +190,6 @@ static inline void ft_fixup_cache(void *blob)
inum_sets = isize / (iline_size * inum_ways);
fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-size", isize);
fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);

7
cpu/mpc85xx/speed.c
View file

@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_DDR_CLK_FREQ
{
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
@ -101,9 +102,9 @@ int get_clocks (void)
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
gd->i2c1_clk = sys_info.freqSystemBus / 3;
else
gd->i2c1_clk = sys_info.freqSystemBus / 2;
else
gd->i2c1_clk = sys_info.freqSystemBus / 3;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
gd->i2c1_clk = sys_info.freqSystemBus / 2;

29
doc/README.imx31 Normal file
View file

@ -0,0 +1,29 @@
U-Boot for Freescale i.MX31
This file contains information for the port of U-Boot to the Freescale
i.MX31 SoC.
1. CONFIGURATION OPTIONS/SETTINGS
---------------------------------
1.1 Configuration of MC13783 SPI bus
------------------------------------
The power management companion chip MC13783 is connected to the
i.MX31 via an SPI bus. Use the following configuration options
to setup the bus and chip select used for a particular board.
CONFIG_MC13783_SPI_BUS -- defines the SPI bus the MC13783 is connected to.
Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
CONFIG_MC13783_SPI_CS -- define the chip select the MC13783 s connected to.
1.2 Timer precision
-------------------
CONFIG_MX31_TIMER_HIGH_PRECISION
Enable higher precision timer. The low-precision timer
(default) provides approximately 4% error, whereas the
high-precision timer is about 0.4% accurate. The extra
accuracy is achieved at the cost of higher computational
overhead, which, in places where time is measured, should
not be critical, so, it should be safe to enable this
option.

17
doc/README.mx31
View file

@ -1,17 +0,0 @@
U-Boot for Freescale i.MX31
This file contains information for the port of U-Boot to the Freescale
i.MX31 SoC.
1. CONFIGURATION OPTIONS/SETTINGS
---------------------------------
1.1 Configuration of MC13783 SPI bus
------------------------------------
The power management companion chip MC13783 is connected to the
i.MX31 via an SPI bus. Use the following configuration options
to setup the bus and chip select used for a particular board.
CONFIG_MC13783_SPI_BUS -- defines the SPI bus the MC13783 is connected to.
Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
CONFIG_MC13783_SPI_CS -- define the chip select the MC13783 s connected to.

2
doc/uImage.FIT/multi.its
View file

@ -56,6 +56,7 @@
data = /incbin/("./eldk-4.2-ramdisk");
type = "ramdisk";
arch = "ppc";
os = "linux";
compression = "gzip";
hash@1 {
algo = "sha1";
@ -67,6 +68,7 @@
data = /incbin/("./eldk-3.1-ramdisk");
type = "ramdisk";
arch = "ppc";
os = "linux";
compression = "gzip";
hash@1 {
algo = "crc32";

3
drivers/mtd/cfi_flash.c
View file

@ -1932,9 +1932,10 @@ ulong flash_get_size (ulong base, int banknum)
/* XXX - Need to test on x8/x16 in parallel. */
info->portwidth >>= 1;
}
flash_write_cmd (info, 0, 0, info->cmd_reset);
}
flash_write_cmd (info, 0, 0, info->cmd_reset);
return (info->size);
}

7
include/asm-ppc/immap_85xx.h
View file

@ -1552,6 +1552,13 @@ typedef struct par_io {
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
#ifdef CONFIG_MPC8536
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
#endif
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */

3
include/configs/MPC8313ERDB.h
View file

@ -174,6 +174,7 @@
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 8 /* flash size in MB */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
@ -596,7 +597,7 @@
#define CONFIG_FDTFILE mpc8313erdb.dtb
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define XMK_STR(x) #x

1
include/configs/MPC8315ERDB.h
View file

@ -193,6 +193,7 @@
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 8 /* FLASH size is 8M */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */

3
include/configs/MPC8323ERDB.h
View file

@ -181,6 +181,7 @@
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
@ -570,7 +571,7 @@
#define CONFIG_FDTFILE mpc832x_rdb.dtb
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define XMK_STR(x) #x

1
include/configs/MPC832XEMDS.h
View file

@ -169,6 +169,7 @@
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */

1
include/configs/MPC8349EMDS.h
View file

@ -156,6 +156,7 @@
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 32 /* max flash size in MB */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* #define CFG_FLASH_USE_BUFFER_WRITE */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \

1
include/configs/MPC8349ITX.h
View file

@ -190,6 +190,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* Vitesse 7385 */

1
include/configs/MPC8360EMDS.h
View file

@ -194,6 +194,7 @@
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */

1
include/configs/MPC837XEMDS.h
View file

@ -229,6 +229,7 @@
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */

3
include/configs/MPC837XERDB.h
View file

@ -253,6 +253,7 @@
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
@ -632,7 +633,7 @@
#define CONFIG_FDTFILE mpc8379_rdb.dtb
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define XMK_STR(x) #x

3
include/configs/MPC8536DS.h
View file

@ -59,7 +59,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
/* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
from ICS307 instead of switches */
@ -303,7 +303,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
*/
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_ID_EEPROM
#define CFG_I2C_EEPROM_NXID
#endif
#define CFG_I2C_EEPROM_ADDR 0x57

19
include/configs/MPC8572DS.h
View file

@ -108,6 +108,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
/* I2C addresses of SPD EEPROMs */
#define CFG_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
@ -293,11 +294,25 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3100
#define CFG_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
/*
* I2C2 EEPROM
*/
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CFG_I2C_EEPROM_NXID
#endif
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_BUS_NUM 1
/*
* General PCI

3
include/configs/TQM5200.h
View file

@ -720,6 +720,9 @@
/* Interval between registers */
#define CFG_ATA_STRIDE 4
/* Support ATAPI devices */
#define CONFIG_ATAPI 1
/*-----------------------------------------------------------------------
* Open firmware flat tree support
*-----------------------------------------------------------------------

4
include/configs/imx31_litekit.h
View file

@ -122,11 +122,9 @@
#define CFG_MEMTEST_START 0 /* memtest works on */
#define CFG_MEMTEST_END 0x10000
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0 /* default load address */
#define CFG_HZ 32000
#define CFG_HZ 1000
#define CONFIG_CMDLINE_EDITING 1

2
include/configs/imx31_phycore.h
View file

@ -126,7 +126,7 @@
#define CFG_LOAD_ADDR 0 /* default load address */
#define CFG_HZ 32000
#define CFG_HZ 1000
#define CONFIG_CMDLINE_EDITING 1

4
include/configs/mx31ads.h
View file

@ -139,11 +139,9 @@
#define CFG_MEMTEST_START 0 /* memtest works on */
#define CFG_MEMTEST_END 0x10000
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR CONFIG_LOADADDR
#define CFG_HZ CONFIG_MX31_CLK32 /* use 32kHz clock as source */
#define CFG_HZ 1000
#define CONFIG_CMDLINE_EDITING 1

28
include/libfdt.h
View file

@ -122,7 +122,7 @@
/* Low-level functions (you probably don't need these) */
/**********************************************************************/
const void *fdt_offset_ptr(const void *fdt, int offset, int checklen);
const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
{
return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
@ -458,6 +458,32 @@ static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
*/
uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
/**
* fdt_get_alias_namelen - get alias based on substring
* @fdt: pointer to the device tree blob
* @name: name of the alias th look up
* @namelen: number of characters of name to consider
*
* Identical to fdt_get_alias(), but only examine the first namelen
* characters of name for matching the alias name.
*/
const char *fdt_get_alias_namelen(const void *fdt,
const char *name, int namelen);
/**
* fdt_get_alias - retreive the path referenced by a given alias
* @fdt: pointer to the device tree blob
* @name: name of the alias th look up
*
* fdt_get_alias() retrieves the value of a given alias. That is, the
* value of the property named 'name' in the node /aliases.
*
* returns:
* a pointer to the expansion of the alias named 'name', of it exists
* NULL, if the given alias or the /aliases node does not exist
*/
const char *fdt_get_alias(const void *fdt, const char *name);
/**
* fdt_get_path - determine the full path of a node
* @fdt: pointer to the device tree blob

2
include/mpc83xx.h
View file

@ -528,7 +528,7 @@
#if defined(CONFIG_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
#if defined(CONIFG_MPC837X)
#if defined(CONFIG_MPC837X)
#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000

19
lib_arm/board.c
View file

@ -220,18 +220,6 @@ static int init_func_i2c (void)
}
#endif
#ifdef CONFIG_SKIP_RELOCATE_UBOOT
/*
* This routine sets the relocation done flag, because even if
* relocation is skipped, the flag is used by other generic code.
*/
static int reloc_init(void)
{
gd->flags |= GD_FLG_RELOC;
return 0;
}
#endif
/*
* Breathe some life into the board...
*
@ -261,11 +249,6 @@ int print_cpuinfo (void); /* test-only */
init_fnc_t *init_sequence[] = {
cpu_init, /* basic cpu dependent setup */
#if defined(CONFIG_SKIP_RELOCATE_UBOOT)
reloc_init, /* Set the relocation done flag, must
do this AFTER cpu_init(), but as soon
as possible */
#endif
board_init, /* basic board dependent setup */
interrupt_init, /* set up exceptions */
env_init, /* initialize environment */
@ -307,6 +290,8 @@ void start_armboot (void)
gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
memset (gd->bd, 0, sizeof (bd_t));
gd->flags |= GD_FLG_RELOC;
monitor_flash_len = _bss_start - _armboot_start;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {

2
lib_ppc/bootm.c
View file

@ -145,7 +145,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
* if the user wants it (the logic is in the subroutines).
*/
if (of_size) {
if (fdt_chosen(of_flat_tree, 0) < 0) {
if (fdt_chosen(of_flat_tree, 1) < 0) {
puts ("ERROR: ");
puts ("/chosen node create failed");
puts (" - must RESET the board to recover.\n");

2
libfdt/fdt.c
View file

@ -78,7 +78,7 @@ int fdt_check_header(const void *fdt)
return 0;
}
const void *fdt_offset_ptr(const void *fdt, int offset, int len)
const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
{
const char *p;

49
libfdt/fdt_ro.c
View file

@ -145,17 +145,12 @@ int fdt_path_offset(const void *fdt, const char *path)
/* see if we have an alias */
if (*path != '/') {
const char *q;
int aliasoffset = fdt_path_offset(fdt, "/aliases");
const char *q = strchr(path, '/');
if (aliasoffset < 0)
return -FDT_ERR_BADPATH;
q = strchr(path, '/');
if (!q)
q = end;
p = fdt_getprop_namelen(fdt, aliasoffset, path, q - p, NULL);
p = fdt_get_alias_namelen(fdt, p, q - p);
if (!p)
return -FDT_ERR_BADPATH;
offset = fdt_path_offset(fdt, p);
@ -306,6 +301,23 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
return fdt32_to_cpu(*php);
}
const char *fdt_get_alias_namelen(const void *fdt,
const char *name, int namelen)
{
int aliasoffset;
aliasoffset = fdt_path_offset(fdt, "/aliases");
if (aliasoffset < 0)
return NULL;
return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);
}
const char *fdt_get_alias(const void *fdt, const char *name)
{
return fdt_get_alias_namelen(fdt, name, strlen(name));
}
int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
{
int pdepth = 0, p = 0;
@ -320,9 +332,6 @@ int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
for (offset = 0, depth = 0;
(offset >= 0) && (offset <= nodeoffset);
offset = fdt_next_node(fdt, offset, &depth)) {
if (pdepth < depth)
continue; /* overflowed buffer */
while (pdepth > depth) {
do {
p--;
@ -330,14 +339,16 @@ int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
pdepth--;
}
name = fdt_get_name(fdt, offset, &namelen);
if (!name)
return namelen;
if ((p + namelen + 1) <= buflen) {
memcpy(buf + p, name, namelen);
p += namelen;
buf[p++] = '/';
pdepth++;
if (pdepth >= depth) {
name = fdt_get_name(fdt, offset, &namelen);
if (!name)
return namelen;
if ((p + namelen + 1) <= buflen) {
memcpy(buf + p, name, namelen);
p += namelen;
buf[p++] = '/';
pdepth++;
}
}
if (offset == nodeoffset) {
@ -347,7 +358,7 @@ int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
if (p > 1) /* special case so that root path is "/", not "" */
p--;
buf[p] = '\0';
return p;
return 0;
}
}