mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-22 15:42:04 +00:00
Blackfin: put memory into self-refresh before/after programming clocks
When initializing the core clocks, stick external memory into self-refresh. This gains us a few cool things: - support suspend-to-RAM with Linux - reprogram clocks automatically when doing "go" on u-boot.bin in RAM - make sure settings are stable before flashing new version - finally fully unify initialize startup code path between LDR/non-LDR Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
d347d572ab
commit
74398b23f9
2 changed files with 197 additions and 89 deletions
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@ -12,6 +12,7 @@
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#include <config.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/bootrom.h>
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#include <asm/mach-common/bits/core.h>
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#include <asm/mach-common/bits/ebiu.h>
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#include <asm/mach-common/bits/pll.h>
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#include <asm/mach-common/bits/uart.h>
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@ -257,6 +258,8 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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divB = serial_early_get_div();
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}
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serial_putc('A');
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#ifdef CONFIG_HW_WATCHDOG
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# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
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# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
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@ -273,7 +276,23 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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}
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#endif
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serial_putc('S');
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serial_putc('B');
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/* If external memory is enabled, put it into self refresh first. */
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bool put_into_srfs = false;
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#ifdef EBIU_RSTCTL
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if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
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bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
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put_into_srfs = true;
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}
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#else
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if (bfin_read_EBIU_SDBCTL() & EBE) {
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bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
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put_into_srfs = true;
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}
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#endif
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serial_putc('C');
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/* Blackfin bootroms use the SPI slow read opcode instead of the SPI
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* fast read, so we need to slow down the SPI clock a lot more during
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@ -286,29 +305,26 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
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}
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serial_putc('B');
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serial_putc('D');
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/* Disable all peripheral wakeups except for the PLL event. */
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(1);
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bfin_write_SIC_IWR1(0);
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(0);
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# endif
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#elif defined(SICA_IWR0)
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bfin_write_SICA_IWR0(1);
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bfin_write_SICA_IWR1(0);
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/* If we're entering self refresh, make sure it has happened. */
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if (put_into_srfs)
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#ifdef EBIU_RSTCTL
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while (!(bfin_read_EBIU_RSTCTL() & SRACK))
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#else
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bfin_write_SIC_IWR(1);
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while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
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#endif
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continue;
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serial_putc('E');
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/* With newer bootroms, we use the helper function to set up
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* the memory controller. Older bootroms lacks such helpers
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* so we do it ourselves.
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*/
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#define BOOTROM_CAPS_SYSCONTROL 0
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if (BOOTROM_CAPS_SYSCONTROL) {
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serial_putc('S');
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uint16_t vr_ctl = bfin_read_VR_CTL();
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if (!ANOMALY_05000386) {
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serial_putc('F');
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ADI_SYSCTRL_VALUES memory_settings;
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uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
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@ -332,22 +348,38 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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bfin_write_SIC_IWR1(-1);
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#endif
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} else {
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serial_putc('L');
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serial_putc('G');
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/* Disable all peripheral wakeups except for the PLL event. */
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(1);
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bfin_write_SIC_IWR1(0);
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(0);
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# endif
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#elif defined(SICA_IWR0)
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bfin_write_SICA_IWR0(1);
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bfin_write_SICA_IWR1(0);
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#else
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bfin_write_SIC_IWR(1);
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#endif
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serial_putc('H');
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bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
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serial_putc('A');
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serial_putc('I');
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/* Only reprogram when needed to avoid triggering unnecessary
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* PLL relock sequences.
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*/
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if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
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if (vr_ctl != CONFIG_VR_CTL_VAL) {
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serial_putc('!');
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bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
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asm("idle;");
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}
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serial_putc('C');
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serial_putc('J');
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bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
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@ -361,8 +393,26 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
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asm("idle;");
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}
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serial_putc('L');
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/* Restore all peripheral wakeups. */
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(-1);
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bfin_write_SIC_IWR1(-1);
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(-1);
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# endif
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#elif defined(SICA_IWR0)
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bfin_write_SICA_IWR0(-1);
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bfin_write_SICA_IWR1(-1);
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#else
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bfin_write_SIC_IWR(-1);
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#endif
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}
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serial_putc('M');
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/* Since we've changed the SCLK above, we may need to update
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* the UART divisors (UART baud rates are based on SCLK).
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* Do the division by hand as there are no native instructions
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@ -380,7 +430,80 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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serial_early_put_div(quotient - ANOMALY_05000230);
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}
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serial_putc('F');
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serial_putc('N');
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/* Program the external memory controller before we come out of
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* self-refresh. This only works with our SDRAM controller.
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*/
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#ifndef EBIU_RSTCTL
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bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
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bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
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bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
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#endif
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serial_putc('O');
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/* Now that we've reprogrammed, take things out of self refresh. */
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if (put_into_srfs)
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#ifdef EBIU_RSTCTL
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bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
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#else
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bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
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#endif
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serial_putc('P');
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/* Our DDR controller sucks and cannot be programmed while in
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* self-refresh. So we have to pull it out before programming.
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*/
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#ifdef EBIU_RSTCTL
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bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
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bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
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bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
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bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
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# ifdef CONFIG_EBIU_DDRCTL3_VAL
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/* default is disable, so don't need to force this */
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bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
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# endif
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# ifdef CONFIG_EBIU_DDRQUE_VAL
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bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
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# endif
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#endif
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serial_putc('Q');
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/* Are we coming out of hibernate (suspend to memory) ?
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* The memory layout is:
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* 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
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* 0x4: return address
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* 0x8: stack pointer
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*
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* SCKELOW is unreliable on older parts (anomaly 307)
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*/
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if (ANOMALY_05000307 || vr_ctl & 0x8000) {
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uint32_t *hibernate_magic = 0;
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__builtin_bfin_ssync(); /* make sure memory controller is done */
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if (hibernate_magic[0] == 0xDEADBEEF) {
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serial_putc('R');
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bfin_write_EVT15(hibernate_magic[1]);
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bfin_write_IMASK(EVT_IVG15);
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__asm__ __volatile__ (
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/* load reti early to avoid anomaly 281 */
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"reti = %0;"
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/* clear hibernate magic */
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"[%0] = %1;"
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/* load stack pointer */
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"SP = [%0 + 8];"
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/* lower ourselves from reset ivg to ivg15 */
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"raise 15;"
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"rti;"
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:
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: "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
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);
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}
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}
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serial_putc('S');
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/* Program the async banks controller. */
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bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
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@ -394,39 +517,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
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#endif
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serial_putc('I');
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/* Program the external memory controller. */
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#ifdef EBIU_RSTCTL
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bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
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bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
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bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
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bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
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# ifdef CONFIG_EBIU_DDRCTL3_VAL
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/* default is disable, so don't need to force this */
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bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
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# endif
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#else
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bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
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bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
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bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
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#endif
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serial_putc('N');
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/* Restore all peripheral wakeups. */
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(-1);
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bfin_write_SIC_IWR1(-1);
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(-1);
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# endif
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#elif defined(SICA_IWR0)
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bfin_write_SICA_IWR0(-1);
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bfin_write_SICA_IWR1(-1);
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#else
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bfin_write_SIC_IWR(-1);
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#endif
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serial_putc('T');
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/* tell the bootrom where our entry point is */
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if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
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@ -95,35 +95,63 @@ ENTRY(_start)
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/* Save RETX so we can pass it while booting Linux */
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r7 = RETX;
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
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/* In bypass mode, we don't have an LDR with an init block
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* so we need to explicitly call it ourselves. This will
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* reprogram our clocks and setup our async banks.
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*/
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/* XXX: we should DMA this into L1, put external memory into
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* self refresh, and then jump there ...
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/* Figure out where we are currently executing so that we can decide
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* how to best reprogram and relocate things. We'll pass below:
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* R4: load address of _start
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* R5: current (not load) address of _start
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*/
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serial_early_puts("Find ourselves");
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call _get_pc;
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r3 = 0x0;
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r3.h = 0x2000;
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cc = r0 < r3 (iu);
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if cc jump .Lproc_initialized;
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serial_early_puts("Program Clocks");
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call _initcode;
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/* Since we reprogrammed SCLK, we need to update the serial divisor */
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serial_early_set_baud
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.Lproc_initialized:
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#endif
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.Loffset:
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r1.l = .Loffset;
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r1.h = .Loffset;
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r4.l = _start;
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r4.h = _start;
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r3 = r1 - r4;
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r5 = r0 - r3;
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/* Inform upper layers if we had to do the relocation ourselves.
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* This allows us to detect whether we were loaded by 'go 0x1000'
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* or by the bootrom from an LDR. "r6" is "loaded_from_ldr".
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* or by the bootrom from an LDR. "R6" is "loaded_from_ldr".
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*/
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r6 = 1 (x);
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cc = r4 == r5;
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if cc jump .Lnorelocate;
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r6 = 0 (x);
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/* In bypass mode, we don't have an LDR with an init block
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* so we need to explicitly call it ourselves. This will
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* reprogram our clocks, memory, and setup our async banks.
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*/
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serial_early_puts("Program Clocks");
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/* if we're executing >=0x20000000, then we dont need to dma */
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r3 = 0x0;
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r3.h = 0x2000;
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cc = r5 < r3 (iu);
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if cc jump .Ldma_and_reprogram;
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call _initcode;
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jump .Lprogrammed;
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/* we're sitting in external memory, so dma into L1 and reprogram */
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.Ldma_and_reprogram:
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r0.l = LO(L1_INST_SRAM);
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r0.h = HI(L1_INST_SRAM);
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r1.l = __initcode_start;
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r1.h = __initcode_start;
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r2.l = __initcode_end;
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r2.h = __initcode_end;
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r2 = r2 - r1; /* convert r2 into length of initcode */
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r1 = r1 - r4; /* convert r1 from load address of initcode ... */
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r1 = r1 + r5; /* ... to current (not load) address of initcode */
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p3 = r0;
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call _dma_memcpy_nocache;
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call (p3);
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/* Since we reprogrammed SCLK, we need to update the serial divisor */
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.Lprogrammed:
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serial_early_set_baud
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/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
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* monitor location in the end of RAM. We know that memcpy() only
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@ -132,19 +160,8 @@ ENTRY(_start)
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* it yet (see "lower to 15" below).
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*/
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serial_early_puts("Relocate");
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call _get_pc;
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.Loffset:
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r2.l = .Loffset;
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r2.h = .Loffset;
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r3.l = _start;
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r3.h = _start;
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r2 = r2 - r3;
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r1 = r0 - r2;
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cc = r1 == r3;
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if cc jump .Lnorelocate;
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r6 = 0 (x);
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r0 = r3;
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r0 = r4;
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r1 = r5;
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r2.l = LO(CONFIG_SYS_MONITOR_LEN);
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r2.h = HI(CONFIG_SYS_MONITOR_LEN);
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call _memcpy_ASM;
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