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OMAP3: Add OMAP3 auto detection
This patch adds OMAP3 cpu type auto detection based on OMAP3 register and removes hardcoded values. Signed-off-by: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
This commit is contained in:
parent
f956fd0338
commit
6530a8bf8a
8 changed files with 49 additions and 8 deletions
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@ -27,7 +27,6 @@ const omap3_sysinfo sysinfo = {
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SDP_3430_V1,
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SDP_3430_V2,
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DDR_STACKED,
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"3530",
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"OMAP3 Beagle board",
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#if defined(CONFIG_ENV_IS_IN_ONENAND)
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"OneNAND",
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@ -27,7 +27,6 @@ const omap3_sysinfo sysinfo = {
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OMAP3EVM_V1,
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OMAP3EVM_V2,
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DDR_DISCRETE,
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"35X-Family",
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"OMAP3 EVM board",
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#if defined(CONFIG_ENV_IS_IN_ONENAND)
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"OneNAND",
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@ -27,7 +27,6 @@ const omap3_sysinfo sysinfo = {
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SDP_3430_V1,
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SDP_3430_V2,
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DDR_STACKED,
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"3503",
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"Gumstix Overo board",
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#if defined(CONFIG_ENV_IS_IN_ONENAND)
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"OneNAND",
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@ -27,7 +27,6 @@ const omap3_sysinfo sysinfo = {
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SDP_3430_V1,
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SDP_3430_V2,
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DDR_STACKED,
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"3530",
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"OMAP3 Pandora",
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"NAND",
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};
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@ -31,7 +31,6 @@ const omap3_sysinfo sysinfo = {
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SDP_3430_V1,
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SDP_3430_V2,
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DDR_STACKED,
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"3430",
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"OMAP3 Zoom MDK Rev 1",
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"NAND",
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};
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@ -36,6 +36,14 @@ static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
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static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
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static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
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/******************************************
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* get_cpu_type(void) - extract cpu info
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******************************************/
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u32 get_cpu_type(void)
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{
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return readl(&ctrl_base->ctrl_omap_stat);
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}
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/******************************************
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* get_cpu_rev(void) - extract version info
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******************************************/
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@ -156,7 +164,25 @@ u32 get_board_rev(void)
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*********************************************************************/
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void display_board_info(u32 btype)
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{
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char *mem_s, *sec_s;
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char *cpu_s, *mem_s, *sec_s;
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switch (get_cpu_type()) {
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case OMAP3503:
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cpu_s = "3503";
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break;
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case OMAP3515:
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cpu_s = "3515";
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break;
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case OMAP3525:
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cpu_s = "3525";
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break;
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case OMAP3530:
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cpu_s = "3530";
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break;
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default:
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cpu_s = "35XX";
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break;
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}
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if (is_mem_sdr())
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mem_s = "mSDR";
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@ -180,7 +206,8 @@ void display_board_info(u32 btype)
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sec_s = "?";
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}
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printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", sysinfo.cpu_string,
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printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s,
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sec_s, get_cpu_rev());
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printf("%s + %s/%s\n", sysinfo.board_string,
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mem_s, sysinfo.nand_string);
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@ -35,11 +35,31 @@ typedef struct ctrl {
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unsigned short gpmc_nwe; /* 0xC4 */
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unsigned char res2[0x22A];
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unsigned int status; /* 0x2F0 */
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unsigned int gpstatus; /* 0x2F4 */
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unsigned char res3[0x08];
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unsigned int rpubkey_0; /* 0x300 */
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unsigned int rpubkey_1; /* 0x304 */
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unsigned int rpubkey_2; /* 0x308 */
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unsigned int rpubkey_3; /* 0x30C */
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unsigned int rpubkey_4; /* 0x310 */
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unsigned char res4[0x04];
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unsigned int randkey_0; /* 0x318 */
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unsigned int randkey_1; /* 0x31C */
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unsigned int randkey_2; /* 0x320 */
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unsigned int randkey_3; /* 0x324 */
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unsigned char res5[0x124];
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unsigned int ctrl_omap_stat; /* 0x44C */
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} ctrl_t;
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#else /* __ASSEMBLY__ */
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#define CONTROL_STATUS 0x2F0
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#endif /* __ASSEMBLY__ */
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/* cpu type */
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#define OMAP3503 0x5c00
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#define OMAP3515 0x1c00
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#define OMAP3525 0x4c00
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#define OMAP3530 0x0c00
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/* device type */
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#define DEVICE_MASK (0x7 << 8)
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#define SYSBOOT_MASK 0x1F
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@ -25,7 +25,6 @@ typedef struct {
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u32 board_type_v1;
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u32 board_type_v2;
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u32 mtype;
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char *cpu_string;
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char *board_string;
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char *nand_string;
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} omap3_sysinfo;
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