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avr32: Add gclk helper functions
Add two helper functions for configuring and enabling generic clocks: - gclk_enable_output: Enables output on a GCLKx pin - gclk_set_rate: Configures a gclk to run at a specific rate This should eliminate any reason to go mucking about with PM registers from board code. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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ab0df36fc7
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98090cd75c
2 changed files with 122 additions and 2 deletions
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@ -25,6 +25,7 @@
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#include <asm/arch/clk.h>
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#include <asm/arch/memory-map.h>
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#include <asm/arch/portmux.h>
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#include "sm.h"
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@ -66,3 +67,27 @@ void clk_init(void)
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sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
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#endif
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}
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unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
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unsigned long rate, unsigned long parent_rate)
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{
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unsigned long divider;
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if (rate == 0 || parent_rate == 0) {
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sm_writel(PM_GCCTRL(id), 0);
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return 0;
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}
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divider = (parent_rate + rate / 2) / rate;
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if (divider <= 1) {
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sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
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rate = parent_rate;
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} else {
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divider = min(255, divider / 2 - 1);
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sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
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| SM_BF(DIV, divider));
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rate = parent_rate / (2 * (divider + 1));
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}
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return rate;
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}
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@ -23,11 +23,13 @@
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#define __ASM_AVR32_ARCH_CLK_H__
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#include <asm/arch/chip-features.h>
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#include <asm/arch/portmux.h>
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#ifdef CONFIG_PLL
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#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
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#define PLL0_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
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#define MAIN_CLK_RATE PLL0_RATE
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#else
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#define MAIN_CLK_RATE (CFG_OSC0_HZ)
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#define MAIN_CLK_RATE (CFG_OSC0_HZ)
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#endif
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static inline unsigned long get_cpu_clk_rate(void)
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@ -87,4 +89,97 @@ extern void gclk_init(void) __attribute__((weak));
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/* Board code may need the SDRAM base clock as a compile-time constant */
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#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
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/* Generic clock control */
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enum gclk_parent {
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GCLK_PARENT_OSC0 = 0,
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GCLK_PARENT_OSC1 = 1,
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GCLK_PARENT_PLL0 = 2,
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GCLK_PARENT_PLL1 = 3,
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};
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/* Some generic clocks have specific roles */
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#define GCLK_DAC_SAMPLE_CLK 6
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#define GCLK_LCDC_PIXCLK 7
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extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
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unsigned long rate, unsigned long parent_rate);
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/**
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* gclk_set_rate - configure and enable a generic clock
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* @id: Which GCLK[id] to enable
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* @parent: Parent clock feeding the GCLK
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* @rate: Target rate of the GCLK in Hz
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*
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* Returns the actual GCLK rate in Hz, after rounding to the nearest
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* supported rate.
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*
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* All three parameters are usually constant, hence the inline.
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*/
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static inline unsigned long gclk_set_rate(unsigned int id,
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enum gclk_parent parent, unsigned long rate)
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{
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unsigned long parent_rate;
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if (id > 7)
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return 0;
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switch (parent) {
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case GCLK_PARENT_OSC0:
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parent_rate = CFG_OSC0_HZ;
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break;
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#ifdef CFG_OSC1_HZ
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case GCLK_PARENT_OSC1:
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parent_rate = CFG_OSC1_HZ;
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break;
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#endif
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#ifdef PLL0_RATE
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case GCLK_PARENT_PLL0:
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parent_rate = PLL0_RATE;
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break;
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#endif
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#ifdef PLL1_RATE
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case GCLK_PARENT_PLL1:
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parent_rate = PLL1_RATE;
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break;
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#endif
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default:
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parent_rate = 0;
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break;
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}
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return __gclk_set_rate(id, parent, rate, parent_rate);
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}
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/**
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* gclk_enable_output - enable output on a GCLK pin
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* @id: Which GCLK[id] pin to enable
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* @drive_strength: Drive strength of external GCLK pin, if applicable
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*/
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static inline void gclk_enable_output(unsigned int id,
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unsigned long drive_strength)
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{
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switch (id) {
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case 0:
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portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 1:
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portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 2:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 3:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 4:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
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PORTMUX_FUNC_A, drive_strength);
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break;
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}
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}
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#endif /* __ASM_AVR32_ARCH_CLK_H__ */
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