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86xx: Update CPU info output on bootup
- Update style of 86xx CPU information on boot to more closely
match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output
== Before ==
Freescale PowerPC
CPU:
Core: E600 Core 0, Version: 0.2, (0x80040202)
System: Unknown, Version: 2.1, (0x80900121)
Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC
== After ==
CPU: 8641D, Version: 2.1, (0x80900121)
Core: E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
CPU:1066.667 MHz, MPX:533.333 MHz
DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1: D-cache 32 KB enabled
I-cache 32 KB enabled
L2: 512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This commit is contained in:
Peter Tyser
Andy Fleming
parent
22c00f8d7d
commit
a1c8a71926
2 changed files with 48 additions and 42 deletions
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@ -50,49 +50,25 @@ checkcpu(void)
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uint pvr, svr;
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uint ver;
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uint major, minor;
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char buf1[32], buf2[32];
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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puts("Freescale PowerPC\n");
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pvr = get_pvr();
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ver = PVR_VER(pvr);
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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puts("CPU:\n");
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puts(" Core: ");
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switch (ver) {
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case PVR_VER(PVR_86xx):
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{
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uint msscr0 = mfspr(MSSCR0);
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printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
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if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
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puts("\n Core1Translation Enabled");
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debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
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}
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break;
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default:
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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uint msscr0 = mfspr(MSSCR0);
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts(" System: ");
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puts("CPU: ");
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switch (ver) {
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case SVR_8641:
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if (SVR_SUBVER(svr) == 1) {
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puts("8641D");
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} else {
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puts("8641");
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}
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break;
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break;
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case SVR_8641D:
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puts("8641D");
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break;
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case SVR_8610:
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puts("8610");
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break;
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@ -101,26 +77,50 @@ checkcpu(void)
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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puts("Core: ");
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pvr = get_pvr();
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ver = PVR_E600_VER(pvr);
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major = PVR_E600_MAJ(pvr);
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minor = PVR_E600_MIN(pvr);
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printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
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if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
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puts("\n Core1Translation Enabled");
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debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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get_sys_info(&sysinfo);
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puts(" Clocks: ");
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printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
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printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
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printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
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puts("Clock Configuration:\n");
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printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
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printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
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printf(" DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, sysinfo.freqSystemBus / 2),
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strmhz(buf2, sysinfo.freqSystemBus));
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if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
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printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000);
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printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
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} else {
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printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
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sysinfo.freqLocalBus);
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}
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puts(" L2: ");
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if (get_l2cr() & 0x80000000)
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puts("Enabled\n");
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else
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puts("L1: D-cache 32 KB enabled\n");
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puts(" I-cache 32 KB enabled\n");
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puts("L2: ");
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if (get_l2cr() & 0x80000000) {
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#if defined(CONFIG_MPC8610)
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puts("256");
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#elif defined(CONFIG_MPC8641)
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puts("512");
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#endif
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puts(" KB enabled\n");
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} else {
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puts("Disabled\n");
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}
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return 0;
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}
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@ -779,6 +779,13 @@
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#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
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#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
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/* e600 core PVR fields */
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#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */
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#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */
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#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */
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#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */
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/* Processor Version Numbers */
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#define PVR_403GA 0x00200000
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@ -859,7 +866,6 @@
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#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
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#define PVR_86xx 0x80040000
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#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
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#define PVR_VIRTEX5 0x7ff21912
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