mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
mpc8641: Support 36-bit physical addressing
This patch creates a memory map with all the devices in 36-bit physical space, in addition to the 32-bit map. The CCSR relocation is moved (again, sorry) to allow for the physical address to be 36 bits - this requires translation to be enabled. With 36-bit physical addressing enabled, we are no longer running with VA=PA translations. This means we have to distinguish between the two in the config file. The existing region name is used to indicate the virtual address, and a _PHYS variety is created to represent the physical address. Large physical addressing is not enabled by default. Set CONFIG_PHYS_64BIT in the config file to turn this on. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
This commit is contained in:
Becky Bruce
Jon Loeliger
parent
c759a01a00
commit
3111d32c49
4 changed files with 192 additions and 53 deletions
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@ -31,12 +31,13 @@
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* if PCI
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* if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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* else if RIO
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* else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
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* 0x8000_0000 0x9fff_ffff RapidIO 512M
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* endif
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* (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
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* 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
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* 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
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* 0xffe0_0000 0xffef_ffff CCSRBAR 1M
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@ -53,15 +54,15 @@ struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
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#endif
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#ifdef CONFIG_PCI
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SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
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#elif defined(CONFIG_RIO)
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SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
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#endif
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SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
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SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -209,11 +209,6 @@ boot_warm:
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sync
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#endif
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#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
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/* setup ccsrbar now while we're in real mode */
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bl setup_ccsrbar
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#endif
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/*
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* Calculate absolute address in FLASH and jump there
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*------------------------------------------------------*/
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@ -267,6 +262,10 @@ addr_trans_enabled:
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sync
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#endif
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#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
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bl setup_ccsrbar
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#endif
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/* set up the stack pointer in our newly created
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* cache-ram (r1) */
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lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
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@ -414,6 +413,26 @@ early_bats:
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mtspr DBAT6L, r4
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mtspr DBAT6U, r3
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isync
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#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
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/* IBAT 7 */
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lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
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ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
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lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
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ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
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mtspr IBAT7L, r4
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mtspr IBAT7U, r3
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isync
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/* DBAT 7 */
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lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
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ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
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lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
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ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
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mtspr DBAT7L, r4
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mtspr DBAT7U, r3
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isync
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#endif
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blr
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.globl clear_tlbs
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@ -860,17 +879,20 @@ setup_ccsrbar:
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lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
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ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
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lis r5, CONFIG_SYS_CCSRBAR@h
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ori r5, r5, CONFIG_SYS_CCSRBAR@l
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srwi r6,r5,12
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stw r6, 0(r4)
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lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
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ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
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srwi r5,r5,12
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li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
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rlwimi r5,r6,20,8,11
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stw r5, 0(r4) /* Store physical value of CCSR */
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isync
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lis r5, 0xffff
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ori r5,r5,0xf000
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lis r5, TEXT_BASE@h
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ori r5,r5,TEXT_BASE@l
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lwz r5, 0(r5)
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isync
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/* Use VA of CCSR to do read */
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lis r3, CONFIG_SYS_CCSRBAR@h
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lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
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isync
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@ -113,6 +113,9 @@ To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
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-------------
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NOTE: RIO and PCI are mutually exclusive, so they share an address
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For 32-bit u-boot, devices are mapped so that the virtual address ==
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the physical address, and the map looks liks this:
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Memory Range Device Size
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------------ ------ ----
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0x0000_0000 0x7fff_ffff DDR 2G
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@ -127,6 +130,27 @@ NOTE: RIO and PCI are mutually exclusive, so they share an address
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0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
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0xef80_0000 0xefff_ffff Flash 8M
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For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
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However, the physical map is altered to reside in 36-bit space, as follows.
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Addresses are no longer mapped with VA == PA. All accesses from
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software use the VA; the PA is only used for setting up windows
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and mappings. Note that the low 32 bits are the same as the VA above;
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only the top 4 bits vary:
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Memory Range Device Size
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------------ ------ ----
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0x0_0000_0000 0x0_7fff_ffff DDR 2G
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0xc_8000_0000 0xc_9fff_ffff RIO MEM 512M
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0xc_8000_0000 0xc_9fff_ffff PCI1/PEX1 MEM 512M
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0xc_a000_0000 0xc_bfff_ffff PCI2/PEX2 MEM 512M
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0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
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0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
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0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
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0x0_f840_0000 0xf_f840_3fff Stack space 32K
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0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
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0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
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0xf_ef80_0000 0xf_efff_ffff Flash 8M
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5. pixis_reset command
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--------------------
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A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
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@ -38,6 +38,7 @@
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#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
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#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
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#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
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/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
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#ifdef RUN_DIAG
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#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
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@ -91,6 +92,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/*
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* With the exception of PCI Memory and Rapid IO, most devices will simply
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* add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
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* when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
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*/
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
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#else
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#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
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#endif
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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@ -99,6 +111,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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/* Physical addresses */
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
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#else
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
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#endif
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#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
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#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
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@ -160,23 +180,31 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
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#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
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| CONFIG_SYS_PHYS_ADDR_HIGH)
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
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/* Convert an address into the right format for the BR registers */
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#ifdef CONFIG_PHYS_64BIT
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#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
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((x & 0x300000000ULL) >> 19)))
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#else
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#define BR_PHYS_ADDR(x) (x & 0xffff8000)
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#endif
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#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \
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| 0x00001001) /* port size 16bit */
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#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
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#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
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| 0x00001001) /* port size 16bit */
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#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
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#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
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| 0x00001001) /* port size 16bit */
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#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
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#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
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| 0x00001001) /* port size 16bit */
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#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
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#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \
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| 0x00000801) /* port size 8bit */
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#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
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#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
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| 0x00000801) /* port size 8bit */
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#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
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/*
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* The LBC_BASE is the base of the region that contains the PIXIS and the CF.
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@ -184,9 +212,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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* required for the smallest BAT mapping, so there's a 64k hole.
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*/
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#define CONFIG_SYS_LBC_BASE 0xffde0000
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#define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \
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| CONFIG_SYS_PHYS_ADDR_HIGH)
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#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
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#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
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#define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
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#define PIXIS_SIZE 0x00008000 /* 32k */
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#define PIXIS_ID 0x0 /* Board ID at offset 0 */
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#define PIXIS_VER 0x1 /* Board version at offset 1 */
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@ -206,6 +237,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
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#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
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#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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@ -295,7 +327,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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* RapidIO MMU
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*/
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#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL
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#else
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#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
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#endif
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#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
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/*
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@ -303,10 +339,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
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#else
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#endif
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
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#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
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| CONFIG_SYS_PHYS_ADDR_HIGH)
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
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/* For RTL8139 */
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@ -315,9 +357,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
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+ CONFIG_SYS_PCI1_MEM_SIZE)
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#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
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#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
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+ CONFIG_SYS_PCI1_MEM_SIZE)
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#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
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+ CONFIG_SYS_PCI1_IO_SIZE)
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#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
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+ CONFIG_SYS_PCI1_IO_SIZE)
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#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
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@ -349,10 +394,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
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/*PCIE video card used*/
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#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS
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#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT
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/*PCI video card used*/
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/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
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/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
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/* video */
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#define CONFIG_VIDEO
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@ -365,7 +410,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_ATI_RADEON_FB
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#define CONFIG_VIDEO_LOGO
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/*#define CONFIG_CONSOLE_CURSOR*/
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
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#endif
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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@ -419,6 +464,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif /* CONFIG_TSEC_ENET */
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/* Contort an addr into the format needed for BATs */
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#ifdef CONFIG_PHYS_64BIT
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#define BAT_PHYS_ADDR(x) ((unsigned long) \
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((x & 0x00000000ffffffffULL) | \
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((x & 0x0000000e00000000ULL) >> 24) | \
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((x & 0x0000000100000000ULL) >> 30)))
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#else
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#define BAT_PHYS_ADDR(x) (x)
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#endif
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/* Put high physical address bits into the BAT format */
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#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
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#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
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/*
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* BAT0 DDR
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*/
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@ -430,12 +490,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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/*
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* BAT1 LBC (PIXIS/CF)
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*/
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#define CONFIG_SYS_DBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
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| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
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| BATL_PP_RW | BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
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| BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
|
||||
| BATL_PP_RW | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
|
||||
|
||||
/* if CONFIG_PCI:
|
||||
|
|
@ -444,14 +505,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
* BAT2 Rapidio Memory
|
||||
*/
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \
|
||||
#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \
|
||||
| BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
|
||||
#else /* CONFIG_RIO */
|
||||
#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT | \
|
||||
BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
|
||||
| BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
|
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
|
||||
|
|
@ -461,22 +531,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
|
||||
/*
|
||||
* BAT3 CCSR Space
|
||||
* This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
|
||||
* instead. The assembler chokes on ULL.
|
||||
*/
|
||||
#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
|
||||
| PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
|
||||
| PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
|
||||
| BATU_VP)
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
|
||||
| PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
|
||||
| PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
|
||||
|
||||
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
|
||||
#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
|
||||
| BATU_BL_1M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
|
||||
#endif
|
||||
|
||||
/*
|
||||
* BAT4 PCI1_IO and PCI2_IO
|
||||
*/
|
||||
#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_128K \
|
||||
#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
|
||||
| BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
|
||||
|
||||
/*
|
||||
|
|
@ -490,12 +581,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
/*
|
||||
* BAT6 FLASH
|
||||
*/
|
||||
#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
|
||||
| BATL_PP_RW | BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
|
||||
| BATU_VP)
|
||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
|
||||
| BATL_PP_RW | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
|
||||
|
||||
/* Map the last 1M of flash where we're running from reset */
|
||||
|
|
@ -652,8 +744,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
"ramdiskfile=your.ramdisk.u-boot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=mpc8641_hpcn.dtb\0" \
|
||||
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
|
||||
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
|
||||
"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
|
||||
"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
|
||||
"maxcpus=2"
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue