mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
44a01a73e8
4 changed files with 194 additions and 246 deletions
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@ -21,8 +21,4 @@
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# MA 02111-1307 USA
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||||
#
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||||
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#
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||||
# esd PMC405 boards
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#
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||||
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TEXT_BASE = 0xFFFC0000
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TEXT_BASE = 0xFFF80000
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|
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@ -2,7 +2,7 @@
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|||
* (C) Copyright 2001-2003
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2005
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* (C) Copyright 2005-2009
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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@ -26,6 +26,7 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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@ -40,7 +41,6 @@ const unsigned char fpgadata[] =
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};
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int filesize = sizeof(fpgadata);
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int board_early_init_f (void)
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{
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/*
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@ -55,107 +55,104 @@ int board_early_init_f (void)
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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* EBC Configuration Register:
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* set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (epcr, 0xa8400000);
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/*
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* Setup GPIO pins
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*/
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mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
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CONFIG_SYS_FPGA_DONE | \
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CONFIG_SYS_XEREADY | \
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CONFIG_SYS_NONMONARCH | \
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mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT |
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CONFIG_SYS_FPGA_DONE |
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CONFIG_SYS_XEREADY |
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CONFIG_SYS_NONMONARCH |
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CONFIG_SYS_REV1_2) << 5));
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if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
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if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
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/* rev 1.2 boards */
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mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
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mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE |
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CONFIG_SYS_SELF_RST) << 5));
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}
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out32(GPIO0_OR, 0);
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out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */
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out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
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/* setup for output */
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out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
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CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
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/* - check if rev1_2 is low, then:
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* - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST#
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/*
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* - check if rev1_2 is low, then:
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* - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
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* in TCR to assert INTA# or SELFRST#
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*/
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_r (void)
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{
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */
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/* deassert EREADY# */
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out_be32((void *)GPIO0_OR,
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in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
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return (0);
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}
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ushort pmc405_pci_subsys_deviceid(void)
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{
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ulong val;
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val = in32(GPIO0_IR);
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val = in_be32((void *)GPIO0_IR);
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if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
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if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
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/* check monarch# signal */
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if (val & CONFIG_SYS_NONMONARCH)
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
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}
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
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}
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
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}
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/*
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* Check Board Identity:
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* Check Board Identity
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*/
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int checkboard (void)
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{
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ulong val;
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char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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int i = getenv_r("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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if (i == -1)
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puts ("### No HW ID - assuming PMC405");
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} else {
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else
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puts(str);
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}
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val = in32(GPIO0_IR);
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val = in_be32((void *)GPIO0_IR);
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if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
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puts(" rev1.2 (");
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if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
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if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
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puts("non-");
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}
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puts("monarch)");
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} else {
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} else
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puts(" <=rev1.1");
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}
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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@ -166,43 +163,3 @@ void reset_phy(void)
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lxt971_no_sleep();
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#endif
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}
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int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong addr;
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volatile uchar *ptr;
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volatile uchar val;
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int i;
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addr = simple_strtol (argv[1], NULL, 16) + 0x16;
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i = 0;
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for (;;) {
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ptr = (uchar *)addr;
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for (i=0; i<8; i++) {
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*ptr = i;
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val = *ptr;
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if (val != i) {
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printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
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return 0;
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}
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/* Abort if ctrl-c was pressed */
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if (ctrlc()) {
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puts("\nAbort\n");
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return 0;
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}
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ptr++;
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}
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}
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return 0;
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}
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U_BOOT_CMD(
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cantest, 3, 1, do_cantest,
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"Test CAN controller",
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NULL
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);
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@ -1028,10 +1028,10 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
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#endif
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}
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/* Set up 16GB inbound memory window at 0 */
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/* Set up 4GB inbound memory window at 0 */
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out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
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out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
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out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
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out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
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out_le32(mbase + PECFG_BAR0LMPA, 0);
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out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
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@ -12,7 +12,7 @@
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
|
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@ -21,16 +21,11 @@
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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@ -45,13 +40,22 @@
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTCOMMAND
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/* Only interrupt boot if space is pressed. */
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#undef CONFIG_AUTOBOOT_DELAY_STR
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#define CONFIG_PREBOOT /* enable preboot variable */
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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|
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@ -59,11 +63,8 @@
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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|
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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|
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
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|
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/*
|
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* BOOTP options
|
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|
|
@ -73,7 +74,6 @@
|
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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|
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|
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/*
|
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* Command line configuration.
|
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*/
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|
|
@ -91,249 +91,241 @@
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#define CONFIG_CMD_UNIVERSE
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#define CONFIG_CMD_EEPROM
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|
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|
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
|
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|
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#undef CONFIG_WATCHDOG /* watchdog disabled */
|
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#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
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#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
|
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#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
|
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#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */
|
||||
#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
|
||||
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
|
||||
#define CONFIG_SYS_BASE_BAUD 806400
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 }
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
/* resource configuration */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
/* resource configuration */
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
|
||||
|
||||
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
|
||||
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
|
||||
|
||||
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
|
||||
|
||||
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
|
||||
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */
|
||||
|
||||
#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
|
||||
#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#if 1
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
|
||||
#else /* old mapping */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------
|
||||
#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
|
||||
#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
|
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
|
||||
|
||||
#define CONFIG_PRAM 0 /* use pram variable to overwrite */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||
#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT }
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
|
||||
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
|
||||
CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */
|
||||
|
||||
/*
|
||||
* JFFS2 partitions - second bank contains u-boot
|
||||
*
|
||||
*/
|
||||
/* No command line, one static partition, whole device */
|
||||
#undef CONFIG_JFFS2_CMDLINE
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0x01b00000
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00400000
|
||||
|
||||
/* mtdparts command line support */
|
||||
/* Note: fake mtd_id used, no linux mtd map file */
|
||||
/*
|
||||
#define CONFIG_JFFS2_CMDLINE
|
||||
#define MTDIDS_DEFAULT "nor0=pmc405-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)"
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment Variable setup
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
|
||||
#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
|
||||
/* total size of a CAT24WC16 is 2048 bytes */
|
||||
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
|
||||
#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
|
||||
/* environment starts at the beginning of the EEPROM */
|
||||
#define CONFIG_ENV_OFFSET 0x000
|
||||
#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
|
||||
#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
|
||||
|
||||
/*
|
||||
* I2C EEPROM (CAT24WC16) for environment
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */
|
||||
/* 16 byte page write mode using*/
|
||||
/* last 4 bits of the address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
/* last 4 bits of the address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
|
||||
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
|
||||
#define CAN_BA 0xF0000000 /* CAN Base Address */
|
||||
#define RTC_BA 0xF0000500 /* RTC Base Address */
|
||||
#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
|
||||
#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
|
||||
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
|
||||
#define CAN_BA 0xF0000000 /* CAN Base Addres */
|
||||
#define RTC_BA 0xF0000500 /* RTC Base Address */
|
||||
#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
|
||||
/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
|
||||
#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000)
|
||||
|
||||
/* Memory Bank 1 (Flash Bank 1) initialization */
|
||||
/* Memory Bank 1 (Flash Bank 1) initialization */
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
|
||||
/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
|
||||
#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000)
|
||||
|
||||
/* Memory Bank 2 (CAN0, 1, RTC) initialization */
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
|
||||
#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
/* Memory Bank 2 (CAN0, 1, RTC) initialization */
|
||||
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x03000440
|
||||
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000)
|
||||
|
||||
/* Memory Bank 3 -> unused */
|
||||
|
||||
/* Memory Bank 4 (NVRAM) initialization */
|
||||
#define CONFIG_SYS_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
|
||||
#define CONFIG_SYS_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
/* Memory Bank 4 (NVRAM) initialization */
|
||||
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
|
||||
#define CONFIG_SYS_EBC_PB4AP 0x03000440
|
||||
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* FPGA stuff
|
||||
*/
|
||||
#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
|
||||
#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
|
||||
#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
|
||||
#define CONFIG_SYS_FPGA_MAX_SIZE (32 * 1024) /* 32kByte for CPLD */
|
||||
|
||||
/* FPGA program pin configuration */
|
||||
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
|
||||
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
|
||||
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
|
||||
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
|
||||
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
|
||||
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
|
||||
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */
|
||||
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */
|
||||
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
|
||||
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */
|
||||
|
||||
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
|
||||
/* pass Ethernet MAC to VxWorks */
|
||||
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* GPIOs
|
||||
*/
|
||||
#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO24 */
|
||||
#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
|
||||
#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
|
||||
#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
|
||||
#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
|
||||
#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */
|
||||
#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */
|
||||
#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
|
||||
#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
|
||||
#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
|
||||
#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
|
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
|
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
/* inside of SDRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
|
||||
|
||||
/* End of used area in RAM */
|
||||
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
|
||||
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
|
||||
CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
|
|
@ -341,7 +333,10 @@
|
|||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue