Commit graph

2558 commits

Author SHA1 Message Date
Rosy Song
f1f943e96c drivers: add ethernet support for qca953x in ag7xxx driver
Signed-off-by: Rosy Song <rosysong@rosinson.com>
2019-04-12 17:32:50 +02:00
Faiz Abbas
0229c9330d board: ti: am335x: Add platdata for cpsw in SPL
The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL
is enabled. Use static platdata instead to save space.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12 08:05:54 -04:00
Faiz Abbas
8a616cc292 net: ti: cpsw: Enable DM_FLAG_PRE_RELOC
Add DM_FLAG_PRE_RELOC to make the driver probe in SPL.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12 08:05:54 -04:00
Faiz Abbas
c3b460a516 net: ti: cpsw: Block off ofdata_to_platdata with OF_CONTROL
The ofdata_to_platdata function should not be called if OF_CONTROL is
not enabled because fdtdec_* calls will fail. Block the function with
OF_CONTROL

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12 08:05:53 -04:00
Faiz Abbas
a58d222df9 net: ti: cpsw-common: Isolate getting syscon address from assigning macid
ti_cm_get_macid() is used to get a syscon node from the dt, read the
efuse address and then assign the macid read from the address. Divide
these two steps into separate functions one of which can be called from
ofdata_to_platdata() while the other can be called from _probe(). This
ensures that platdata can be assigned statically in a board file when
OF_CONTROL is not enabled. Also add a macid_sel_compat in private data
to get information about the macid byte placement.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12 08:05:53 -04:00
Faiz Abbas
f32a816c26 net: ti: cpsw: Convert cpsw_platform_data to a pointer in cpsw_priv
Convert cpsw_platform_data to a pointer in cpsw_priv. Allocate it
dynamically and assign it as a part of eth_pdata. This helps in
isolating platform data handling and implementing platdata for SPL
in a board file.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12 08:05:53 -04:00
Faiz Abbas
e50f878c98 net: ti: cpsw: Move cpsw_phy_sel() to _probe()
cpsw_phy_sel() is a configuration step that should not be in
ofdata_to_platdata(). Add phy_sel_compat to the cpsw_platform_data
structure so that it is accessible in _probe. Then move the call of
cpsw_phy_sel() to _probe.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12 08:05:52 -04:00
Murali Karicheri
55d5cb1728 net: netcp: add support for phy with rgmii ids
Enhance the netcp driver to support phys that can be configured
for internal delay (rgmii-id, rgmii-rxid, rgmii-txid)

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:46 -04:00
Tom Rini
f95fdf237d Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various rmobile fixes
2019-04-11 14:29:22 -04:00
Marek Vasut
4a45e93ff3 net: sh_eth: Initialize PHY in probe() once
Reset and initialize the PHY once in the probe() function rather than
doing it over and over again is start() function. This requires us to
keep the clock enabled while the driver is in use. This significantly
reduces the time between transfers as the PHY doesn't have to restart
autonegotiation between transfers, which takes forever.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2019-04-09 18:19:10 +02:00
Stefan Roese
7bf9bca7c0 net: macb: Add small delay after link establishment
I've noticed that the first ethernet packet after PHY link establishment
is not tranferred correctly most of the time on my AT91SAM9G25 board.
Here I usually see a timeout of a few seconds, which is quite
annoying.

Adding a small delay (10ms in this case) after the link establishment
helps to solve this problem. With this patch applied, this timeout
on the first packet is not seen any more.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-09 09:28:50 +03:00
Andrejs Cainikovs
31d4045d4b net: dm: fec: Support phy-reset-post-delay property
As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
  a delay of phy-reset-post-delay milliseconds will be observed after the
  phy-reset-gpios has been toggled. Can be omitted thus no delay is
  observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-04-08 15:23:28 +02:00
Hannes Schmelzer
afbc31948a net: phy: implement fallback mechanism for negative phy adresses
Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Lukasz Majewski <lukma@denx.de>
2019-04-07 20:31:16 -04:00
Pramod Kumar
ba7eadd8e1 drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offset
Fix EC1 and EC2 read from correct offset 26, instead of 25

Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:01 +05:30
Meenakshi Aggarwal
43ad41e6ae mc : Reduce MC memory size to 128M
ls2088, ls1088 : minimum MC Memory size is 128 MB
lx2 : minimum MC memory size is 256 MB

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:00 +05:30
Ioana Ciocoi Radulescu
2e9f1bf588 driver: net: fsl-mc: Fix DPC MAC address fixup
If node /board_info/ports does not exist in the DPC file,
function mc_fixup_dpc() will skip not only MAC address fixup,
but also the cache flush at the end. This may cause the other
fixup changes (e.g. ICID related ones) to be ignored by MC.

Fixes: 1161dbcc0a ("drivers: net: fsl-mc: Include MAC addr fixup to DPL")

Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:00 +05:30
Pankaj Bansal
82fadccccf drivers: net: ldpaa_eth: check if the dpmac is enabled
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.

Therefore, in fsl_rgmii_init function of SOC, we will check if the
dpmac is enabled or not? if it is (fsl_serdes_init has already enabled
the dpmac), then don't enable it.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:00 +05:30
Hannes Schmelzer
b882005a18 drivers/net/fec: phy_init: remove redundant logic
The phy_connect_dev(...) function from phy.c does all the handling
(inclusive catching fixed-link).

So we drop here the single steps and call just phy_connect_dev(...).

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-13 09:14:35 +01:00
Atish Patra
fbcaa260e5 net: macb: Fix GEM hardware detection
Fix MID bit field check to correctly identify all GEM hardwares.

The check is updated as per macb driver in Linux location:
<linux_sources>/drivers/net/ethernet/cadence/macb_main.c:259

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-27 09:12:33 +08:00
Anup Patel
2e242f5f43 net: macb: Fix clk API usage for RISC-V systems
Don't fail in macb_enable_clk() if clk_enable() returns
-ENOSYS because we get -ENOSYS for fixed-rate clocks.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Simon Goldschmidt
6fb1eb1b76 arm: socfpga: gen5 enable designware_socfpga
Enable the socfpga specific designware ethernet driver by default for
socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a
MACH_SOCFPGA config.

This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-18 13:00:53 +01:00
Simon Goldschmidt
4f1267cea1 net: designware: socfpga: adapt to Gen5
This driver was written for Arria10, but it applies to Gen5, too.

The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the
syscon bits are encoded in the same register, thus an offset is needed.

This offset is already read from the devicetree, but for Arria10 it is
always 0, which is probably why it has been ignored. By using this
offset when writing the phy mode into the syscon regiter, we can use
this driver to set the phy mode for both of the MACs on Gen5.

Since the PHY mode bits in sysmgr are the same even for Stratix10,
let's drop the detection of the sub-mach by checking compatible
version and just use the same code for all FPGAs.

To work correctly, this driver depends on SYSCON and REGMAP, so select
those via Kconfig when it is enabeld.

Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift
offset is required).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-18 13:00:53 +01:00
Tim Harvey
69280961d7 net: mv88e61xx: fix autonegotiation on ports
phy_reset should be called before autoneg is setup

The only boards using MV88E61XX_SWITCH are:
 - alliedtelesis/SBx81LIFKW
 - alliedtelesis/SBx81LIFXCAT
 - gateworks/gw_ventana

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2019-02-15 13:01:28 +01:00
Adam Ford
8f1a5ac797 net: dm: fec: Fix regulator enable when using DM_REGULATOR
When DM_REGULATOR is enabled, the driver attempts to call
regulator_autoset() which expects the regulators to be on at boot
and/or always on and fails if they are not true.
For a more generic approach, this patch just calls
regulator_set_enable() which shouldn't have such restrictions.

Fixes: ad8c43cbca ("net: dm: fec: Support the phy-supply
binding")

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-15 12:41:12 +01:00
Horatiu Vultur
c5620aeea4 net: Add MSCC Luton networkd driver.
Add network driver for Microsemi Ethernet switch, it is
present on Luton SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
0b8f34dc8c net: mscc: Remove unused variables
Remove unused variables in the struct ocelot_private and make
miim variable static.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
45f2748c50 net: mscc: Move mac_table_add function into different file.
Move the function mac_table_add into a different file,
so it can be reused.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
36d04f52ff net: mscc: Move ocelot_send and ocelot_recv in a different file.
This functions can be reused by other MSCC SoCs therefore,
make them more generic and move them in separate files.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
2fff4a9b59 net: mscc: Move miim commands into separate file.
Move miim functions that can be shared in a different file inside
mscc_eswitch.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
4c66157f42 net: mscc: Move ocelot_switch to mscc_eswitch folder
Move file ocelot_switch to mscc_eswitch to prepare to add
new net drivers for other MSCC SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Martyn Welch
774ec60b74 Enable FEC driver to retrieve PHY address from device tree
Currently if we have more than one phy on the MDIO bus, we do not have a
good mechanism for determining which should be used at runtime. Enable the
FEC driver to determine the address for the PHY from the device tree.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-28 12:47:15 +01:00
Tom Rini
68489ed037 Merge branch 'master' of git://git.denx.de/u-boot-net 2019-01-24 15:30:06 -05:00
Valentin-catalin Neacsu
91c9cbabf9 net: phy: aquantia: Print information on config
Print information about Aquantia system interface and firmware loaded
on the phy.

Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Valentin-catalin Neacsu
c54bfbf96f net: phy: aquantia: Enable autoneg when on USXGMII
If System Interface protocol is USXGMII then enable USXGMII autoneg

Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Chris Packham
67bb984249 net: remove CONFIG_MCAST_TFTP
No mainline board enables CONFIG_MCAST_TFTP and there have been
compilation issues with the code for some time. Additionally, it has a
potential buffer underrun issue (reported as a side note in
CVE-2018-18439).

Remove the multicast TFTP code but keep the driver API for the future
addition of IPv6.

Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Chris Packham
1a4af5c562 net: move ether_crc to tsec driver
ether_crc was added to the core net code in commit 53a5c424bf
("multicast tftp: RFC2090") so that other drivers could use it. However
the only current user of it is tsec.c so move it there.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Carlo Caione
e57c9fdb04 net: phy: realtek: Add functions to read PHY's extended registers
According to the datasheet to access the extended registers we have to:

1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
   Standard Registers)

Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Ramon Fried
9043c4e0fc net: macb: fix mapping of registers
Some architectures (MIPS) needs mapping to access IOMEM.
Fix that.

Fixes: f1dcc19b21 ("net: macb: Convert to driver model")

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Aditya Prayoga
18bfc8fa84 net: mvneta: Add GPIO configuration support
This patch add GPIO configuration support in mvneta driver.
Driver will handle PHY reset. GPIO pins should be set in device tree.

Ported from mvpp2x
[https://patchwork.ozlabs.org/patch/799654/]

Initial discussion to port the changes into mvneta
[https://patchwork.ozlabs.org/patch/1005765/]

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Tested-by: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Chris Packham
92f129f4a0 net: mvgbe: fallback phy-mode to GMII
Some existing device trees don't specify a phy-mode so fallback to GMII
when a phy-mode is not provided.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Andreas Pretzsch
3b4cda34d4 net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.

The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.

Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.

Fix the check by using the bit width instead of hardcoded value(s).

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Baruch Siach
21586cdd50 net: mvpp2: mdio device per port
Current code forces all ports on a given Ethernet device to use the same
mdio device. In practice different ports might be wired to separate mdio
devices. Move the mdio device from the container struct mvpp2 to the per
port struct mvpp2_port.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Baruch Siach
acce753dfb net: mvpp2: fix lookup of mdio registers base address
Current mdio base lookup code relies on a 'reg' property at the upper CP
node. There is no 'reg' property there in current DT files of Armada
CP110. Use ofnode_get_addr() instead since it provides proper DT address
translation.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:27 -06:00
Simon Goldschmidt
7efb75b114 net: designware: clear padding bytes
Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.

Fix the padding code to zero out the padded bytes at the end.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:27 -06:00
Simon Goldschmidt
ae8ac8d423 net: designware: fix tx packet length
The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.

This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.

Fix this by correctly clearing the size mask before setting the new
length.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-24 11:35:27 -06:00
Pankaj Bansal
b3eabd82f2 net: phy: Add clause 45 identifier to phy_device
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:26 -06:00
Siva Durga Prasad Paladugu
c256d3f7c5 net: phy: Move fixed link code to separate routine
This patch moves fixed-link functionality code to a separate
routine inorder to make it more modular and cleaner.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 10:03:43 +01:00
Stefan Theil
1059858061 zynq-gem: Use appropriate cache flush/invalidate for RX and TX
The cache was only flushed before *transmitting* packets, but not
when receiving them, leading to an issue where new packets were
handed to the receive handler with old contents in cache. This
only happens when a lot of packets are received without sending
packages every now and then. Also flushing the receive buffers
in the transmit function makes no sense and can be removed.

Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Gregory CLEMENT
c8546163fa net: add MSCC Ocelot switch support
This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:26:44 +01:00
Tom Rini
77c07e7ed3 Add TFA boot flow for more boards
Add TFA boot defconfig for ls1088a and ls2088a.
 Add dts fixup for PCIe endpoint and root complex.
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Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for more boards

Add TFA boot defconfig for ls1088a and ls2088a.
Add dts fixup for PCIe endpoint and root complex.
2019-01-18 23:11:51 -05:00
Tom Rini
f83ef0dac8 - MIPS: mscc: various enhancements for Luton and Ocelot platforms
- MIPS: mscc: added support for Jaguar2 platform
 - MIPS: optimised SPL linker script
 - MIPS: bcm6368: fix restart flow issues
 - MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards
 - MIPS: mt7688: small fixes and enhancements
 - mmc: compile-out write support if disabled
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Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips

- MIPS: mscc: various enhancements for Luton and Ocelot platforms
- MIPS: mscc: added support for Jaguar2 platform
- MIPS: optimised SPL linker script
- MIPS: bcm6368: fix restart flow issues
- MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards
- MIPS: mt7688: small fixes and enhancements
- mmc: compile-out write support if disabled
2019-01-17 19:12:55 -05:00
Mian Yousaf Kaukab
7e96804975 fsl-layerscape: dpaa: fix fsl-mc status in fdt with bootefi
fsl-mc lazyapply command applies dpl from efi_exit_boot_services().
Status of fsl-mc node in working fdt is updated at this stage.
However, an efi application like grub may already have copied the fdt.
So the updates to fdt done at efi_exit_boot_services() may not be
visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply
command is used.

Fixes: b7b8410a8f (ls2080: Exit dpaa only right before exiting U-Boot)
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:49 -08:00
Álvaro Fernández Rojas
a4ae422570 net: bcm6368: fix restart flow issues
Correctly enable/disable bcm6368-net controller to avoid flow issues.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Tom Rini
aac0c29d4b Fix recent changes to serial API for driver model
Buildman clang support and a few fixes
 Small fixes to 'dm tree' and regmap test
 Improve sandbox build compatibility
 A few other minor fixes
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Merge tag 'dm-pull-15jan19' of git://git.denx.de/u-boot-dm

Fix recent changes to serial API for driver model
Buildman clang support and a few fixes
Small fixes to 'dm tree' and regmap test
Improve sandbox build compatibility
A few other minor fixes
2019-01-15 22:05:34 -05:00
Simon Glass
8405452e6a net: Fix error handling in sb_eth_raw_ofdata_to_platdata()
At present this stores the error number in an unsigned int so an error is
never detected. Use the existing signed variable instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-14 17:47:13 -07:00
Weijie Gao
23f17164d9 ethernet: MediaTek: add ethernet driver for MediaTek ARM-based SoCs
This patch adds ethernet support for Mediatek ARM-based SoCs, including
a minimum setup of the integrated switch.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-By: "Frank Wunderlich" <frank-w@public-files.de>
2019-01-14 17:43:18 -05:00
Tom Rini
522e035441 imx for 2019.01
- introduce support for i.MX8M
 - fix size limit for Vhybrid / pico boards
 - several board fixes
 - w1 driver for MX2x / MX5x
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Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x
2019-01-01 10:01:00 -05:00
Peng Fan
cd357ad112 imx: rename mx8m,MX8M to imx8m,IMX8M
Rename mx8m,MX8M to imx8m,IMX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
2019-01-01 14:12:18 +01:00
Michal Simek
7b4ea2d888 phy: Fix u-boot coruption when fixed-phy is used
When fixed-link phy is used subnode offset is used as phy address. This
number is bigger then space allocated for bus structure (allocated via
mdio_alloc).
bus->phymap[] array has PHY_MAX_ADDR size (32).
That's why writing bus->phymap[addr] where addr is < 0 or > PHY_MAX_ADDR
is causing write to memory which can caused full U-Boot crash.

The patch is checking if address is in correct range.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-12-26 21:35:52 -05:00
Álvaro Fernández Rojas
9622972af4 net: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
55e55fe4a6 net: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:00 +01:00
Tom Rini
d94604d558 Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC
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Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-10 17:19:59 -05:00
Philipp Tomsich
a740ee913e lib: merge CRC16-CCITT into u-boot/crc.h
This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure.  Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-08 20:18:32 -05:00
Priyanka Jain
4909b89ec7 armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
382c53f946 net: fm: add TFABOOT support
Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:42 -08:00
Tom Rini
2a055ea532 Minor sandbox enhancements / fixes
tpm improvements to clear up v1/v2 support
 buildman toolchain fixes
 New serial options to set/get config
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Merge tag 'dm-pull-5dec18' of git://git.denx.de/u-boot-dm

Minor sandbox enhancements  / fixes
tpm improvements to clear up v1/v2 support
buildman toolchain fixes
New serial options to set/get config
2018-12-05 20:32:25 -05:00
Tom Rini
9450ab2ba8 Merge branch 'master' of git://git.denx.de/u-boot-spi
- Various MTD fixes from Boris
- Zap various unused / legacy paths.
- pxa3xx NAND update from Miquel

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-05 15:06:24 -05:00
Simon Glass
e628bba785 sandbox: net: Correct name copy in eth_raw_bus_post_bind()
We cannot be sure that the interface name takes up the full length of the
space available to it. Use strcpy() instead of memcpy() in this case. This
corrects a valgrind warning.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-05 06:01:34 -07:00
Tom Rini
0a3d59e010 Xilinx changes for v2019.01
microblaze:
 - Use default functions for memory decoding
 - Showing model from DT
 
 zynq:
 - Fix spi flash DTs
 - Fix zynq_help_text with CONFIG_SYS_LONGHELP
 - Tune cse/mini configurations
 - Enabling cse/mini testing with current targets
 
 zynqmp:
 - Enable gzip SPL support
 - Fix chip detection logic
 - Tune mini configurations
 - DT fixes(spi-flash, models, clocks, etc)
 - Add support for OF_SEPARATE configurations
 - Enabling mini testing with current targets
 - Add mini mtest configuration
 - Some minor config setting
 
 nand:
 - arasan: Add subpage configuration
 
 net:
 - gem: Add 64bit DMA support
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Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.01

microblaze:
- Use default functions for memory decoding
- Showing model from DT

zynq:
- Fix spi flash DTs
- Fix zynq_help_text with CONFIG_SYS_LONGHELP
- Tune cse/mini configurations
- Enabling cse/mini testing with current targets

zynqmp:
- Enable gzip SPL support
- Fix chip detection logic
- Tune mini configurations
- DT fixes(spi-flash, models, clocks, etc)
- Add support for OF_SEPARATE configurations
- Enabling mini testing with current targets
- Add mini mtest configuration
- Some minor config setting

nand:
- arasan: Add subpage configuration

net:
- gem: Add 64bit DMA support
2018-12-03 19:30:54 -05:00
Siva Durga Prasad Paladugu
5f68f44c14 net: zynq_gem: Add check for 64-bit dma support by hardware
This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2018-12-03 16:22:06 +01:00
Vipul Kumar
9a7799f4f4 net: zynq_gem: Added 64-bit addressing support
This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2018-12-03 16:22:01 +01:00
Tom Rini
93e72ac472 Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
 - net: designware: add meson meson compatibles
 - Amlogic Meson cleanup for AXG SoC support
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Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
2018-11-29 15:16:58 -05:00
Jagan Teki
e2cae51472 spi: Remove unused spi_init
Remove spi_init definition which never used on
respective code since from many years.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27 21:06:53 +05:30
Neil Armstrong
71a38a8e8e net: designware: add meson meson axg compatible
Add the compatible string for the upcoming Amlogic AXG SoC family.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:10 +01:00
Neil Armstrong
ec353ad1b6 net: designware: add meson meson gxbb compatible
Add the compatible string for the Amlogic GXBB SoC family.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:10 +01:00
Icenowy Zheng
9b16ede4a4 sun8i_emac: add support for setting EMAC TX/RX delay
Some boards have the EMAC TX/RX lanes wired with a different length with
the clock lane, which can be workarounded by setting a TX/RX delay in
the EMAC.

This kind of delays are already defined in the newest device tree
binding of dwmac-sun8i, which has already entered linux-next.

Add support for setting these delays.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-23 11:01:09 +05:30
Grygorii Strashko
79d8127168 driver: net: ti: keystone_net: switch to use common mdio lib
Update TI Keystone 2 driver to re-use common mdio lib.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:01 -06:00
Grygorii Strashko
4f41cd9a95 driver: net: ti: cpsw: switch to use common mdio lib
Update TI CPSW driver to re-use common mdio lib

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:01 -06:00
Grygorii Strashko
6c4bbccc6e driver: net: ti: introduce common mdio support library
All existing TI SoCs network HW have similar MDIO implementation, so
introduce common mdio support library which can be reused by TI networking
drivers.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:42:00 -06:00
Grygorii Strashko
cbec53b434 driver: net: ti: cpsw: update to use SPDX identifier
Update to use SPDX license identifier.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:00 -06:00
Grygorii Strashko
af0cf2178b drivers: net: keystone_net: drop non dm code
Networking support for all TI K2 boards converted to use DM model and
CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop
unused non DM K2 networking code.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:00 -06:00
Grygorii Strashko
6a256a8ed4 configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig
Convert DRIVER_TI_KEYSTONE_NET to Kconfig.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:41:59 -06:00
Grygorii Strashko
ffad5fa0cd driver: net: consolidate ti's code in separate folder
Add drivers/net/ti/ folder and move all TI's code in this folder for better
maintenance.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:41:59 -06:00
Quentin Schulz
05bbd676a7 net: phy: mscc: add support for VSC8574 PHY
The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with
the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and
can set the blinking pattern of each of its 4 LEDs, supports SyncE as
well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8574 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:59 -06:00
Quentin Schulz
b5bca65e19 net: phy: mscc: factorize part of config function for VSC8584
Part of the config is common between the VSC8584 and the VSC8574, so to
prepare for the upcoming support of VSC8574, use the phy_device.priv
pointer that will keep the function that holds code that is PHY-specific
and that should be called during config function.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:58 -06:00
Quentin Schulz
04087fc494 net: phy: mscc: add support for VSC8584 PHY
The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with the
MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set
the blinking pattern of each of its 4 LEDs, supports hardware offloading
of MACsec and supports SyncE as well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8584 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

The revA of the VSC8584 PHY (which is not and will not be publicly
released) should NOT patch the firmware of the microcontroller or it'll
make things worse, the easiest way is just to not support it.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:58 -06:00
Cédric Le Goater
e6ddacc2d0 net: ftgmac100: Add support for the Aspeed SoC
The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:58 -06:00
Cédric Le Goater
1c0c61e927 net: ftgmac100: add clock support
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:57 -06:00
Cédric Le Goater
d0e0b84c66 net: ftgmac100: handle timeouts when transmitting
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:57 -06:00
Cédric Le Goater
e766849713 net: ftgmac100: convert the RX/TX descriptor arrays
Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:57 -06:00
Cédric Le Goater
538e75d3fc net: ftgmac100: add MDIO bus and phylib support
Implement the MDIO bus read/write functions using the readl_poll_timeout()
routine, initialize the bus and scan for the PHY. RGMII and RMII mode
are supported.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:57 -06:00
Cédric Le Goater
591ffd98b0 net: ftgmac100: use setbits_le32() in the reset method
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Cédric Le Goater
f95de0bd10 net: ftgmac100: convert to driver model
The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.

Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Cédric Le Goater
3bd796351f net: ftgmac100: use the aligned() macro
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Cédric Le Goater
f72b4a3dde net: ftgmac100: use the BIT() macro
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Stefan Roese
c895ef4650 net: Add MT7628 ethernet driver
This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs
(e.g. MT7628 and MT7688), including a minimum setup of the integrated
switch. This driver is loosly based on the driver version included in
this MediaTek github repository:

https://github.com/MediaTek-Labs/linkit-smart-uboot.git

Tested on the MT7688 LinkIt smart-gateway and on the
Gardena-smart-gateway.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Frank Wunderlich <frankwu@gmx.de>
Cc: Weijie Gao <hackpascal@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Bin Meng
db148f2a69 powerpc: t1040: Correct RCW EC2 settings
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2
settings.

- The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should
  be 0x04000000 (value of 1 in RCW bit [420:421])
- Value of 2/3 are reserved in RCW bit [420:421], hence there is no
  macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 13:19:43 -07:00
Patrick Delaunay
22929e1266 drivers: cosmetic: Convert SPDX license tags to Linux Kernel style
Complete in the drivers directory the work started with
commit 83d290c56f ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-28 09:26:39 -04:00
Anatolij Gustschin
58ec4d3342 net: fec_mxc: add support for i.MX8X
Add compatible property and enable the FEC ipg clock when probing
on i.MX8X. Add specific function for reading FEC clock rate via
clock driver when configuring MII speed register. Allow FEC_MXC
selection for i.MX8.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:38 -05:00
Baruch Siach
18593fa80b net: mvpp2: increase PHY reset pulse
The default Linux PHY reset delay is 10ms. This is also the requirement
for Marvell 88E151x PHYs, which are likely to be used with this Ethernet
MAC.

Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-10-24 14:45:38 -05:00
Baruch Siach
fa14027d5c net: mvpp2: fix polarity of PHY reset signal
The dm_gpio_set_value() call sets the logical level of the GPIO signal.
That is, it takes the GPIO_ACTIVE_{LOW,HIGH} property into account. The
driver needs to assert the reset, and then deassert it. Not the other
way around.

Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-10-24 14:45:38 -05:00
Martin Fuzzey
0126c641e8 net: dm: fec: Obtain the transceiver type from the DT
The DT property "phy-mode" already provides the transceiver type.
Use it so that we do not have to also set CONFIG_FEC_XCV_TYPE

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Martin Fuzzey
ad8c43cbca net: dm: fec: Support the phy-supply binding
Configure the phy regulator if defined by the "phy-supply" DT phandle.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Martin Fuzzey
331fcabe4f net: dm: fec: Fix phy-reset-duration clamping and defaults
The DT binding says:
- phy-reset-duration : Reset duration in milliseconds.  Should present
  only if property "phy-reset-gpios" is available.  Missing the property
  will have the duration be 1 millisecond.  Numbers greater than 1000 are
  invalid and 1 millisecond will be used instead.

However the current code:
 - clamps values greater than 1000ms to 1000ms rather than 1.
 - does not initialize the delay if the property does not exist
   (else clause mismatch)
 - returns an error if phy-reset-gpios is not defined

Fix all this and simplify by using dev_read_u32_default()

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Martin Fuzzey
9b8b918884 net: dm: fec: Fix time unit error in phy-reset-duration
The DT binding says that phy-reset-duration is in ms, but the driver
currently uses udelay().

Switch to mdelay() to fix this.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Jeremy Gebben
30a2c8cca8 net: phy: aquantia: autodetect if firmware needs to be loaded
If the phy reports a valid firmware version and doesn't indicate
a fault, skip loading the firmware.  This allows the same image
to be used on boards that have firmware storage and those that do not.

Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Jeremy Gebben
4506423ad2 net: phy: aquantia: add firmware loading support
Aquantia phys have firmware that can be loaded automatically
from storage directly attached to the phy or via MDIO commands.
Add support for loading firmware from either a file or a
raw location on an MMC device.

Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Jeremy Gebben
1c6501088e configs: migrate CONFIG_PHY_AQUANTIA to Kconfig
The aquantia driver requires both CONFIG_PHY_GIGE and CONFIG_PHYLIB_10G.

Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:36 -05:00
Michal Simek
3dc80934f4 net: gem: Do not setup any clock for Xilinx SoC Versal
Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Michal Simek
ec48b6c991 arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:21 +02:00
Tom Rini
15f22ac2ee ldpaa_eth.c: Fix warning when PHYLIB is not enabled
We need to #ifdef some variables to avoid warning about them being
unused.

Fixes: 1a048cd656 ("driver: net: fsl-mc: Add support of multiple phys for dpmac")
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-12 07:41:24 -04:00
Pankaj Bansal
1a048cd656 driver: net: fsl-mc: Add support of multiple phys for dpmac
Till now we have had cases where we had one phy device per dpmac.
Now, with the upcoming products (LX2160AQDS), we have cases, where there
are sometimes two phy devices for one dpmac. One phy for TX lanes and
one phy for RX lanes. to handle such cases, add the support for multiple
phys in ethernet driver. The ethernet link is up if all the phy devices
connected to one dpmac report link up. also the link capabilities are
limited by the weakest phy device.

i.e. say if there are two phys for one dpmac. one operates at 10G without
autoneg and other operate at 1G with autoneg. Then the ethernet interface
will operate at 1G without autoneg.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:45:28 -05:00
Pankaj Bansal
1ed19a1421 driver: net: fsl-mc: initialize dpmac irrespective of phy
The dpmac initalization should not depend on phy.
As the phy is not necessary to be present for dpmac to function.
Therefore, remove dpmac initialization dependency from phy.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:45:23 -05:00
Pankaj Bansal
a3cb5340f1 driver: net: fsl-mc: Modify the dpmac link detection method
when there is no phy present for a dpmac, a dummy phy device is created.
when we move to multiple phy method, we need to create as many dummy phy
devices.

Change this method so that we don't need to create dummy phy devices.
We always report linkup if no phy is present.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:45:01 -05:00
Pankaj Bansal
f259c43d89 driver: net: fsl-mc: fix error handing in init_phy
if an error occurs during init_phy, we should free the phydev structure
which has been allocated by phy_connect.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:43:18 -05:00
Pankaj Bansal
d75e81d9e0 driver: net: fsl-mc: remove unused strcture elements
The phydev structure is present in both ldpaa_eth_priv and
wriop_dpmac_info. the phydev in wriop_dpmac_info is not being used

As the phydev is created based on phy_addr and bus members of
wriop_dpmac_info, it is appropriate to keep phydev in wriop_dpmac_info.

Also phy_regs is not being used, therefore remove it

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:36:34 -05:00
Pankaj Bansal
afd6c6b470 driver: net: fsl-mc: modify the label name
The goto label name is misspelled it should be DPMAC not DPAMC

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:30:28 -05:00
Joe Hershberger
72ff004258 test: eth: Add a test for the target being pinged
The target will respond to pings while doing other network handling.
Make sure that the response happens and is correct.

This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:29:00 -05:00
Joe Hershberger
45988dae4c test: eth: Add a test for ARP requests
This tests that ARP requests made to this target's IP address are
responded-to by the target when it is doing other networking operations.

This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:29:00 -05:00
Joe Hershberger
9cbe5972c3 net: sandbox: Add a priv ptr for tests to use
Tests need to be able to pass their "unit test state" to the handlers
where asserts are evaluated. Add a function that allows the tests to set
this private data on the sandbox eth device.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:59 -05:00
Joe Hershberger
c67a420781 net: sandbox: Allow fake eth to handle more than 1 packet response
Use up to the max allocated receive buffers so as to be able to test
more complex situations.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:58 -05:00
Joe Hershberger
76a503439e net: sandbox: Share the priv structure with tests
If tests want to implement tx handlers, they will likely need access to
the details in the priv structure.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:57 -05:00
Joe Hershberger
c7eb733d60 net: sandbox: Make the fake eth driver response configurable
Make the send handler registerable so tests can check for different
things.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:57 -05:00
Joe Hershberger
e95bb16110 net: sandbox: Refactor sandbox send function
Make the behavior of the send function reusable.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:56 -05:00
Joe Hershberger
e4ab9a6508 net: sandbox: Move disabled flag into priv struct
Store the per-device data with the device.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:56 -05:00
Janine Hagemann
0f347a0096 net: phy: ti: Add binding for the CLK_OUT pin muxing
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:28:54 -05:00
Janine Hagemann
be71a74c59 net: phy: ti: Recover from "port mirroring" N/A MODE4
The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.

To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).

To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.

Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"

https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954

Based on commit ac6e058b75be ("net: phy: dp83867: Recover from "port mirroring"
N/A MODE4") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2018-10-10 12:28:54 -05:00
Janine Hagemann
fba725f410 net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver
This patch adds support for enabling or disabling the lane swapping
(called "port mirroring" in PHY's CFG4 register) feature of the DP83867
TI's PHY device.

One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).

Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping
support in the DP83867 TI's PHY driver") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:28:53 -05:00
Bin Meng
dda5251037 net.h: Include linux/if_ether.h to avoid duplication
There are plenty of existing drivers that have macros like ETH_ALEN
defined in their own source files. Now that we imported the kernel's
if_ether.h to U-Boot we can reduce some duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:28:52 -05:00
Bin Meng
339613eba5 net: pch_gbe: Make probe/remove static
These two routines are internal to pch_gbe driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-09 14:18:21 -05:00
Bin Meng
b06d76f9ae linux/compat.h: Add netdev_### log macros
Currently there are two ethernet drivers (mvneta.c and mvpp2.c) that
has netdev_### (eg: netdev_dbg) log macros defined in its own driver
file. This adds these log macros in a common place linux/compat.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-09 14:18:17 -05:00
Janine Hagemann
3d1bd5b590 net: gmac_rockchip: Add handling for RGMII_ID/RXID/TXID
Using PHY internal delays in combination with the phy-mode
rgmii-id/rxid/txid was not possible. Only rgmii was supported.

Now we can disable rockchip's gmac delay lines and also use
rgmii-id/rxid/txid.

Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add
handling for RGMII_ID/RXID/TXID") for mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Janine Hagemann
04acabd22c net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii
We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of
RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii()
to enable the RX delay.
The MASK was used in a wrong way.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Reviewed-by: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-04 21:15:46 +02:00
Tom Rini
27f622d568 Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
 Switch to driver model for SATA on LS1021A and LS1043A.
 Add support for LS1012AFRWY rev C board.
 Enable SMMU for LS1043A.
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Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.
2018-09-29 11:47:32 -04:00
Zhao Qiang
db947fa038 net: fman: Support both new and legacy FMan Compatibles
Recently the FMan Port and MAC compatibles were changed. This patch
aligns the FMan Port and MAC compatibles to the new FMan device tree
binding document. The FMan device tree binding document can be found
in the Linux kernel version 3.18.0, commit
297d35fd2a7d3fbd4e5c0f0c1c18213117ba11ba
./Documentation/devicetree/bindings/powerpc/fsl/fman.txt

This patch doesn't affect legacy compatibles support.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:01:27 -07:00
Pramod Kumar
7abf92327f ls1012a: remove debug info from u-boot log
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:58:42 -07:00
Prabhakar Kushwaha
87519a9ece driver: net: fsl-mc: Memset MC reserve ram memory before usage
Memory reserved for Management Complex needs to be cleaned before any
usage.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[York S: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:55:21 -07:00
Nipun Gupta
a78df40cba u-boot: fixup the iommu-map property of fsl-mc node
The iommu-map property in the fsl-mc node is updated by
valid stream-ids by u-boot. This patch is to fixup this
property for LS208x and LS1088.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:55:05 -07:00
Yinbo Zhu
c3ced8a6ed ppa/fm/qe: use block layer in ppa/fm/qe driver
At present the MMC subsystem maintains its own list of MMC devices.
This cannot work with driver model when CONFIG_BLK is enabled, use
blk_dread to replace previous mmc read interface, use
mmc_get_blk_desc to get the mmc device property.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:48:51 -07:00
Tom Rini
bbef20d479 Xilinx changes for v2018.11
- Handle BOARD_LATE_INIT via Kconfig
 
 SPL:
 - Enable GZIP for all partitions types(not only for kernel)
 
 ZynqMP:
 - Rearrange pmufw version handling
 - Support newer PMUFW with improved fpga load sequence
 
 Zynq:
 - Cleanup config file
 - Simplify zybo config by enabling option via Kconfig
 
 net:
 - Fix gems max-speed property reading
 - Enable support for fixed-link phys
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Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11

- Handle BOARD_LATE_INIT via Kconfig

SPL:
- Enable GZIP for all partitions types(not only for kernel)

ZynqMP:
- Rearrange pmufw version handling
- Support newer PMUFW with improved fpga load sequence

Zynq:
- Cleanup config file
- Simplify zybo config by enabling option via Kconfig

net:
- Fix gems max-speed property reading
- Enable support for fixed-link phys
2018-09-27 08:29:10 -04:00
Michal Simek
3888c8d197 net: zynq_gem: Add support for fixed-link phy
Based on dt-specs fixed-link doesn't require phy-handle to be used.
Fix driver to only read phy related setting when phy-handle is found.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-09-27 07:59:26 +02:00
Siva Durga Prasad Paladugu
f213dbbdec net: zynq_gem: Fix reading of max-speed property
max-speed property is part of phynode and it has to be
read using ofnode_read_u32_default(). This fixes the issue
of incorrect max-speed read from DT.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Sekhar Nori
e2597be5bc drivers: net: cpsw: add support to update phy address
On some boards using TI CPSW, it may be possible that
PHY address was not latched correctly, and the actual
address that the phy responds on is different from that
set in device-tree. For example, see this problem report
on beaglebone black:

https://groups.google.com/d/msg/beagleboard/9mctrG26Mc8/1FuI_i5KW10J

Add support to check for this condition and use the
detected phy address when its safe to do so.

Also, add a public API that exposes the phy address of
a given slave. This can be used to update device-tree that
is passed to Linux kernel.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-25 21:49:18 -04:00
Adam Ford
d7869b2183 Convert CONFIG_MII et al to Kconfig
This converts the following to Kconfig:
   CONFIG_MII
   CONFIG_DRIVER_TI_EMAC

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-17 13:03:54 -04:00
Tom Rini
719afeb0b3 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-08-17 07:24:34 -04:00
Marek Vasut
215a06565a net: designware: socfpga: Add Arria10 extras
Add wrapper around the designware MAC driver to handle the SoCFPGA
specific configuration bits. On Arria10, this is configuration of
syscon phy_intf.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-08-13 22:35:42 +02:00
Pankaj Bansal
c022ec039d fsl/mc: Limit the ethernet name to ETH_NAME_LEN
The ethernet name should be within the ETH_NAME_LEN, as this
is the buffer space allocated to ethernet name.

Otherwise, this causes buffer overflow.

Reported-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-08 08:23:49 -07:00
Siva Durga Prasad Paladugu
26026e695a net: zynq_gem: convert to use livetree
This patch updates the zynq gem driver to support livetree.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:23 -05:00
Grygorii Strashko
41080e180c drivers: net: zynq_gem: fix phy dt node setting
Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26 14:08:23 -05:00
Grygorii Strashko
d4bb981700 drivers: net: cpsw: fix phy dt node setting
Now CPSW driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:23 -05:00
Grygorii Strashko
aadbd97843 net: phy: xilinx: switch to use phy_get_ofnode()
Use PHY API phy_get_ofnode() helper to get PHY DT node.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:22 -05:00
Grygorii Strashko
b8d7ec782f net: phy: dp83867: switch to use phy_get_ofnode()
Use PHY API phy_get_ofnode() helper to get PHY DT node.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26 14:08:22 -05:00
Grygorii Strashko
eef0b8a930 net: phy: add ofnode node to struct phy_device
Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in
case of Ethernet PHYs which are linked to UCLASS_ETH device using
"phy-handle" DT property and when Ethernet PHY driver needs to read some
additional information from DT. In such cases following happens (in
general):

- network drivers
	priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
				   priv->interface);
	<-- phydev is connected to dev which is UCLASS_ETH device

	if (priv->phy_of_handle > 0)
		dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
	<-- phydev->dev->node is overwritten by phy-handle DT node

- PHY driver in .config() callback
	int node = dev_of_offset(dev);
	<-- PHY driver uses overwritten dev->node
        const void *fdt = gd->fdt_blob;

	 if (fdtdec_get_bool(fdt, node, "property"))
		...

As result, UCLASS_ETH device can't be used any more for DT accessing.

This patch adds additional ofnode node field to struct phy_device which can
be set explicitly by network drivers and used by PHY drivers, so
overwriting can be avoided. Also add helper function phy_get_ofnode()
which will check and return phy_device->node or dev_ofnode(phydev->dev) for
backward compatibility with existing drivers.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:22 -05:00
Joe Hershberger
05b60ac549 net: phy: Clean up includes of common.h
We want to be able to include some other system headers in phy.h but
that requires us to have included common.h in the top-level first.

Also, common.h includes config.h as the first thing it does, so don't
include it directly.

Series-to: u-boot
Series-cc: Grygorii Strashko <grygorii.strashko@ti.com>
Seried-cc: ti
Series-process-log: sort, uniq
Cover-letter:
Prepare for net: phy: prevent uclass_eth device "node" field overwriting
Prepare for [1] so that it doesn't break the build for a bunch of
boards. There are a number of reasons this series broke the build
but none of them depend on changes in the series, so fix up those
situations ahead of applying that series.

[1] https://patchwork.ozlabs.org/cover/940104/
END
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:22 -05:00
Grygorii Strashko
3ab75cf76e net: phy: dp83867: switch to use ofnode api
Switch to use more generic ofnode API instead of FDT API.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26 14:08:21 -05:00
Murali Karicheri
63d3192984 net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
supported (see note below Table 5 (4-Level Strap Pins)).

It further advises that if a board has this pin strapped in mode 1 and
mode 2, then bit[7] of Configuration Register 4 (address 0x0031) must
be cleared to 0. This is to ensure proper operation of PHY.

Since it is not possible to detect in software if RX_DV/RX_CTRL pin is
incorrectly strapped, add a device-tree property to advertise this and
allow corrective action in software.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26 14:08:21 -05:00
Chris Packham
fb73107698 net: mvgbe: convert to DM
Add driver model support to the mvgbe driver. As a temporary measure
both DM and non-DM uses are supported. Once all the users have been
converted the non-DM support can be dropped.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:21 -05:00
Chris Packham
e9bf75c9d3 net: mvgbe: prepare for conversion to driver model
Extract some function bodies to helper functions that can be reused in
the DM/non-DM implementations.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:20 -05:00
Joe Hershberger
f40a31e695 sandbox: eth-raw: Add a SIMPLE_BUS to enumerate host interfaces
Ask the OS for each of its interfaces and for each one, bind a U-Boot
device and then probe it. This will allocate the priv data structure
that is then populated.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:19 -05:00
Joe Hershberger
b96ced9cdb sandbox: eth-raw: Make random MAC addresses available to eth-raw
We don't necessarily know how many MAC addresses we'll need, so implement
a ROM read so we always have something valid.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
c9e2caff85 sandbox: eth-raw: Allow interface to be specified by index
With systemd stable interface names, eth0 will almost never exist.
Instead of using that name in the sandbox.dts, use an index.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
ac13270b49 sandbox: eth-raw: Add a function to ask the host about localhost
Instead of doing a simple string compare against "lo", look for the flag
that indicates a localhost interface.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
8c7988b6db net: sandbox-raw: Convert raw eth driver to livetree
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
b32dd183c2 net: sandbox: Convert sandbox mock eth driver to livetree
Use the dev_ functions to access DT properties.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
c25f40627f net: Correct comment in Kconfig
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Michael Trimarchi
efd0b79106 eth: dm: fec: Add gpio phy reset binding
Add the missing gpio phy reset binding to the gpio and
reset time configuration

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-23 10:28:01 +02:00
Lothar Felten
e46d73fa96 net: sun8i-emac: support R40 GMAC
Add support for the GMAC found in the Allwinner R40/V40 SoC.

The R40 GMAC interface is not controlled by the syscon register but
has a separate configuration register in the CCU.
The clock gate and reset bits are in a different register compared
to the other SoCs supported by this driver.
The driver uses the -gmac suffix for the R40 because the R40 also
has a different 100 MBit MAC (EMAC).

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16 12:27:27 +05:30
Lothar Felten
c6a21d6615 net: sun8i-emac: set mux and clock by driver data
Use driver data->variant information to select device specific
pin mux and phy clock settings.

Suggested by Jagan Teki

Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16 12:27:27 +05:30
Lothar Felten
2f15743633 net: sun8i-emac: fix printing NULL character
If the variant is not set and therefore NULL, do not attempt to print
the variant.

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16 12:27:27 +05:30
Ley Foon Tan
495c70f9df net: designware: Add reset ctrl to driver
Add code to reset all reset signals as in Ethernet DT node. A reset
property is an optional feature, so only print out a warning and do not
fail if a reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-09 15:28:28 -04:00
Rabeeh Khoury
318b5d76b6 net: mvneta: zero Tx descriptors on init
Make the initialization sequence consistent with the Linux kernel
driver.

Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-07-02 14:14:20 -05:00
Rabeeh Khoury
0f8888b763 net: mvneta: dcache flush TX descriptors at init
This fixes sporadic timeout on initial packet Tx (usually ARP), with an
error message like:

  timeout: packet not sent

Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-07-02 14:14:20 -05:00
Michal Simek
d1b226b7d4 net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()
phyread can timeout and val will contain random value. Initialize it to
zero not to report random value in case of error.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-02 14:14:19 -05:00
Marek Vasut
159b329226 net: sh_eth: Support reset GPIO both in mac and phy node
The recent DTs have the PHY reset GPIO in the PHY node rather than
the ethernet MAC node, support extracting the PHY reset GPIO info
from both the PHY node and ethernet MAC node.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19 06:15:55 +02:00
Marek Vasut
701db6e9c6 net: ravb: Support reset GPIO both in mac and phy node
The recent DTs have the PHY reset GPIO in the PHY node rather than
the ethernet MAC node, support extracting the PHY reset GPIO info
from both the PHY node and ethernet MAC node.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19 06:15:55 +02:00
Marek Vasut
536fb5d47c net: ravb: Filter out supported PHY features
The RAVB only supports 100Full and 1000Full operation, it does not support
10Full or any Half-duplex modes. The PHY could still advertise those features
though, so filter out the PHY features accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19 06:15:55 +02:00
Marek Vasut
c4a8d9ca04 net: ravb: Do not shut down clock in start callback
Do not stop the clock in the start callback in case of failure, keep
them running to also keep the PHY running. The failure could be ie.
PHY failing to negotiate link and if the clock get shut down, another
attempt at bringing the link up would fail. The clock right now are
started in probe function and stopped in remove function, which is
the correct behavior.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19 06:15:55 +02:00
Michal Simek
5b2c9a6ce3 net: gem: Check return value from memalign/malloc
Functions can return NULL in case of error that's why checking return
value is needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:59:04 -05:00
Michal Simek
7674b64d78 net: zynq_gem: Initialize phyreg variable
In case of phyread()/phy_setup_op() timeout code is working with
uninitialized phyreg variable. Initialize this variable to make sure
that code it not working with random value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:18 -05:00
Michal Simek
b33d4a5fc7 net: zynq_gem: Fix return type for phy...()
wait_for_bit_le32 returns negative value on failure. Fix phy...() to
handle these failures properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Chris Packham
5194ed7edc net: mvgbe: extract common code for SMI wait
Combine repeated code from smi_reg_read/smi_reg_write into a common
function smi_wait_ready.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Quentin Schulz
c61221948c net: designware: set the PS bit when resetting DMA bus in MII configuration
On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block,
the DMA reset never succeeds when a MII PHY is used (no problem with a
GMII PHY). The designware_eth_init() function sets the
DMAMAC_SRST bit in the DMA_BUS_MODE register, and then
polls until this bit clears. When a MII PHY is used, with the current
driver, this bit never clears and the driver therefore doesn't work.

The reason is that the PS bit of the GMAC_CONTROL register should be
correctly configured for the DMA reset to work. When the PS bit is 0,
it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells
the MAC we have a MII PHY.

Doing a DMA reset clears all registers, so the PS bit is cleared as
well. This makes the DMA reset work fine with a GMII PHY. However,
with MII PHY, the PS bit should be set.

We have identified this issue thanks to two SPEAr600 platform:

- One equipped with a GMII PHY, with which the existing driver was
working fine.

- One equipped with a MII PHY, where the current driver fails because
the DMA reset times out.

Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Chris Packham
3cb51dad0d net: phy: mv88e61xx: Force CPU port link up
When connecting to from a CPU direct to a 88e6097 typically RGMII is
used. In order for traffic to actually pass we need to force the link up
so the CPU MAC on the other end will see the link.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Jon Nettleton
199b27bb70 mvebu: neta: align DMA buffers
This makes sure the DMA buffers are properly aligned for the
hardware.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Kunihiko Hayashi
a8927795ef net: add Socionext AVE ethernet driver support
Add driver for Socionext AVE ethernet controller that includes MAC and
MDIO bus supporting RGMII/RMII modes.
The driver behaves the ethernet driver model (DM_ETH) with devicetree.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Radu Bulie
98017a1fb5 drivers/net/vsc9953: Initialize action RAM in VCAP complex
VCAP tables must be initialized even if no advanced classification
is used. If no initialization is performed, then ECC error will
be observed by the user when the first packet enters the l2switch.
The error is marked in MPIC_EISR0 -bit 29 which means - Internal RAM
multi-bit ECC error.
This patch fixes the aforementioned ECC error by performing the
initialization of VCAP tables.

Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:16 -05:00
Alex Kiernan
286bea2e85 net: cpsw: ti: Reap completed packets before stopping interface
If you send a final packet just before stopping the interface (e.g. a final
ACK as part of the UDP fastboot protocol), then that packet isn't reliably
delivered onto the wire.

Reap packets prior to stopping the interface to ensure any which are
in-flight make it out. Also remove buffer and len from the call to
cpdma_process() as we weren't using them on their return.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:16 -05:00
Vicentiu Galanopulo
552e7c57d0 net/phy/cortina: Add support for CS4223 PHY
Add support for Cortina CS4223 10G PHY
  - As per the CS4223 specs, an EEPROM module is
    connected to the PHY. At startup the PHY reads
    the firmware line and tries to load the firmware
    into the internal memory.
  - This driver reads the EEPROM status
    and checks if firmware has been loaded

Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:15 -05:00
Joe Hershberger
6e35686d89 net: sunxi: Correct MAC address register order
Put the enetaddr data in the same order as it was before the change in
commit ace1520cb5 ("net: sunxi-emac: Write HW address via function")

Reported-by: Udo Maslo <u.maslo@web.de>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:15 -05:00
Mario Six
5e9d9abe08 tsec: Fix reading phy registers from DT
Bus translations should be applied when reading the address of the sgmii
phy registers from the DT. Use ofnode_get_addr_index instead of the
plain ofnode_read_u32_default to fix this.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:15 -05:00
Vinitha V Pillai
2d91b53331 LS1012AFRWY: Add Secure Boot support
Added the following:
1. defconfig for LS1012AFRWY Secure boot
2. PfE Validation support

Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-06-11 12:34:45 -07:00
Tom Rini
040b2583c3 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-06-02 16:58:27 -04:00
Marek Vasut
34f1dba983 net: ravb: Add R8A77990 E3 compatible
Add new compatible to the Ethernet AVB driver for R8A77990 E3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:02 +02:00
Rick Chen
28b52a6fb7 net: ftmac100: Fix compiler warning
Fix warnings as below when compile in 64-bit.

warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-29 14:45:03 +08:00
Tuomas Tynkkynen
ed9072c797 net: Drop CONFIG_TSI108_ETH
Last user of this driver went away in June 2015 in commit
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-05-23 17:30:03 -04:00
Chris Packham
f6e62ee04c net: MVGBE don't automatically select PHYLIB
When Kconfig support was added for MVGBE it included automatically
selected PHYLIB support. But MVGBE does not need PHYLIB it will build
fine without it. Commit ed52ea507f ("net: add Kconfig for MVGBE")
should have been a no-op in terms of build size but because of the
selecting PHYLIB the openrd configs increased in size.

Remove the automatic selection of PHYLIB, boards that need it will have
already enabled it in their config header file.

Fixes: commit ed52ea507f ("net: add Kconfig for MVGBE")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:38:31 +02:00
Chris Packham
ed52ea507f net: add Kconfig for MVGBE
Add Kconfig for MVGBE and update boards to select this.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-05-14 21:28:38 -04:00
Chris Packham
edcf7eacbd net: mvgbe: remove CONFIG_DOVE
Nothing defines CONFIG_DOVE so remove the code that uses it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-14 21:28:38 -04:00
Marek Behún
cf2cf8510a net: mvneta: Fix fault when wrong device tree
The driver does not check id phy_connect failed (for example on wrong
property name in device tree). In such a case a fault occurs and the
CPU is restarted.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00
Tom Rini
c590e62d3b Merge git://git.denx.de/u-boot-fsl-qoriq 2018-05-11 07:09:21 -04:00
Tom Rini
f739fcd831 SPDX: Convert a few files that were missed before
As part of the main conversion a few files were missed.  These files had
additional whitespace after the '*' and before the SPDX tag and my
previous regex was too strict.  This time I did a grep for all SPDX tags
and then filtered out anything that matched the correct styles.

Fixes: 83d290c56f ("SPDX: Convert all of our single license tags to Linux Kernel style")
Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-10 20:38:35 -04:00
Yogesh Gaur
a6f2a6eafe driver: net: fsl-mc: updated copyright info
Updated copyright info for the issues reported after running
check-legal test.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
b25f8e2112 Merge git://git.denx.de/u-boot-imx 2018-04-30 07:14:05 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Adam Ford
f1b1f77060 Convert CONFIG_SPI to Kconfig
This converts the following to Kconfig:
   CONFIG_SPI

This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the MPC8xx SPI driver.  For now, just update
the CONFIG tests.  This also involves reworking the default for
CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
reasonable default, as it does not cause any compile failures.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:11 -04:00
Lukasz Majewski
948239ea16 dts: dm: fec: imx53: Provide proper compatible string for imx53 fec driver
After this change the DM FEC ETH driver can be also reused on some imx53
devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-04-26 09:28:49 +02:00
Lukasz Majewski
178d4f0099 eth: dm: fec: Change FEC PHY mask setting from CONFIG_PHYLIB to CONFIG_FEC_MXC_PHYADDR
Without this commit we do have an explicit dependency on CONFIG_PHYLIB
when one wants to set PHY ADDR on a iMX board (FEC + driver model).

This shall be changed to CONFIG_FEC_MXC_PHYADDR, as only when we do have
it set, we shall mask out other devices.

As a side effect, when CONFIG_FEC_MXC_PHYADDR is not set, we scan PHY bus
for connected PHY devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-04-26 09:27:22 +02:00
Joe Hershberger
16879cd25a net: phy: Don't limit phy addresses by default
Some boards expect to find more than one phy while other boards are old
and need to be limited to a specific phy address. Only limit the phy
address for boards that opt in.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-13 15:56:47 -05:00
Marek Vasut
b107fd5bab net: sh_eth: Add remaining Gen2 DT compatible
Add compatible strings for R8A7790, R8A7793 and R8A7794, since the
contemporary DTs use those don't have a generic match value.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 15:47:52 -05:00
Siva Durga Prasad Paladugu
69065e8ff4 net: zynq_gem: Use max-speed property from dt
Add support to use max-speed property from dt for
determining the supported speed. Use 1000Mbps as
default.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 15:47:48 -05:00
Ye Li
2087eac257 net: fec: Fix issue in DM probe timeout
Since the probe function has changed to reset FEC controller prior than
setup PHY. If reset FEC controller timeout, the priv->phydev is not
initialized, so can't free it.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 15:47:39 -05:00
Peng Fan
979e0fc862 net: fex_mxc: add i.MX6UL/SX/SL compatible
Add i.MX6UL/SX/SL compatible.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 15:47:39 -05:00
Peng Fan
fbada4855d net: fec: sharing MDIO for two enet controllers
On i.MX6SX, 6UL and 7D, there are two enet controllers each has a
MDIO port. But Some boards share one MDIO port for the two enets. So
introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate
the MDIO port for sharing.
In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter
the CONFIG_FEC_MXC_MDIO_BASE.

To i.MX28, adapt to use the new config

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-13 15:47:38 -05:00
Peng Fan
8b20386356 net: fec: set dev->seq to priv->dev_id
To platforms has two enet interface, using dev->seq could
avoid conflict.

i.MX6UL/ULL evk board net get the wrong MAC address from fuse,
eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the
priv->dev_id to device->seq as the real net interface alias id then
.fec_get_hwaddr() read the related MAC address from fuse.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 15:47:38 -05:00
Peng Fan
1bcabd7921 net: fec_mxc: simplify fec_get_miibus
No need to provide two prototype for this function.
Use ulong for the first parameter, then this function
could be shared for DM/non DM case.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 15:47:37 -05:00
Ye Li
07763ac928 net: fec_mxc: Fix DM driver issue in recv
When using ethernet DM driver, the recv interface has a
change with non-DM interface, that driver needs to set
the packet pointer and provide it to upper layer to process.

In fec driver, the fecmxc_recv functions does not handle the
packet pointer parameter. This may cause crash in upper layer
processing because the packet pointer is not set.

This patch allocates a buffer for the packet pointer and free it
through free_pkt interface.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 15:47:37 -05:00
Matt Pelland
0a85f024c5 net: mvneta: support setting hardware address
mvneta already supports setting the MAC address but this was only done
internally when some other part of U-Boot tries to actually use the
interface. This commit exposes this functionality to the ethernet core
code so that the MAC addresses of all interfaces are configured
correctly even if they are not used before loading Linux.

Signed-off-by: Matt Pelland <mpelland@starry.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 15:47:31 -05:00
Tom Rini
2600df4f8e Xilinx changes for v2018.05-rc2
- Various DT changes and sync with mainline kernel
 - Various defconfig updates
 - Add SPL init for zcu102 revA
 - Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
   and zc1751-dc3
 - Net fixes - xlnx,phy-type
 - 64bit axi ethernet support
 - arasan: Fix nand write issue
 - fpga fixes
 - Maintainer file updates
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Merge tag 'xilinx-for-v2018.05-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05-rc2

- Various DT changes and sync with mainline kernel
- Various defconfig updates
- Add SPL init for zcu102 revA
- Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
  and zc1751-dc3
- Net fixes - xlnx,phy-type
- 64bit axi ethernet support
- arasan: Fix nand write issue
- fpga fixes
- Maintainer file updates
2018-04-09 11:06:21 -04:00
Siva Durga Prasad Paladugu
c643c491b9 net: phy: xilinx_phy: Read phytype using property xlnx,phy-type
This patch reads phytype from property "xlnx,phy-type" instead
od simply looking for "phy-type". This is to be inline with
Linux and also fixes the issue of detecting it wrongly in
u-boot.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-09 12:14:51 +02:00
Vipul Kumar
047f3bf828 axi: ethernet: Added support for 64 bit addressing for axi-ethernet
This patch uses writeq() function to enable greater than 32 bit
addressing of axi-ethernet for the ZynqMP devices.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-09 12:14:50 +02:00
Alex Kiernan
9925f1dbc3 net: Move enetaddr env access code to env config instead of net config
In order that we can use eth_env_* even when CONFIG_NET isn't set, move
these functions to environment code from net code.

This fixes failures such as:

  board/ti/am335x/built-in.o: In function `board_late_init':
  board/ti/am335x/board.c:752: undefined reference to `eth_env_set_enetaddr'
  u-boot/board/ti/am335x/board.c:766: undefined reference to `eth_env_set_enetaddr'

which caters for use cases such as:

commit f411b5cca4 ("board: am335x: Always set eth/eth1addr environment
variable")

when Ethernet is required in Linux, but not U-Boot.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-08 23:00:58 -04:00
Alex Kiernan
f02b8d1761 Migrate CONFIG_DRIVER_TI_CPSW to Kconfig
This converts CONFIG_DRIVER_TI_CPSW to Kconfig

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-08 23:00:58 -04:00
Mario Six
171510522e treewide: Migrate CONFIG_TSEC_ENET to Kconfig
Migrate the CONFIG_TSEC_ENET option to Kconfig.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-04-08 15:12:53 -04:00
Christophe Leroy
18f8d4c60d powercp: mpc8xx: move commproc.h
include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and
move it into arch/powerpc/include/asm

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06 16:30:37 -04:00
Christophe Leroy
ee1e600c13 powerpc: mpc8xx: Change CONFIG_8xx to CONFIG_MPC8xx
CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06 16:30:37 -04:00
Tom Rini
e294ba0678 Merge git://git.denx.de/u-boot-sunxi
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-04 14:10:39 -04:00
Andre Przywara
ecd0cec04c net: sun8i-emac: remove support for old binding
The original DT binding used by U-Boot's sun8i-emac driver was not really
agreed upon, and deviated from the "official" binding now used by the
kernel. Since now all U-Boot users have been converted to the new
binding, we can remove support for the old DT nodes from the driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-04 11:31:35 +05:30
Andre Przywara
12afd95711 net: sun8i-emac: add support for new EMAC DT binding
The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an
upstream Linux driver in v4.15.
This one uses a slightly different binding from the original one used
by the U-Boot driver.
The differences to the old binding are:
- The "syscon" address is held in a separate node, referenced via a
  phandle in the "syscon" property.
- The reference to the PHY is held in a property called "phy-handle",
  not "phy".
- The PHY register is at offset 0x30 in the syscon device, not at 0.
- The internal PHY is activated when the node, which phy-handle points
  to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node.

Teach the U-Boot driver how to find its resources in a "new-style" DT,
so that we can use a Linux kernel compatible DT for U-Boot as well.
This keeps support for the old binding for now, to allow a smooth
transition.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-04 11:31:35 +05:30
Andre Przywara
c034117302 net: sun8i-emac: support new pinctrl DT bindings
The Linux kernel driver for the Allwinner pin controller gained support
for generic properties, which are now also used in the DTs.
The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from
the DT, but so far only supported the old binding.
Update the parsing routine to cope with both the old and new bindings,
so that the newer DTs can be used with U-Boot and its Ethernet driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-04 11:31:35 +05:30
Siva Durga Prasad Paladugu
d77081cf50 net: zynq_gem: Dont run any phy detection logic for GMII case
This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as phy detection logic is different for some phys
like xilinx phy which can be connected over SGMII and GMII
interface.
This fixes the issue of ethernet failures when xilinx phy is
connected over GMII interface.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-23 09:34:42 +01:00
Tuomas Tynkkynen
d04791dfa5 net: Drop CONFIG_ENC28J60
Last user of this driver went away in October 2014 in
commit d58a9451e7 ("ppc/arm: zap EMK boards").

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:32 -05:00
Heinrich Schuchardt
6cdf072d9e net: macb: remove superfluous logical constraint
In

	if (a > =0) {...}
	else (a < 0) {...}

the second logical constraint is superfluous.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:32 -05:00
Heinrich Schuchardt
4b23d3c864 drivers: net: cpsw: remove superfluous assignment.
In

	int ret = A;
	ret = B;

the first assignment has not effect.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:32 -05:00
Priyanka Jain
b321c44ac9 net/phy/cortina: Add No firmware upload option
Current Cortina phy driver assumes that firmware upload
is required during initialization and is dependent
on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR
for compilation.

But Cortina phy has provision to store phy firmware in
attached dedicated EEPROM. And boards designed with such
EEPROM does not require firmware upload.

Add CORTINA_NO_FW_UPLOAD option in cortina.c to support
such boards.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:31 -05:00
Priyanka Jain
af5484acb0 net/phy/cortina.c: Update get_phy_id implementation
Update get_phy_id() implementation in cortina.c to check
for Cortina_phy by comparing device phy_id with cortina phy_id
instead of relying on presence of CORTINA macros.

This will allow get_phy_id to work with non-cortina phy devices
which might have same phy address as Cortina device but on
different  bus.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:31 -05:00
Calvin Johnson
a802d1e268 configs: ls1012a: add pfe configuration for LS1012A
Add configurations for PFE.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:31 -05:00
Calvin Johnson
6281a769b3 drivers: net: pfe_eth: provide pfe commands
pfe_command provides command line support for several features that
support pfe, like starting or stopping the pfe, checking the health
of the processor engines and checking status of different units inside
pfe.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:28 -05:00
Calvin Johnson
a4a4043749 drivers: net: pfe_eth: LS1012A PFE driver introduction
This patch adds PFE driver to U-Boot

Following are the main driver files:-
pfe_hw.c: provides low level helper functions to initialize PFE
internal processor engines and other hardware blocks
pfe_driver.c: provides initialization functions
and packet send and receive functions
pfe_eth.c: provides high level gemac initialization functions
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
pfe_mdio.c: provides functions to initialize phy and mdio.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:28 -05:00
Calvin Johnson
365108ef52 drivers: net: phy: Fix aquantia compilation with DM
With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.

drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
          phydev->dev->name);
		     ^~

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:28 -05:00
Heinrich Schuchardt
b24b1e4b1d net: mvpp2x: add check after calloc
After allocating plat the pointer is checked.
Afterwards name is allocated and not checked.

Add the missing check to avoid a possible NULL dereference.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:28 -05:00
kevans@FreeBSD.org
66526e7038 net: phy: Add PHY_RTL8211E_PINE64_GIGABIT_FIX for realtek phys
Setting PHY_RTL8211E_PINE64_GIGABIT_FIX forces internal rx/tx delays off
on the PHY, as well as flipping some magical undocumented bits. The
magic number comes from the Pine64 engineering team, presumably as a
proxy from Realtek. This configuration fixes the throughput on some
Pine64 models. Packet loss of up to 60-70% has been observed without
this.

Signed-off-by: Kyle Evans <kevans@FreeBSD.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:27 -05:00
Stefan Mavrodiev
b30c419040 Move CONFIG_PHY_ADDR to Kconfig
CONFIG_PHY_ADDR is used for old-style configuration. This makes
impossible changing the PHY address, if multiple boards share a same
config header file (for example include/configs/sunxi-common.h).

Moving this to Kconfig helps overcoming this issue. It's defined
as entry inside PHYLIB section.

After the implemention, moveconfig was run. The issues are:
	- edb9315a	- CONFIG_PHYLIB is not enabled. Entry is
			  deleted.

	- ds414		- CONFIG_PHYLIB is in incompatible format:
			  { 0x1, 0x0 }. This entry is also deleted.

	- devkit3250	- The PHY_ADDR is in hex format (0x1F).
			  Manually CONFIG_PHY_ADDR=31 is added in
			  the defconfig.

After the changes the suspicious defconfigs passes building.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 22:36:33 +05:30
Samuel Holland
2d53018a0e net: sun8i_emac: Fix PHY initialization
The previous code tried to update the PHY parameters without waiting for
autonegotiation to complete. This caused wrong values to be written to
the EMAC in sun8i_adjust_link(). As a result, any commands that called
eth_start() before autonegotiation completed would find the network
nonfunctional. Fix this by using the correct function to start up the
PHY.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 21:16:51 +05:30
Tom Rini
81f077f40f Merge git://git.denx.de/u-boot-sh 2018-03-05 20:24:17 -05:00
Masahiro Yamada
b08c8c4870 libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -> include/linux/libfdt.h
  include/libfdt_env.h     -> include/linux/libfdt_env.h

and replaces include directives:
  #include <libfdt.h>      -> #include <linux/libfdt.h>
  #include <libfdt_env.h>  -> #include <linux/libfdt_env.h>

Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-05 10:16:28 -05:00
Marek Vasut
7a7081e6f3 net: ravb: Add R8A77965 M3N entries
Add entries for the R8A77965 M3N SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-03-05 10:59:37 +01:00
Arno Steffens
a0fd381fc6 net: phy: smsc: Add SMSC LAN8741 support
Signed-off-by: Arno Steffens <star@gmx.li>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-02-26 15:51:37 -06:00
Bernhard Messerklinger
8f5672ea9d net: e1000: Fix e1000_igb semaphore handling
Fix commit f1bcad22dd ("net: e1000: add support for writing to
EEPROM").

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-02-26 15:51:36 -06:00
Eugeniy Paltsev
1693a577be NET: designware: fix clock enable
After commit ba1f966725 ("net: designware: add clock support")
we got NET broken on axs101 and axs103 platforms.

Some clock don't support gating so their clock drivers don't
implement .enable/.disable callbacks. In such case clk_enable
returns -ENOSYS.
Also some clock drivers implement .enable/.disable callbacks not for all
clock IDs and return -ENOSYS (or -ENOTSUPP) for others.

If we have such clock in 'clocks' list of designware ethernet controller
node we fail to probe designware ethernet.

Fix it.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-02-26 15:49:26 -06:00
Mario Six
8d6312032e phy: Fix style violations
Fix some style violations in the generic PHY management code.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-02-26 15:48:55 -06:00
Mario Six
431be621c6 net: phy: marvell 88e151x: Fix handling of bare RGMII interface type
Commit 68e6ecadc5 ("net: phy: marvell 88e151x: Fix handling of RGMII
interface types") fixed the initialization of 88e151x phys, but made it
so that interfaces of type PHY_INTERFACE_MODE_RGMII had both RX and TX
delay bits cleared. The default (like in m88e1111s_config) is to have
both bits set.

Hence, this patch changes the behavior in the PHY_INTERFACE_MODE_RGMII
case so that both bits are set.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-02-26 15:47:07 -06:00
Mario Six
76f11d3adf net: phy: marvell: Fix style violations
Fix some style violations (mostly wrong indentions) in the Marvell PHY
driver.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-02-26 15:46:09 -06:00
Mario Six
1313aaf031 net: tsec: Make live-tree compatible
Make the tsec ethernet driver compatible with a live device tree.

Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-02-26 15:45:56 -06:00
Mario Six
5775f00e12 net: tsec: Fix memory leak in error path
tsec_initialize allocates a private driver structure using malloc.
Should the memory allocation of this private structure fail, the
function execution is aborted with a return 0, but the previously
allocated device structure is never freed, hence leaked.

Free the device structure in the error case.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-02-26 15:28:43 -06:00
Mario Six
d38de3380d net: tsec: Fix style violations
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-02-26 15:28:39 -06:00
Michal Simek
744247de29 net: Remove Xilinx ll_temac driver
ll_temac driver was used by Xilinx Microblaze big endian and
Xilinx ppc405/ppc440 SoCs.

ppc support was removed by: "powerpc: remove 4xx support"
(sha1: 98f705c9ce)
and Microblaze BE is not tested for a long time that's why this driver
can be removed because none is going to updated it to DM anyway.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-02-23 10:40:51 -05:00
Marek Vasut
5abcbd7847 net: sh_eth: Fix DT base address fetching
Drop the whole map/unmap_physmem stuff and just use the address
already obtained from DT in ofdata_to_platdata(), instead of
repeating that, wrongly, in probe.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-18 11:20:18 +01:00
Marek Vasut
5262767ded net: sh_eth: Fix checkpatch warning
Fix minor checkpatch warning about udelay(3000) being too long
and should be replaced by mdelay(3).

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-18 11:20:18 +01:00
Marek Vasut
60279b5757 net: sh_eth: Return directly from sh_eth_recv_start
Drop the len variable, it's useless.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-18 11:20:18 +01:00
Marek Vasut
3c5a7b7547 net: sh_eth: Zap port variable
Inline this variable which is quite useless.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-18 11:20:17 +01:00
Marek Vasut
d64c789414 net: ravb: Initialize PHY in probe() once
Reset and initialize the PHY once in the probe() function rather than
doing it over and over again is start() function. This requires us to
keep the clock enabled while the driver is in use. This significantly
reduces the time between transfers as the PHY doesn't have to restart
autonegotiation between transfers, which takes forever.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-16 16:43:09 +01:00
Michal Simek
c946b0e9fd Kconfig: net: phylib: Phylib should depends on NET
There is no value to enable phylib without networking support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-02-08 12:48:10 -05:00
Hannu Lounento
8d9bde0dbb net: e1000: implement eth_write_hwaddr
Implement programming MAC address to the hardware, i.e. external flash
seen as EEPROM.

MAC address is only written if it differs from what is already stored in
flash or if reading the current MAC address fails.

Signed-off-by: Hannu Lounento <hannu.lounento@ge.com>
CC: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
2018-02-04 12:00:58 +01:00
Hannu Lounento
e0a75fed9e net: e1000: split e1000_read_mac_addr
Split the implementation of e1000_read_mac_addr into eeprom and register
versions called by e1000_read_mac_addr.

This allows for calling e1000_read_mac_addr when MAC address is needed
with no constraints where it is read from, and for calling the register
and, especially, the eeprom version directly in order to specify where
to read the address from.

Signed-off-by: Hannu Lounento <hannu.lounento@ge.com>
CC: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
2018-02-04 12:00:58 +01:00
Hannu Lounento
f1bcad22dd net: e1000: add support for writing to EEPROM
Port functions for writing to EEPROM, updating the checksum and
committing data to flash from the Linux kernel igb driver.

Functions were ported from Linux 4.8-rc2 (694d0d0bb20).

Signed-off-by: Hannu Lounento <hannu.lounento@ge.com>
CC: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
2018-02-04 12:00:58 +01:00
Ye Li
f24e482ae0 net: fec: fix build warnings for 64bits support
When building for 64bits system, we get some warnings about type
cast between pointer and integer. This patch eliminates the warnings
by using ulong/long type which is 32bits on 32bits system or 64bits on
64bits system.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-04 12:00:58 +01:00
Peng Fan
238a53c710 net: fec: do not access reserved register for i.MX8M
The MIB RAM and FIFO receive start register does not exist on
i.MX8M. Accessing these register will cause system hang.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-02-04 12:00:58 +01:00
Tom Rini
48f58a5973 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-01-31 18:44:31 -05:00
Yogesh Gaur
f9747a5a5d driver: fsl-mc: Perform fsl-mc fdt fixup for lazyapply dpl
For for case of lazyapply method, API fdt_fixup_board_enet() gets
invoked before DPL being deployed. This leads to an issue that
fsl-mc fdt fixup status marked as fail and dprc driver didn't get
registered in linux boot.

Fixes this issue by calling fdt_fixup_board_enet() for case when
DPL is deployed successfully in lazyapply method.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-30 09:13:32 -08:00
Tom Rini
c5e6e9b3d6 mvpp2: Fix warning over 32bit vs 64bit targets
When we have a driver that is used on both 32bit and 64bit targets and
we are talking about address space we cannot use u64 nor u32 and instead
need to use phys_addr_t.

Fixes: 377883f16d ("net: mvpp2x: fix phy connected to wrong mdio issue")
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-29 12:48:34 -05:00
David Wu
d12d7c09eb net: gmac_rockchip: Add support for the RK3228 GMAC
The GMAC in the RK3228 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3368-specific logic necessary to reuse this driver.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28 17:12:38 +01:00
David Wu
b3d2a6df30 net: gmac_rockchip: Add rk3328 gmac support
The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3328-specific logic necessary to reuse this driver.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28 17:12:37 +01:00
David Wu
caf746172b net: gmac_rockchip: Add support for the RV1108 GMAC
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28 17:12:37 +01:00
Tom Rini
9c486e7cb0 Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh 2018-01-27 18:25:00 -05:00
Marek Vasut
319202640a net: sh_eth: Add DM and DT support
Add DM capable code into the SH ethernet driver and support probing
both from DT and pdata. The legacy non-DM, non-DT support is retained
as there are still systems in the tree which are not DM or DT capable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-01-27 20:38:53 +01:00
Marek Vasut
a220784b14 net: sh_eth: Clump legacy functions together
Move the legacy functions around, so that they can be wrapped in a
massive ifdef CONFIG_DM_ETH once DM support is added. No functional
change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-01-27 20:38:53 +01:00
Marek Vasut
013af64f8f net: sh_eth: Split sh_eth_init
Split sh_eth_init() function into smaller chunks, which can
be called from both DM and non-DM code while handling the
specifics of both configurations.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-01-27 20:38:53 +01:00
Marek Vasut
68ac92e937 net: sh_eth: Separate out MAC address programming
Pull out the code for writing MAC address into the NIC into a
separate function, so it can be reused by both DM and non-DM
code. This is done in preparation for DM support, which handles
MAC address programming separately.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-01-27 20:38:53 +01:00
Marek Vasut
52c15e220b net: sh_eth: Split sh_eth_recv
Split sh_eth_recv into two functions, one which checks whether
a packet was received and one which handles the received packet.
This is done in preparation for DM support, which handles these
two parts separately.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-01-27 20:38:53 +01:00
Marek Vasut
dca221bd92 net: sh_eth: Pass sh_eth_dev around
Pass sh_eth_dev structure around instead of eth_device, since the
later is specific to the legacy networking support. This change is
done in preparation for the DM addition.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-01-27 20:38:53 +01:00
Marek Vasut
effb79027e net: sh_eth: Unify CONFIG_R8A779[01234] as CONFIG_RCAR_GEN2
Use the common RCAR_GEN2 config option instead of enumerating
each SoC and having a lengthy ifdef clause. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-01-27 20:38:53 +01:00
Marek Vasut
e3105eacf5 net: ravb: staticize ravb_start
Cosmetic fix, make ravb_start() static.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-01-27 20:38:53 +01:00
Tom Rini
1d12a7c8cd Merge git://git.denx.de/u-boot-spi 2018-01-26 07:46:34 -05:00
Álvaro Fernández Rojas
48263504c8 wait_bit: use wait_for_bit_le32 and remove wait_for_bit
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Zhao Qiang
1e2d2597a6 phy: atheros: set auto-negotiation for AR8021
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:27 -06:00
Nobuhiro Iwamatsu
dcd18eaf61 net: sh-eth: Add to Kconfig and convert
This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:26 -06:00
Nobuhiro Iwamatsu
aae5d237b9 net: sh-eth: Fix misaligned cache operation warning
When we using network on board using sh-eth, it prints a lot of
"CACHE: Misaligned operation at range" messages.
This commit fixes this problem.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:26 -06:00
Nobuhiro Iwamatsu
fbfb511548 net: sh-eth: Change read/write() param to struct sh_eth_info
This changes Change structure used in sh_eth_read and sh_eth_write function
from struct sh_eth_dev to struct sh_eth_info. This is necessary to convert
to Driver Model.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:25 -06:00
Nobuhiro Iwamatsu
9b5f9ecf6e net: sh-eth: Remove bd_t from sh_eth_config()
bd_t is not used in sh_eth_config(). This deletes bd_t from sh_eth_config()

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:24 -06:00
Nobuhiro Iwamatsu
dc14867d0f net: sh-eth: Fix coding style checked by checkpatch.pl
This fixes the chord style checked by checkpatch.pl.
Details of change details are as follows:

 - Fix typo
    Change from alligned to aligned.
 - Remove whitespace before ','
 - Add spaces preferred around that '|'
 - Fix missing a blank line after declarations
 - Remove space after a cast declaration
 - Fix format of block comments
 - Add a blank line after function/struct/union/enum declarations

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:24 -06:00
Florian Fainelli
f3d78fbfaf net: phy: b53: Add b53_reg read/write commands
Add a b53_reg read/write command which allows inspecting the switch
registers. Because the Broadcom BCM53xx registers have different sizes,
we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain
expected results.

Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15 12:05:22 -06:00
Florian Fainelli
7a9ca9db40 net: designware: Pad small packets
Make sure that we pad small packets to a minimum length of 60 bytes
(without FCS). This is necessary to interface with Ethernet switches
that will reject RUNT frames unless padded correctly.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15 12:05:21 -06:00
Florian Fainelli
137963d71a net: phy: Add Broadcom BCM53xx switch driver
Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar
to the Marvell MV88E617x. This takes care of configuring the minimum
amount out of the switch hardware such that each user visible port
(configurable) and the CPU port can forward packets between each other
while preserving isolation with other ports.

This is useful for e.g: the Lamobo R1 board featuring a Broadcom
BCM53125 switch.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15 12:05:21 -06:00
Patrice Chotard
ba1f966725 net: designware: add clock support
This implementation manages several clocks, disable and
free all of them in case of error during probe and in remove
callback.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:20 -06:00
Jason Brown
32ac8b0bba net: mvneta - Fixed recv() when multiple packets have arrived.
This patch fixes a problem in the mvneta driver where if more than
one packet arrives between calls to mvneta_recv(), the additional
descriptors will be marked as free even though only one descriptor
has been read and processed from the receive queue.  This causes
the additional packet(s) to be delayed until the next packet arrives.
>From this point on all packets will be delayed because the receive
queue will contain unprocessed packets but the hardware shows no
busy descriptors.

Signed-off-by: Jason Brown <jason.brown@apcon.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:19 -06:00
Chris Brandt
33bab10457 net: miiphybb: fix casting error
Since the return value is a signed int, if the leading MSB of rdreg is a 1,
it will get signed extended and will return a negative value which is an
error even though we read the correct value.

Fixes: dfcc496ed7 ("net: mii: Changes not made by spatch")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:17 -06:00
Chris Brandt
f6ac626c8a net: sh-eth: remove sh_eth_offset_rz table
First, this table could never be included in the build anyway because
SH_ETH_TYPE_RZ is not defined until later in the file.
Second, the register PIR was missing, so PHY MDIO never worked.
Third, after adding the PIR register, the table is EXACTLY the same as
sh_eth_offset_gigabit, so there is no value to it.

Therefore, just delete it use the gigabit one.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:17 -06:00
Chris Brandt
5ad565b0d1 net: sh-eth: fix inl and outl definitions
The macros inl and outl maybe already be defined from file
arch/arm/include/asm/io.h so there may be no reason to define them.
And if you do try defined them here, you get a redefined complier warning.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:16 -06:00
Lukasz Majewski
ce27eb9b40 net: phy: marvell: Add functions to read PHY's extended registers
This commit allows extended Marvell registers to be read with:

foo > mdio rx FEC 3.10
Reading from bus FEC
PHY at address 0:
3.16 - 0x1063
foo > mdio wx FEC 3.10 0x1011

The above code changes the way ETH connector LEDs blink.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:16 -06:00
Joe Hershberger
3cacc6a772 net: Fix buffer overrun error in netconsole
Need to not access the byte after the input_buffer.

Reported-by: Coverity (CID: 144423)
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:14 -06:00
Wilson Lee
4bf56913d0 net: macb: Add support for Xilinx Zynq SoC
Although Xilinx Zynq SoC was using MACB similar hardware. However,
U-boot MACB driver was not supporting Xilinx Zynq SoC. This patch is
to add support for the Xilinx Zynq SoC to the existing MACB network
driver.

This patch is to add Zynq GEM DMA Config, provide callback
function for different linkspeed for case of using Xilinx Zynq
Programmable Logic as GMII to RGMII converter.

This patch convert the return value to use error codes.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:14 -06:00
Tom Rini
6bf634223a Merge git://git.denx.de/u-boot-fsl-qoriq 2018-01-11 11:18:49 -05:00
Ahmed Mansour
541d57663f configs: Move SYS_DPAA_QBMAN to Kconfig
The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
add device tree fixups that allow deep sleep in Linux. The define was
placed in header files included by a number of boards, but was not
explicitly documented in any of the Kconfigs. A description was added
to the drivers/networking menuconfig and default selection for
current SOCs that have this part

Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10 12:28:58 -08:00
Miquel Raynal
e7ab2ccd15 ARM: mvebu: Allow MVNETA to be selected with Armada 3700 SoCs
Until now, Armada 3700 SoCs could not enable the mvneta driver, and thus
did not benefit from Ethernet support. Add ARMADA_3700 in the
"depends on" list of the MVNETA Kconfig entry.

Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Tom Rini
76cc372879 Merge git://git.denx.de/u-boot-sunxi 2017-12-19 07:57:33 -05:00
Tom Rini
1a3fc354b5 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-12-18 18:39:00 -05:00
Jerome Brunet
30cbb524bc net: phy: meson-gxl: detect LPA corruption
This patch is ported from the Linux patch posted at [1] and applied to
net tree as commit f1e2400a80ff.

The purpose of this change is to fix the incorrect detection of the link
partner (LP) advertised capabilities which sometimes happens with this PHY
(roughly 1 time in a dozen)

This issue may cause the link to be negotiated at 10Mbps/Full or
10Mbps/Half when 100MBps/Full is actually possible. In some case, the link
is even completely broken and no communication is possible.

To detect the corruption, we must look for a magic undocumented bit in the
WOL bank (hint given by the SoC vendor kernel) but this is not enough to
cover all cases. We also have to look at the LPA ack. If the LP supports
Aneg but did not ack our base code when aneg is completed, we assume
something went wrong.

The detection of a corrupted LPA triggers a restart of the aneg process.
This solves the problem but may take up to 6 retries to complete.

[1] https://lkml.kernel.org/r/20171208110811.30789-1-jbrunet@baylibre.com

Fixes: 8995a96d1d ("net: phy: Add Amlogic Meson GXL Internal PHY support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-18 13:06:30 -05:00
Wenbin song
a8f33034f2 armv8: ls1043a/ls2080a: check SoC by device ID
Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities of the same SoC family.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-13 13:40:29 -08:00
Marek Vasut
9e4a63736e net: ravb: Add R8A77995 D3 compatible
Add new compatible to the Ethernet AVB driver for R8A77995 D3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:26 +01:00
Marek Vasut
dc3bb3d41e net: ravb: Add R8A77970 V3M compatible
Add new compatible to the Ethernet AVB driver for R8A77970 V3M SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:26 +01:00
Stefan Mavrodiev
aba3924927 sunxi: Fix A20-OLinuXino-MICRO LAN8710 support
>From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-12-07 10:57:23 +05:30
Yogesh Gaur
73fa206aef driver: fsl-mc: MC object cleanup when DPL not loaded
For case when MC is loaded but DPL is not deployed perform MC
object [DPBP, DPIO, DPNI and DPRC] cleanup.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-06 14:56:31 -08:00
Yogesh Gaur
2557c5a942 driver: net: fsl-mc: flib changes for MC 10.3.0
Existing MC driver framework is based on MC-9.x.x flib. This patch
migrates MC obj (DPBP, DPNI, DPRC, DPMAC etc) to use latest MC flib
which is MC-10.3.0.

Changes introduced due to migration:
1. To get OBJ token, pair of create and open API replaces create APIs
2. Pair of close and destroy APIs replaces destroy APIs
3. For version read, get_version APIs replaces get_attributes APIs
4. dpni_get/reset_statistics APIs replaces dpni_get/set_counter APIs
5. Simplifies struct dpni_cfg and removes dpni_extended_cfg struct
6. Single API dpni_get_buffer_layout/set_buffer_layout replaces
   dpni_get_rx/set_rx, tx related, tx_conf_buffer_layout related APIs.
   New API takes a queue type as an argument.
7. Similarly dpni_get_queue/set_queue replaces
   dpni_get_rx_flow/set_rx_flow , tx_flow related, tx_conf related
   APIs

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-06 14:55:17 -08:00
Marek Vasut
90997cda76 net: ravb: Fix reset GPIO handling
Fix handling of the reset GPIO. Drop the _nodev() suffix from the
gpio_request_by_name() call as there is now a proper DM capable
GPIO driver. Also check if the GPIO is valid before freeing it in
remove path, otherwise U-Boot will crash.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:34 +01:00
Siva Durga Prasad Paladugu
a04a5daae2 net: xilinx_axi_emac: Use readl and writel for io ops
This patch uses readl and writel instead of in_be32 and
out_be32 for io ops as these internally uses readl,
writel for microblaze and for Zynq, ZynqMP there is
no need of endianness conversion and readl, writel
should work straightaway. This patch starts supporting
the driver for Zynq and ZynqMP platforms.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Siva Durga Prasad Paladugu
dd12a27ce2 net: zynq_gem: Dont enable SGMII and PCS selection
Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Siva Durga Prasad Paladugu
89ce5a9dbe net: xilinx_axi_emac: Add support for non processor mode
Add support for non processor mode, this mode doesn't have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2017-11-29 08:02:33 +01:00
Siva Durga Prasad Paladugu
dc1fcc423c net: xilinx_axi_emac: Read dma address using fdtdec_get_addr
Read dma address using fdtdec_get_addr as it checks for
address cells and size cells and reads the address
properly. fdtdec_get_int always assume address is of int
size which goes wrong if using it on 64-bit architecture.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:27 +01:00
Siva Durga Prasad Paladugu
d02a0b1fdf net: xilinx_axi_emac: Use wait_for_bit instead of while loop
Use wait_for_bit instead while loop during init

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2017-11-28 16:09:27 +01:00
Neil Armstrong
8995a96d1d net: phy: Add Amlogic Meson GXL Internal PHY support
The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY.

The PHY acts as a generic PHY but needs a slight configuration right
before it's configuration.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-11-17 07:44:13 -05:00
Prabhakar Kushwaha
f53e12d80a driver: net: fsl-mc: Use base 16 in simple_strtoul
Value provided in MC_MEM_SIZE_ENV_VAR is in hex. Use 16 as base
in simple_strtoul.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-15 10:53:15 -08:00
Ashish Kumar
5e9445da28 drivers: net: ldpaa_eth: Correct error handler for qbman_swp_acquire()
The zero value returned from qbman_swp_acquire() is an error
condition meaning no free buffer for allocation.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kushwaha Prabhakar <prabhakar@freescale.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-14 08:33:20 -08:00
Chen-Yu Tsai
13ae2a40e7 net: sun8i_emac: Fix build for non-H3/H5 SoCs
Only the H3/H5 SoCs have an internal PHY and its related clock and
reset controls.

Use an #ifdef to guard the internal PHY control code block so it
can be built for other SoCs, such as the A83T or A64.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-10 19:10:33 +05:30
Artturi Alm
6270a3f035 sunxi: restore PHYLIB for CONFIG_SUN4I_EMAC users
due misnaming of CONFIG_SUN4I_EMAC in include/configs/sunxi-common.h,
likely missed in:
	commit 3146f0c017 ("Move PHYLIB to Kconfig")

Signed-off-by: Artturi Alm <artturi.alm@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-09 14:39:30 +05:30
Artturi Alm
e286fada9d sunxi: fix CONFIG_SUNXI_EMAC references
fixes CONFIG_SUNXI_EMAC references from drivers/net/Makefile and
include/configs/sunxi-common.h likely forgotten in:
	commit abc3e4df59 ("sunxi: Convert SUNXI_EMAC to Kconfig")

Signed-off-by: Artturi Alm <artturi.alm@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-09 14:39:09 +05:30
Fabio Estevam
41b93679fd net: fec_mxc: Change "error frame" message to debug level
As reported by Jonathan Gray:

"After the recent changes to add SimpleNetworkProtocol to efi_loader
when booting off mmc via an efi payload that doesn't use
SimpleNetworkProtocol U-Boot's fec_mxc driver will now display
various "error frame" messages.
....
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Scanning disks on sata...
Found 6 disks
reading efi/boot/bootarm.efi
67372 bytes read in 32 ms (2 MiB/s)
## Starting EFI application at 12000000 ...
>> OpenBSD/armv7 BOOTARM 1.0
error frame: 0x8f57ec40 0x00003d74
error frame: 0x8f57ec40 0x00007079
error frame: 0x8f57ec40 0x00006964
error frame: 0x8f57ec40 0x00006f6f
error frame: 0x8f57ec40 0x0000726f
error frame: 0x8f57ec40 0x00002074
error frame: 0x8f57ec40 0x00006f6f"

Heinrich Schuchardt explains:

"A receive FIFO overrun can be expected if network packages are not
processed.
With the network patches we check if a package is available quite often."

Move the "error frame" messages to debug level so that a clean output
log can be seen.

Reported-by: Jonathan Gray <jsg@jsg.id.au>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-30 18:57:42 +01:00
Ashish Kumar
2af1b08a1a armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_ID
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.

These change where introduced in phy driver in commit 05b29aa0cb
("net: phy: realtek: fix enabling of the TX-delay for RTL8211F").

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:41:12 -07:00
Prabhakar Kushwaha
a572fb6bdd driver: fsl-mc: use calloc instead malloc
Memory allocated via malloc is not guaranteed to be zeroized.
So explicitly use calloc instead of malloc.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:38:29 -07:00
Adam Ford
8daec2d9d3 net: Add SMC911X driver to Kconfig, convert
We add the various SMC91XX symbols to drivers/net/Kconfig and then this
converts the following to Kconfig:
   CONFIG_SMC911X
   CONFIG_SMC911X_BASE
   CONFIG_SMC911X_16_BIT
   CONFIG_SMC911X_32_BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Apply to the rest of the tree, re-squash old and new patch]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 21:40:26 -04:00
Tom Rini
2ee87b0c1a Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2017-10-10 20:14:38 -04:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Chris Packham
7654f62f4e ARM: mvebu: Convert CONFIG_MVNETA to Kconfig
This converts the following to Kconfig:
   CONFIG_MVNETA

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26 06:51:30 +02:00
Marek Vasut
bddb44e94a net: ravb: Add PHY reset GPIO support
Add support for obtaining PHY reset GPIO from DT and toggling it
before configuring the PHY to put the PHY into defined state.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-24 14:12:07 +09:00
rick
1341494c7d nds32: ftmac100: Fix write mac addr fail problem.
After soft reset complete, write mac address immediately will fail.
Add delay to work around this problem.

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
rick
ce4e2370f7 nds32: ftmac100: support cache enable.
Add cache inval and flush when rx and tx.

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
Philipp Tomsich
b343837e90 net: phy: micrel: Convert to livetree
Update the Micrel KSZ90x1 driver for a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:34 +02:00
Philipp Tomsich
15050f1cb0 net: designware: Convert to livetree
Update the Designware Ethernet MAC driver to support a live device
tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:34 +02:00
Bin Meng
723b43daec blk: Remove various places that do flush cache after read
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.

The underlying drivers should be responsible for the cache operation.
Remove these codes completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
2017-09-15 08:05:10 -04:00
Ashish Kumar
17d066fc5d armv8: fsl-layerscape: Support to add RGMII for ls1088aqds
This patch adds support for RGMII protocol

NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
6d9b82d085 armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Priyanka Jain
033c538e56 drivers:net:fsl-mc: Update MC address calculation
Update MC address calculation as per MC design requirement of address
as least significant 512MB address of MC private allocated memory,
i.e. address should point to end address masked with 512MB offset in
private DRAM block.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
[YS: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Heinrich Schuchardt
e4691564cc net: fix typos
%s/Desriptor/Descriptor/g

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-09-07 13:23:52 -05:00
Madalin Bucur
05b29aa0cb net: phy: realtek: fix enabling of the TX-delay for RTL8211F
The old logic always enabled the TX-delay when the phy-mode was set to
PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for
PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and
disable it for PHY_INTERFACE_MODE_RGMII.

Based on a similar change made in the Linux Realtek PHY driver
by Martin Blumenstingl <martin.blumenstingl@googlemail.com>.

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
2017-09-07 13:23:52 -05:00
Tom Rini
470135be27 Merge git://www.denx.de/git/u-boot-imx
Update pfla02 for setenv changes and PHYLIB/etc migration to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16 18:12:00 -04:00
Simon Glass
723806cc5b env: Rename some other getenv()-related functions
We are now using an env_ prefix for environment functions. Rename these
other functions as well, for consistency:

   getenv_vlan()
   getenv_bootm_size()
   getenv_bootm_low()
   getenv_bootm_mapsize()
   env_get_default()

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:31:11 -04:00
Simon Glass
35affd7a2f env: Rename eth_getenv_enetaddr() to eth_env_get_enetaddr()
Rename this function for consistency with env_get().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:44 -04:00
Simon Glass
00caae6d47 env: Rename getenv/_f() to env_get()
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.

Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:24 -04:00
Simon Glass
fd1e959e91 env: Rename eth_setenv_enetaddr() to eth_env_set_enetaddr()
Rename this function for consistency with env_set().

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:56 -04:00
Simon Glass
018f530323 env: Rename common functions related to setenv()
We are now using an env_ prefix for environment functions. Rename these
commonly used functions, for consistency. Also add function comments in
common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:23:32 -04:00
Simon Glass
382bee57f1 env: Rename setenv() to env_set()
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:22:18 -04:00
Prabhakar Kushwaha
a5fe87e829 driver: net: ldpaa: Update priv->phydev after free()
Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv->phydev as NULL after memory free.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-14 12:47:33 -05:00
Madalin Bucur
3f8f1410b5 net: fman: add support RGMII_TXID to memac
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-14 12:47:32 -05:00
Philipp Tomsich
793f2fd2dc net: gmac_rockchip: Add support for the RK3368 GMAC
The GMAC in the RK3368 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3368-specific logic necessary to reuse this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-13 17:12:33 +02:00
Tom Rini
7f513e8196 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-08-11 07:10:18 -04:00
Stefan Chulski
ceec6c48a4 net: mvpp2x: Set BM poll size once during priv probe
Set BM poll size once during priv probe and do not
overwrite it during port probe procedure. Pool is common for
all CP ports.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
a25962c417 net: mvpp2x: remove TX drain from transmit routine
TX drain in transmit procedure could cause issues due
to race between drain procedure and transmition of descriptor
between AGGR TXQ and physical TXQ.
TXQ will be cleared before moving to Linux by stop procedure.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
783e78562d net: mvpp2x: Set BM pool high address
MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
16f18d2a4d net: mvpp2x: Remove IRQ configuration from U-Boot
Remove IRQ configuration from U-Boot PP driver.
U-Boot don't use interrupts and configuration of IRQ in U-Boot
caused crashes in Linux shared interrupt mode.
Also interrupt use is redundant in RX routine since a single RX
queue is used.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
d4b0e00829 net: mvpp2x: remove MBUS configurations from MvPP22 driver
MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
f0e970fd2a net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.

Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
bb915c843f net: mvpp2x: fix BM configuration overrun issue
Issue:
BM counters were overrun by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.

Fix:
Use probe_done and num_ports to call init and remove procedure
once per communication controller.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
73f592fb72 net: mvpp2x: Enable GoP packet padding in TX
This patch enables padding of packets shorter than 64B in TX(set by default).
Disabling of padding causes crashes on MACCIATO board.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
377883f16d net: mvpp2x: fix phy connected to wrong mdio issue
A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.

Issue:
Wrong base address is assigned to MDIO interface during probe.

Fix:
Get MDIO address from PHY handler parent base address.

This should be refined in the future when MDIO driver is implemented.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Stefan Chulski
4189373a3d net: mvpp2x: Add GPIO configuration support
This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-08-10 08:33:02 +02:00
Santan Kumar
06651b9456 driver: net: fsl-mc: fsl_mc_ldpaa_exit exit earlier if dpl applied
In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied,
it should return earlier without executing dpbp_exit().

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:33 -07:00
Sebastien Bourdelin
ef1f61aa03 net: phy: micrel: add an option to disable gigabit for the KSZ9031
The environment variable "disable_giga" can now be used to disable
1000baseTx on the Micrel's KSZ9031.

Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:31 -05:00
Arun Parameswaran
d7e8ac6f45 net: phy: Add AFE settings to the Broadcom Cygnus phy
Added the AFE (Analog Front End) settings for stability to the
Broadcom Cygnus phy. This improves the time take to perform
auto negotiation.

Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:31 -05:00
Suji Velupillai
c89782dcac net: move Broadcom SF2 driver to Kconfig
move to Kconfig:
	CONFIG_BCM_SF2_ETH
	CONFIG_BCM_SF2_ETH_DEFAULT_PORT
	CONFIG_BCM_SF2_ETH_GMAC

Also modified defconfigs of all platforms that use these configs.

Signed-off-by: Suji Velupillai <suji.velupillai@broadcom.com>
Tested-by: Suji Velupillai <suji.velupillai@broadcom.com>
Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
9a31c739d2 net: phy: Hide Micrel KSZ9021 and KSZ9031 Kconfig options
The correct option is PHY_MICREL_KSZ90X1, but some configs still
select the 9021 and 9031 options, which are deprecated.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
fbc120e668 net: phy: micrel: Remove ksz90x1 drivers from micrel_ksz8xxx
There should be no longer be any ksz9000 users that pick up the PHY
driver from ksz8xxx, so remove ksz9000 remnants from there.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
d397f7c45b net: phy: micrel: Separate KSZ9000 drivers from KSZ8000 drivers
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.

As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.

To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Alexandru Gagniuc
cb543d30df net: phy: Remove duplicate Kconfig selection for Micrel KSZ9021
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:29 -05:00
Joe Hershberger
2fd519f777 net: ag7xxx: Propagate errors on phy access
Don't wait forever.
Pass errors back to the caller.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Marek Vasut <marex@denx.de>
2017-08-07 15:18:29 -05:00
Joe Hershberger
9240a2f5f1 net: ag7xxx: Comment register names
The register constants don't use the exact names that are used in the
TRM, so add comments that use the exact names so that it is clear what
register is being referred to.

https://www.atheros-drivers.com/qualcomm-atheros-datasheets-for-AR9331.html

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Marek Vasut <marex@denx.de>
2017-08-07 15:18:29 -05:00
Christian Gmeiner
8f0b169382 drivers/net/phy/fixed: do not overwrite addr
phy_device_create(..) sets the addr of phy_device with a sane value.
There is no need overwrite it.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:28 -05:00
Marek Vasut
1fea9e25fa net: ravb: Add clock handling support
Add support for enabling and disabling the clock using the clock
framework based on the content of OF instead of doing it manually
in the board file.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:25 +09:00
Marek Vasut
e821a7bdb1 net: ravb: Detect PHY correctly
The order of parameters passed to the phy_connect() was wrong.
Moreover, only PHY address 0 was used. Replace this with code
capable of detecting the PHY address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:25 +09:00
Marek Vasut
5ee8b4d7f5 net: ravb: Add OF probing support
Add support for probing the RAVB Ethernet block from device tree.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-03 04:26:25 +09:00
Lothar Waßmann
cb5761f774 net: fec_mxc: adjust prototype of fec_get_miibus() for DM_ETH
commit 306dd7dabd ("net: fec_mxc: fix PHY initialization bug with CONFIG_DM_ETH")
has broken the build of the fec_mxc driver with CONFIG_DM_ETH
enabled because it changed the parameters passed to *fec_get_miibus()
without changing the functions prototype.

This patch fixes up the prototype of fec_get_miibus() for the DM_ETH case.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
2017-07-28 13:41:49 +02:00
Christophe Leroy
08dd988be5 powerpc, 8xx: fix missing function declarations.
Add missing .h and add missing declarations in .h
Declare local functions as static.  Make interrupt_init_cpu function
signatures consistent with how decrementer_count is declared.

Based on warnings reported by 'make C=2'

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[trini: drop cpu_init_f as 8xx/83xx are different from the rest, rework
interrupt_init_cpu/decrementer_count]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-23 09:23:29 -04:00
Tom Rini
39632b4a01 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-07-18 08:42:48 -04:00
Stefano Babic
552a848e4f imx: reorganize IMX code as other SOCs
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 10:17:44 +02:00
Lothar Waßmann
306dd7dabd net: fec_mxc: fix PHY initialization bug with CONFIG_DM_ETH
When CONFIG_DM_ETH is set, the FEC ethernet controller is reset after
the PHY has been set up and initialzed. This breaks the communication
with the PHY and results in an inoperable ethernet interface.

Do the initialization with CONFIG_DM_ETH in the same order as with
legacy ETH support to fix this.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-12 09:44:22 +02:00
Grygorii Strashko
750b34c9ae net: fm: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-11 22:41:48 -04:00
Grygorii Strashko
1ceac70080 net: phy: cortina: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-11 22:41:48 -04:00
Philipp Tomsich
7ad326a905 rockchip: net: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the Gigabit Ethernet MAC (i.e. common designware driver and
rockchip-specific wrapper).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Christophe Leroy
53193a4f07 powerpc, 8xx: Add support for MCR3000 board from CSSI
CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000
and CMPC885 which are respectively based on MPC866 and MPC885 processors.

This patch adds support for the first board.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-08 15:56:06 -04:00
Christophe Leroy
fad51ac3af powerpc, 8xx: move FEC Ethernet driver in drivers/net
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-08 15:56:02 -04:00
Heiko Schocher
98f705c9ce powerpc: remove 4xx support
There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>
2017-07-03 17:35:28 -04:00
Tom Rini
de8203653f ti816x: Enable ethernet support
The ti816x SoC revision of the ethernet IP block is handled by the
"davinci_emac" driver, rather than the "cpsw" driver as done by later
members of the family.  Enable the relevant plumbing.

Signed-off-by: Sriramakrishnan <srk@ti.com>
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-28 11:43:39 -04:00
Tom Rini
821560fd8e Merge git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/imx6qdl_icore_rqs.h
	include/configs/imx6ul_geam.h
	include/configs/imx6ul_isiot.h
2017-06-27 09:32:37 -04:00
Heiko Schocher
064b55cfcb powerpc, 5xxx, 512x: remove support for mpc5xxx and mpc512x
There was for long time no activity in the mpx5xxx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in mpc5xxx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>
2017-06-16 10:14:55 -04:00
Masahiro Yamada
51855e8981 treewide: remove unneeded semicolons
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-16 10:11:38 -04:00
Tom Rini
4f58002013 Merge git://git.denx.de/u-boot-mpc85xx 2017-06-14 18:53:03 -04:00
York Sun
ef621da7f8 net: phy: marvell: Fix init function for m88e1145
Commit a058052c changed the generic phy_reset() to clear all bits in
BMCR. This inevitably clears the ANEG bit. m88e1145 requires any
change to ANEG bit to be followed by a software reset. This seems to
be different from other PHYs. Implement read-modify-write procedure
for this PHY init.

Signed-off-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-12 12:18:14 -07:00
Heiko Schocher
5b8e76c35e powerpc, 8xx: remove support for 8xx
There was for long time no activity in the 8xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8xx,
so remove it (with a heavy heart, knowing that I remove
here the root of U-Boot).

Signed-off-by: Heiko Schocher <hs@denx.de>
2017-06-12 08:37:55 -04:00
Simon Glass
6e2941d787 common: freescale: Move arch-specific declarations
The declarations should not be in common.h. Move them to the arch-specific
headers.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05 12:30:55 -04:00
Tom Rini
5cafcbab58 Merge git://git.denx.de/u-boot-net 2017-06-03 18:05:28 -04:00
Tom Rini
541f538f4c Merge git://git.denx.de/u-boot-fsl-qoriq 2017-06-03 18:05:04 -04:00
Paul Burton
2303bff7d5 net: pch_gbe: Add cache maintenance
On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is
present. When there is no IOCU we need to writeback or invalidate the
data caches at appropriate points. Perform this cache maintenance in
the pch_gbe driver which is used on the MIPS Boston development board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:20 -05:00
Paul Burton
52e727c8eb net: pch_gbe: CPU accessible addresses are virtual
Use the virt_to_bus & bus_to_virt functions rather than phys_to_bus &
bus_to_phys, since the addresses accessed by the CPU will be virtual
rather than physical. On MIPS physical & virtual addresses differ as we
use virtual addresses in kseg0, and attempting to use physical addresses
directly caused problems as they're in the user segment which would be
mapped via the uninitialised TLB.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:20 -05:00
Paul Burton
db225f1131 net: pch_gbe: Fix rx descriptor buffer addresses
The loop to set up buffer addresses in rx descriptors always operated on
descriptor 0, rather than on each descriptor sequentially. Fix this in
order to setup correct buffer addresses for each descriptor.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:20 -05:00
Paul Burton
43979cbacb net: pch_gbe: Reset during probe
Using the EG20T gigabit ethernet controller on the MIPS Boston board, we
find that we have to reset the controller in order for the RGMII link to
the PHY to become functional. Without doing so we constantly time out in
pch_gbe_mdio_ready.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:20 -05:00
Siva Durga Prasad Paladugu
f0b94c4bcd net: zynq_gem: Dont flush dummy descriptors
Dont flush dummy descriptors as they are already
allocated from a region with dcache off. Tested
this on Zynq(zc702) and ZynqMP(zcu102) boards.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:20 -05:00
Siva Durga Prasad Paladugu
dea004e41a net: zynq_gem: Use wait_for_bit with non breakable
Use wait_for_bit to be non breakable as using it with
breakable causes issue of un interruptible auto negotiation.
This is due to the ctrlc pressed will taken for wait_for_bit()
abort during phy_read() and hence not coming out of
auto negotiation.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:20 -05:00
Phil Edworthy
68e6ecadc5 net: phy: marvell 88e151x: Fix handling of RGMII interface types
The 88E1518 code is programming the wrong registers for rgmii-id,
rgmii-txid and rgmii-rxid interfaces.

Since the PHY defaults to rgmii-id, it would appear that the code
was previously only used with sgmii and rgmii-id interfaces.

Tested on 88E1512 PHY in rgmii-id mode which is from the same family
as 88E1518.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:19 -05:00
Sekhar Nori
96d1d84c79 drivers: net: cpsw: abort init() on aneg timeout
Abort CPSW driver init when auto-negotiation of link
times out. Currently, the code ignores return status
of phy_startup(), and goes ahead with network operation
(like DHCP) even though the link may be down.

Instead, abort init process if link is down or if there
is another error, so phy_startup() can easily be retried
again. This also helps quick fallback to next network interface
(like USB RNDIS) without inordinate delay.

Tested on AM571x IDK and AM335x BeagleBone black.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:19 -05:00
Wenyou Yang
6de046eaa7 net: macb: Fix GMAC not work when enable DM_ETH
Always search the PHY to determine the macb->phy_addr before using
the PHY to fix "No PHY present" error.

Fix the wrong test of the GMAC's phy interface mode, it should be
PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:19 -05:00
Stefan Chulski
e09d0c8314 net: mvpp2.c: Enable 10G support for port 0 (SFI)
This patch fixes some remaining issues in the mvpp2 driver for the 10GB
support on port 0. These changes are:

- Incorrect PCS configuration
- Skip PHY configuration when no PHY is connected
- Skip GMAC configurations if 10G SFI mode set

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:19 -05:00
Madalin Bucur
cc1aa218f5 armv8/ls1046a: RGMII PHY requires internal delay on Tx
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:18 -05:00
Madalin Bucur
5a78a472f6 armv8/ls1043a: RGMII PHY requires internal delay on Tx
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:18 -05:00
Olliver Schinagl
b233089787 net: zynq_gem: Do not return -ENOSYS on success
The .read_rom_hwaddr net_ops hook does not check the return value, which
is why it was never caught that we are currently returning 0 if the
read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise.

In this case we can simplify this by just returning the result of the
function.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-06-02 14:44:18 -05:00
Jacob Chen
6ec922fae2 net: designware: Add phy supply support
Some board need a regulator for gmac phy, so add this code to handle it.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:18 -05:00
Philipp Tomsich
449ea2cd0d net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectable
This change migrate the following configuration options for Kconfig:
 * PHY_GIGE, indicates that a controller (with an appropriate PHY) is
   Gigabit capable and enables extra support in the miiutil for
   parsing the status of Gigabit PHYs
 * adds configuration options for Micrel KSZ9021 and KSZ9031 GbE PHYs,
   which previously had to enabled through a board-specific config file

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:18 -05:00
Bogdan Purcareata
1161dbcc0a drivers: net: fsl-mc: Include MAC addr fixup to DPL
Previous to MC v10.x, port mac address was specified via DPL. Since
newer MC versions are compatible with old style DPLs, make the u-boot
env mac addresses visible there. This applies only to DPLs that have
an older version.

DPLs use 32 bit values for specifying MAC addresses. U-boot
environment variables take precedence over the MAC addresses already
visible in the DPL/DPC.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Signed-off-by: Heinz Wrobel <heinz.wrobel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-01 19:56:24 -07:00
Bogdan Purcareata
33a8991a87 drivers: net: fsl-mc: Link MC boot to PHY_RESET_R
DPAA2 platforms boot the Management Complex based on the u-boot env
variable "mcinitcmd". Instead of doing this step on each platform
individually, define a single mc_env_boot function in the MC driver,
since it's semantically tied to it.

Call the function in a per-board reset_phy hook, as it gets called at a
later moment, when all board PHY devices have been initialized.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Signed-off-by: Heinz Wrobel <heinz.wrobel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-01 19:55:50 -07:00
Simon Glass
eed36609b5 fdt: Rename a few functions in fdt_support
These two functions have an of_ prefix which conflicts with naming used
in of_addr. Rename them:

   fdt_read_number
   fdt_support_bus_default_count_cells

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:11 -06:00
Simon Glass
150c5afe5b dm: gpio: Add live tree support
Add support for requesting GPIOs with a live device tree.

This involves adjusting the function signature for the legacy function
gpio_request_by_name_nodev(), so fix up all callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes to stm32f746-disco.c:
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-01 07:03:10 -06:00
Simon Glass
45a26867e8 dm: core: Update device_bind_driver_to_node() to use ofnode
Adjust this function to us an ofnode instead of an offset, so it can be
used with livetree. This involves updating all callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:08 -06:00
Simon Glass
911f3aef35 dm: core: Rename of_device_is_compatible()
The of_ prefix conflicts with the livetree version of this function.
Rename it to avoid problems when we add livetree support.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:06 -06:00
Simon Glass
da409ccc4a dm: core: Replace of_offset with accessor (part 2)
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:04 -06:00
Simon Glass
a821c4af79 dm: Rename dev_addr..() functions
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:01 -06:00
Simon Glass
9d922450aa dm: Use dm.h header when driver mode is used
This header includes things that are needed to make driver build. Adjust
existing users to include that always, even if other dm/ includes are
present

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 06:57:52 -06:00
Jagan Teki
a43241a406 drivers: net: Kconfig: Add PHY_MICREL_KSZ9021 entry
Add kconfig entry for Micrel KSZ9021 PHY support.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-05-31 10:22:14 +02:00
Tom Rini
380e86f361 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-05-26 11:19:27 -04:00
Tom Rini
8dc1b17f14 Merge branch 'master' of git://git.denx.de/u-boot-nds32
Move FTMAC100 to where it should be, alphabetically in
drivers/net/Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	drivers/net/Kconfig
2017-05-26 11:18:53 -04:00
Yogesh Gaur
42e8179007 driver: net: fsl-mc: Update fsl_mc_ldpaa_exit() path
Earlier when MC is loaded but DPL is not deployed results in FDT
fix-up code execution hangs. For this case now print message on
console and return success instead of return -ENODEV. This update
allows fdt fixup to continue execution.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <Priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23 09:24:59 -07:00
rick
be71a179bd nds32: eth: Support ftmac100 DM.
Support Andestech eth ftmac100 device tree flow on AG101P/AE3XX platform.
Verification:
 Boot linux kernel via dhcp and bootm ok.

 NDS32 # setenv bootm_size 0x2000000;setenv fdt_high 0x1f00000;
 NDS32 # dhcp 0x600000 10.0.4.97:boomimage-310y-ae300-spi.bin
 BOOTP broadcast 1
 BOOTP broadcast 2
 BOOTP broadcast 3
 BOOTP broadcast 4
 DHCP client bound to address 10.0.4.178 (4899 ms)
	Using mac@e0100000 device
	TFTP from server 10.0.4.97; our IP address is 10.0.4.178
	Filename 'boomimage-310y-ae300-spi.bin'.
	Load address: 0x600000
	Loading: #################################################################
	         #################################################################
	         #################################################################
...
...
	         ###################################
	         233.4 KiB/s
					 done
					 Bytes transferred = 13872076 (d3abcc hex)
	NDS32 # dhcp 0x2000000 10.0.4.97:ae300.dtb
	BOOTP broadcast 1
	BOOTP broadcast 2
	BOOTP broadcast 3
	BOOTP broadcast 4
	DHCP client bound to address 10.0.4.178 (4592 ms)
	Using mac@e0100000 device
	TFTP from server 10.0.4.97; our IP address is 10.0.4.178
	Filename 'ae300.dtb'.
	Load address: 0x2000000
	Loading: #
	         82 KiB/s
					 done
					 Bytes transferred = 2378 (94a hex)
	NDS32 # bootm 0x600000 - 0x2000000
	 Image Name:
	 Created:      2017-03-22   6:52:03 UTC
	 Image Type:   NDS32 Linux Kernel Image (uncompressed)
	 Data Size:    13872012 Bytes = 13.2 MiB
	 Load Address: 0000c000
	 Entry Point:  0000c000
	 Verifying Checksum ... OK
	 Booting using the fdt blob at 0x2000000
	 Loading Kernel Image ... OK
	 Loading Device Tree to 01efc000, end 01eff949 ... OK
	 Linux version 3.10.102-20375-gb0034c1-dirty (rick@app09)
	(gcc version 4.9.3 (2016-07-06_nds32le-linux-glibc-v3_experimental) )
  #293 PREEMPT Wed Mar 22 14:49:28 CST 2017
	CPU: NDS32 N13, AndesCore ID(wb), CPU_VER 0x0d11103f(id 13, rev 17, cfg 4159)
...
...
Signed-off-by: rick <rick@andestech.com>
2017-05-23 13:48:27 +08:00
Marek Vasut
8ae51b6f32 net: ravb: Add Renesas Ethernet RAVB driver
Add driver for the Renesas Ethernet AVB block found in RCar H3/M3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Based on work of:
Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Takeshi Kihara <takeshi.kihara.df@renesas.com>
Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
2017-05-22 04:38:24 +09:00
Andy Duan
979a58936b net: fec_mxc: specify the registered eth index by dev_id
Specify the registered eth index by dev_id.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2017-05-18 11:23:31 +02:00
Andy Duan
f01e4e1e14 net: fec_mxc: avoid transfer dev_id -1 to get mac address from fuse
Avoid transfer parameter dev_id value with "-1" to .fec_get_hwaddr(),
it should transfer fec->dev_id to get mac address from fuse.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2017-05-18 11:23:31 +02:00
Peng Fan
27255fe821 net: fec: do not access reserved register for i.MX6ULL
The MIB RAM and FIFO receive start register does not exist on
i.MX6ULL. Accessing these register will cause enet not work well or
cause system report fault.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2017-05-18 11:23:31 +02:00
Tom Rini
65a4771085 net: uli526x: Fix unknown storage size error
The variable netdev_ethtool_ops is not referenced, drop it.  However
with gcc-6 or later we fail to even compile as we do not have the
required struct definition in U-Boot.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-12 08:37:32 -04:00
Tom Rini
4201223de8 net: phy: mv88e61xx: Fix uninitialized variable warning
The variable 'res' may be unused uninitialized if our call to
mv88e61xx_port_read (register read) fails and we goto the error
handling section.  In this case we set 'res' to -EIO to indicate why we
failed.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-12 08:37:30 -04:00
Tom Rini
63c6f1ce3c net: eepro100: Fix unused variable warning
The variable i82557_config_cmd is never referenced, drop.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-12 08:37:30 -04:00
Tom Rini
dd9999d5f4 Merge git://git.denx.de/u-boot-dm 2017-05-09 16:11:36 -04:00
Wenyou Yang
7546025341 net: macb: Align the compatibles with kernel
Add the compatibles to align with the kernel.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
1870d4d7bd net: macb: Add remove callback
To avoid the failure of mdio_register(), add the remove callback
to unregister the mii_dev when removing the ethernet device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fixed up unused variable warning, e.g. for gurnard:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Stefan Roese
2f720f1957 net: mvpp2: Add remove function that is called before the OS is started
This patch adds a remove function to the mvpp2 ethernet driver which is
called before the OS is started, doing:

- Allocate the used buffers back from the buffer manager
- Stop the BM activity

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-09 13:38:17 +02:00
Tom Rini
6f008a2e16 Merge git://git.denx.de/u-boot-sunxi 2017-04-25 16:12:42 -04:00
Mylène Josserand
751b0be0a1 sunxi: Convert CONFIG_RGMII to Kconfig
Convert CONFIG_RGMII to Kconfig. Thanks to that, it is possible to
update defconfig files of SYS_EXTRA_OPTIONS accordingly and
remove it when it is possible.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:20:29 +02:00
Mylène Josserand
abc3e4df59 sunxi: Convert SUNXI_EMAC to Kconfig
Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS
from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it
with SUN8I_EMAC.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:19:59 +02:00
Mylène Josserand
4d43d065db sunxi: Move SUNXI_GMAC to Kconfig
Move the SUNXI_GMAC config option to Kconfig, remove it
from SYS_EXTRA_OPTIONS and rename it into SUN7I_GMAC.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:19:56 +02:00
Tom Rini
3c476d841d Merge git://git.denx.de/u-boot-fsl-qoriq 2017-04-18 11:36:06 -04:00
Masahiro Yamada
90d6500c0f drivers: remove Blackfin specific drivers
These drivers have no user since commit ea3310e8aa ("Blackfin:
Remove").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-04-18 10:29:14 -04:00
York Sun
c1303bfd7e armv8: ls1043a: Drop macro CONFIG_LS1043A
Use CONFIG_ARCH_LS1043A instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17 09:03:30 -07:00
York Sun
4a3ab19322 armv8: ls2080a: Drop macro CONFIG_LS2080A
Use CONFIG_ARCH_LS2080A instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17 09:03:30 -07:00
Tom Rini
b7b24a7a3c Merge git://git.denx.de/u-boot-dm
Here with some DM changes as well as the long-standing AT91 DM/DT
conversion patches which I have picked up via dm.
2017-04-13 17:31:06 -04:00
Wenyou Yang
2dc63f7367 gpio: at91_gpio: remove CPU_HAS_PIO3 macro
The intention of the removal is the preparation to introduce the
new AT91 PIO pinctrl driver.

Use the union to make the PIO3 and PIO2's registers be together
and make their offset aligned.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-13 14:44:50 -06:00
Tom Rini
1622559066 Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Drop CONFIG_STACKSIZE from include/configs/imx6_logic.h

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-13 11:19:00 -04:00
Tom Rini
089795090a Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-04-08 09:28:02 -04:00
Philipp Tomsich
4d555ae3f5 sun8i_emac: configure PHY reset GPIO via DM
This ports the support for configuring a GPIO for resetting the
Ethernet PHY (incl. such details as the reset polarity and
pulse-length) from the Designware driver.

X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 10:17:25 +05:30
Tom Rini
01abae4d04 Remove various unused interrupt related code
With d53ecad92f some unused interrupt related code was removed.
However all of these options are currently unused.  Rather than migrate
some of these options to Kconfig we just remove the code in question.

The only related code changes here are that in some cases we use
CONFIG_STACKSIZE in non-IRQ related context.  In these cases we rename
and move the value local to the code in question.

Fixes: d53ecad92f ("Merge branch 'master' of git://git.denx.de/u-boot-sunxi")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-06 20:42:18 -04:00
Tom Rini
d53ecad92f Merge branch 'master' of git://git.denx.de/u-boot-sunxi
trini: Disable CONFIG_SPL_USE_ARCH_MEMSET on orangepi_2

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-06 20:40:24 -04:00
Tom Rini
936478e797 SPARC: Remove
The SPARC architecture is currently unmaintained, remove.

Cc: Francois Retief <fgretief@spaceteq.co.za>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05 13:52:20 -04:00
Tom Rini
ea3310e8aa Blackfin: Remove
The architecture is currently unmaintained, remove.

Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05 13:52:01 -04:00
Andre Przywara
7b82a229e5 sunxi: prepare for sharing MACH_SUN8I_H3 config symbol
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05 15:03:17 +05:30
Philipp Tomsich
1f08aa1c9f net: gmac_rockchip: Add support for the RK3399 GMAC
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it
is a Designware GMAC core and requires similar configuration as the
RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit).
The key difference is that the register offsets (within the GRF block)
and bit-offsets (within those registers) used to hold the configuration
differ between the various RK32/33 CPUs.

This change refactors the gmac_rockchip.c driver to use a function
table (selected via driver_data) to factor out these differences. Each
function's implementation then matches the underlying processor.

Some collateral changes are needed in the definitions describing the
bits and offsets in the GRF are needed to prefix each set of symbolic
constants with the SoC name to avoid name clashes... and in doing so,
the shifts for masks and constants have been moved into the header
files for readability (and to make it easier to stay below 80 chars).

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed commit message typo s/factor our/factor out/:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Tom Rini
f532703665 Merge git://www.denx.de/git/u-boot-marvell
This includes Marvell mvpp2 patches with the ethernet support for the
ARMv8 Armada 7k/8k platforms. The ethernet patches are all acked by Joe
and he is okay with me pushing them via the Marvell tree.
2017-04-04 09:17:56 -04:00
Tom Rini
797f165f7a Merge git://git.denx.de/u-boot-fsl-qoriq 2017-04-04 09:17:08 -04:00
Stefan Roese
fbaa266230 net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool
As pointed out by Stefan Chulski, this variable is unused and should be
removed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:37 +02:00
Stefan Roese
fb64072934 net: mvpp2: Configure SMI PHY address needed for PHY polling
On PPv2.2 we enable PHY polling, so we also need to configure the PHY
address in the specific PHY address rgisters.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:32 +02:00
Stefan Roese
3e3cbb4967 net: mvpp2: Enable PHY polling mode on PPv2.2
Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:26 +02:00
Stefan Roese
025e5921be net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID
Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should
be handled identical to PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:11 +02:00
Stefan Roese
2fe23044cd net: mvpp2: Add GoP and NetC support for port 0 (SFI)
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:02 +02:00
Stefan Roese
31aa1e3815 net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:43:42 +02:00
Stefan Roese
9acb7da14e net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII
Read the "phy-speed" DT property to differentiate between 1 and 2.5GB
SGMII operations. Please note that its unclear right now, if this
DT property will be accepted in mainline Linux. If not, we need to
revisit this code and change it to use the accepted property.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:43:20 +02:00
Stefan Roese
66b11ccbb6 net: mvpp2: Restructure probe / init functions
This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:59 +02:00
Stefan Roese
ff572c6d53 net: mvpp2: Add RX and TX FIFO configuration for PPv2.2
This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
driver. The RX FIFO packet data size is changed to the recommended
FIFO sizes. The TX FIFO configuration is newly added.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:39 +02:00
Stefan Roese
c9607c9325 net: mvpp2: Handle eth device naming in multi-CP case correctly
Currently, the naming of the ethernet ports is not handled correctly in
the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP
also instantiates an ethernet controller with the same device ID's.
This patch now takes this into account and adds the required base-id
so that the slave-CP ethernet devices will be named "mvpp2-3 ...".

This patch also updates my Copyright notice to include 2017 as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:33 +02:00
Stefan Roese
e7935c4770 net: mvpp2: Enable compilation for Armada 7K/8K platforms
Since Armada 7K/8K is also equipped with a newer version of the MVPP2
ethernet controller, lets enable compilation of this driver for these
platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:20 +02:00
Stefan Roese
30edc374ea net: mvpp2.c: Clear all buffer / descriptor areas before usage
This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:16 +02:00
Stefan Roese
1fabbd074e net: mvpp2: Move probe function from MISC to ETH DM driver
This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_register().

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:11 +02:00
Stefan Roese
0a61e9ad1c net: mvpp2: Add MDIO support for PPv2.2
In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver,
currently only supporting the 32bit platforms (Armada 37x). This patch
now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF
can be used as well on these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:05 +02:00
Thomas Petazzoni
a83a6418a2 net: mvpp2: finally add the PPv2.2 compatible string
Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:01 +02:00
Thomas Petazzoni
09b3f948dc net: mvpp2: adapt rxq distribution to PPv2.2
In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.

In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from the range of 32 RXQs available for each port. So port 0 must
use RXQs in the range 0->31, port 1 in the range 32->63, etc.

This commit adapts the mvpp2 to this difference between PPv2.1 and
PPv2.2:

- The constant definition MVPP2_MAX_RXQ is replaced by a new field
  'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of
  RXQs per port. This field is initialized during ->probe() depending
  on the IP version.

- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total
  number of RXQs by multiplying the number of ports by the maximum of
  RXQs per port. This was anyway used in only one place.

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted
  to cope with the different allocation strategy between PPv2.1 and
  PPv2.2. Due to this change, the 'next_first_rxq' argument of this
  function is no longer needed and is removed.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:30 +02:00
Thomas Petazzoni
bc0bbf41b1 net: mvpp2: rework RXQ interrupt group initialization for PPv2.2
This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:25 +02:00
Thomas Petazzoni
cdf77799a3 net: mvpp2: add AXI bridge initialization for PPv2.2
The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:22 +02:00
Thomas Petazzoni
7c7311f1a2 net: mvpp2: handle misc PPv2.1/PPv2.2 differences
This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).

Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot
version of this patch does not remove this function but simply adds the
check for MVPP21 before the mvpp2_port_fc_adv_enable() call.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:17 +02:00
Thomas Petazzoni
26a5278c9e net: mvpp2: handle register mapping and access for PPv2.2
This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.

Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:

- On PPv2.1, we had a first area for the common registers, and then one
  area per port.

- On PPv2.2, we have a first area for the common registers, and a
  second area for all the per-ports registers.

In addition, on PPv2.2, the area for the common registers is split into
so-called "address spaces" of 64 KB each. They allow to access the same
registers, but from different CPUs. Hence the introduction of cpu_base[]
in 'struct mvpp2', and the modification of the mvpp2_write() and
mvpp2_read() register accessors. For PPv2.1, the compatibility is
preserved by using an "address space" size of 0.

Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the
code, macros and variables introduced in the Linux patch version for this.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:11 +02:00
Thomas Petazzoni
80350f55cf net: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2
In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:07 +02:00
Thomas Petazzoni
b8c8e6ffac net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2
This commit modifies the mvpp2_defaults_set() function to not do the
loopback and FIFO threshold initialization, which are not needed for
PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:03 +02:00
Thomas Petazzoni
8f3e4c3800 net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2
The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:59 +02:00
Thomas Petazzoni
c8feeb2b93 net: mvpp2: adjust the allocation/free of BM pools for PPv2.2
This commit adjusts the allocation and freeing of BM pools to support
PPv2.2. This involves:

- Checking that the number of buffer pointers is a multiple of 16, as
  required by the hardware.

- Adjusting the size of the DMA coherent area allocated for buffer
  pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per
  buffer, as opposed to 2 pointers of 32-bits per buffer in
  PPv2.1. The size in bytes is now stored in a new field of the
  mvpp2_bm_pool structure.

- On PPv2.2, getting the physical and virtual address of each buffer
  requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order
  bits of those addresses. A new utility function
  mvpp2_bm_bufs_get_addrs() is introduced to handle this.

- On PPv2.2, releasing a buffer requires writing the high order 32 bits
  of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no
  longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:54 +02:00
Thomas Petazzoni
f50a0118d1 net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors
This commit adds the definition of the PPv2.2 HW descriptors, adjusts
the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts
the accessors to work on both PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:49 +02:00
Thomas Petazzoni
9a6db0bb06 net: mvpp2: introduce an intermediate union for the TX/RX descriptors
Since the format of the HW descriptors is different between PPv2.1 and
PPv2.2, this commit introduces an intermediate union, with for now
only the PPv2.1 descriptors. The bulk of the driver code only
manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the
descriptors can only be accessed and modified through the accessor
functions. A follow-up commit will add the descriptor definitions for
PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:44 +02:00
Thomas Petazzoni
16a9898d80 net: mvpp2: add hw_version field in "struct mvpp2"
In preparation to the introduction for the support of PPv2.2 in the
mvpp2 driver, this commit adds a hw_version field to the struct
mvpp2, and uses the .data field of the DT match table to fill it in.

Having the MVPP21 and MVPP22 definitions available will allow to start
adding the necessary conditional code to support PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:39 +02:00
Thomas Petazzoni
cfa414aefd net: mvpp2: add and use accessors for TX/RX descriptors
The PPv2.2 IP has a different TX and RX descriptor layout compared to
PPv2.1. In order to prepare for the introduction of PPv2.2 support in
mvpp2, this commit adds accessors for the different fields of the TX
and RX descriptors, and changes the code to use them.

For now, the mvpp2_port argument passed to the accessors is not used,
but it will be used in follow-up to update the descriptor according to
the version of the IP being used.

Apart from the mechanical changes to use the newly introduced
accessors, a few other changes, needed to use the accessors, are made:

- The mvpp2_txq_inc_put() function now takes a mvpp2_port as first
  argument, as it is needed to use the accessors.

- Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first
  argument, for the same reason.

- In mvpp2_rx_error(), instead of accessing the RX descriptor in each
  case of the switch, we introduce a local variable to store the
  packet size.

- Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie"
  variable to store the RX descriptor cookie, rather than accessing
  it from the descriptor each time.

- In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the
  packet size from the TX descriptor, we use the actual value
  available in the function, which is used to set the TX descriptor
  packet size a few lines before.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:34 +02:00
Thomas Petazzoni
cd9ee19226 net: mvpp2: store physical address of buffer in rx_desc->buf_cookie
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:30 +02:00
Thomas Petazzoni
15f4df3091 net: mvpp2: remove support for buffer header
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:23 +02:00
Thomas Petazzoni
4dae32e676 net: mvpp2: use "dma" instead of "phys" where appropriate
As indicated by Russell King, the mvpp2 driver currently uses a lot
"phys" or "phys_addr" to store what really is a DMA address. This commit
clarifies this by using "dma" or "dma_addr" where appropriate.

This is especially important as we are going to introduce more changes
where the distinction between physical address and DMA address will be
key.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:18 +02:00
Stefan Roese
a7c28ff184 net: mvpp2: enable building on 64-bit platforms (more U-Boot specific)
Some more U-Boot specific 64bit support changes, mostly changing u32
to unsigned long.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:14 +02:00
Thomas Petazzoni
d1d075a558 net: mvpp2: enable building on 64-bit platforms
The mvpp2 is going to be extended to support the Marvell Armada 7K/8K
platform, which is ARM64. As a preparation to this work, this commit
enables building the mvpp2 driver on ARM64, by:

 - Adjusting the Kconfig dependency

 - Fixing the types used in the driver so that they are 32/64-bits
   compliant. We use dma_addr_t for DMA addresses, and unsigned long
   for virtual addresses.

It is worth mentioning that after this commit, the driver is for now
still only used on 32-bits platforms, and will only work on 32-bits
platforms.

Changed by Stefan for U-Boot:
Removed the Kconfig change as it does not apply to U-Boot this way.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:09 +02:00
Thomas Petazzoni
c0abc761b1 net: mvpp2: simplify MVPP2_PRS_RI_* definitions
Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which
doesn't compile nicely on 64-bit. Moreover, those definitions are in
fact unneeded, since they are always used in combination with a bit
mask that ensures only the appropriate bits are modified.

Therefore, such definitions should just be set to 0x0. In addition, as
suggested by Russell King, we change the _MASK definitions to also use
the BIT() macro so that it is clear they are related to the values
defined afterwards.

For example:

 #define MVPP2_PRS_RI_L2_CAST_MASK              0x600
 #define MVPP2_PRS_RI_L2_UCAST                  ~(BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_MCAST                  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                  BIT(10)

becomes

 #define MVPP2_PRS_RI_L2_CAST_MASK              (BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_UCAST                  0x0
 #define MVPP2_PRS_RI_L2_MCAST                  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                  BIT(10)

Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and
MVPP2_PRS_RI_L2_BCAST) are always applied with
MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for
MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)).

It fixes the following warnings when building the driver on a 64-bit
platform (which is not possible as of this commit, but will be enabled
in a follow-up commit):

drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’:
drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow]
 #define MVPP2_PRS_RI_L2_UCAST   ~(BIT(9) | BIT(10))
                                  ^
drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro ‘MVPP2_PRS_RI_L2_UCAST’
     mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:02 +02:00
Thomas Petazzoni
6b28f42a51 net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:39:59 +02:00
Thomas Petazzoni
dbeb6de136 net: mvpp2: remove unused register definitions
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:39:55 +02:00
Thomas Petazzoni
f1060f0dd0 net: mvpp2: simplify mvpp2_bm_bufs_add()
The mvpp2_bm_bufs_add() currently creates a fake cookie by calling
mvpp2_bm_cookie_pool_set(), just to be able to call
mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract
the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID.

Instead of doing this convoluted thing, just call mvpp2_bm_pool_put()
directly, since we have the BM pool ID.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:39:49 +02:00
Stefan Roese
f811e04ad7 net: mvpp2: Round up top tx buffer boundaries for dcache ops
check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.

This gets rid of the warnings:
CACHE: Misaligned operation at range ...

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:39:44 +02:00
Konstantin Porotchkin
3fbeb52bda mvebu: neta: a37xx: Add fixed link support to neta driver
Add support for fixed link to NETA driver.
This feature requreed for proper support of SFP modules
and onboard connected devices like Ethernet switches

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29 07:38:09 +02:00