net: phy: Don't limit phy addresses by default

Some boards expect to find more than one phy while other boards are old
and need to be limited to a specific phy address. Only limit the phy
address for boards that opt in.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Joe Hershberger 2018-03-30 11:52:16 -05:00
parent 86271b3f29
commit 16879cd25a
16 changed files with 23 additions and 0 deletions

View file

@ -44,6 +44,7 @@ CONFIG_SYS_OMAP24_I2C_SPEED=1000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y

View file

@ -38,6 +38,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y

View file

@ -39,6 +39,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y

View file

@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y

View file

@ -37,6 +37,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y

View file

@ -39,6 +39,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y

View file

@ -39,6 +39,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y

View file

@ -36,6 +36,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=31
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y

View file

@ -41,6 +41,7 @@ CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y

View file

@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y

View file

@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y

View file

@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y

View file

@ -33,6 +33,7 @@ CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_NETDEVICES=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y

View file

@ -36,6 +36,7 @@ CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LPC32XX_SSP=y

View file

@ -44,6 +44,7 @@ CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y

View file

@ -13,12 +13,20 @@ menuconfig PHYLIB
if PHYLIB
config PHY_ADDR_ENABLE
bool "Limit phy address"
default y if ARCH_SUNXI
help
Select this if you want to control which phy address is used
if PHY_ADDR_ENABLE
config PHY_ADDR
int "PHY address"
default 1 if ARCH_SUNXI
default 0
help
The address of PHY on MII bus. Usually in range of 0 to 31.
endif
config B53_SWITCH
bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."