mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh
This commit is contained in:
Tom Rini
commit
9c486e7cb0
126 changed files with 37442 additions and 1451 deletions
10
arch/arm/dts/r8a7790-lager-u-boot.dts
Normal file
10
arch/arm/dts/r8a7790-lager-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Lager board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7790-lager.dts"
|
||||
#include "r8a7790-u-boot.dtsi"
|
||||
856
arch/arm/dts/r8a7790-lager.dts
Normal file
856
arch/arm/dts/r8a7790-lager.dts
Normal file
|
|
@ -0,0 +1,856 @@
|
|||
/*
|
||||
* Device Tree Source for the Lager board
|
||||
*
|
||||
* Copyright (C) 2013-2014 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014 Cogent Embedded, Inc.
|
||||
* Copyright (C) 2015-2016 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 1: AK4643
|
||||
* 2: CN22
|
||||
* 3: ADV7511
|
||||
*
|
||||
* This command is required when Playback/Capture
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
* amixer set "DVC Out" 100%
|
||||
* amixer set "DVC In" 100%
|
||||
*
|
||||
* You can use Mute
|
||||
*
|
||||
* amixer set "DVC Out Mute" on
|
||||
* amixer set "DVC In Mute" on
|
||||
*
|
||||
* You can use Volume Ramp
|
||||
*
|
||||
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
|
||||
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
|
||||
* amixer set "DVC Out Ramp" on
|
||||
* aplay xxx.wav &
|
||||
* amixer set "DVC Out" 80% // Volume Down
|
||||
* amixer set "DVC Out" 100% // Volume Up
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7790.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Lager";
|
||||
compatible = "renesas,lager", "renesas,r8a7790";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scifa1;
|
||||
i2c8 = &gpioi2c1;
|
||||
i2c10 = &i2cexio0;
|
||||
i2c11 = &i2cexio1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
memory@140000000 {
|
||||
device_type = "memory";
|
||||
reg = <1 0x40000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
lbsc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
one {
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
two {
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
three {
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
four {
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led6 {
|
||||
gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led7 {
|
||||
gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led8 {
|
||||
gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
fixedregulator3v3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator-vcc-sdhi2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator-vccq-sdhi2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcodec>;
|
||||
simple-audio-card,frame-master = <&sndcodec>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&audio_clock>;
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
x13_clk: x13-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
gpioi2c1: i2c-8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "i2c-gpio";
|
||||
status = "disabled";
|
||||
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
|
||||
&gpio1 16 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <5>;
|
||||
};
|
||||
|
||||
/*
|
||||
* IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
|
||||
* We use the I2C demuxer, so the desired IP core can be selected at runtime
|
||||
* depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
|
||||
* Note: For testing the I2C slave feature, it is convenient to connect this
|
||||
* bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
|
||||
* instantiate the slave device at runtime according to the documentation.
|
||||
* You can then communicate with the slave via IIC3.
|
||||
*
|
||||
* IIC0/I2C0 does not appear to support fallback to GPIO.
|
||||
*/
|
||||
i2cexio0: i2c-10 {
|
||||
compatible = "i2c-demux-pinctrl";
|
||||
i2c-parent = <&iic0>, <&i2c0>;
|
||||
i2c-bus-name = "i2c-exio0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
/*
|
||||
* IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
|
||||
* This is similar to the arangement described for i2cexio0 (above)
|
||||
* with a fallback to GPIO also provided.
|
||||
*/
|
||||
i2cexio1: i2c-11 {
|
||||
compatible = "i2c-demux-pinctrl";
|
||||
i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
|
||||
i2c-bus-name = "i2c-exio1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
|
||||
"dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
scifa1_pins: scifa1 {
|
||||
groups = "scifa1_data";
|
||||
function = "scifa1";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
mmc1_pins: mmc1 {
|
||||
groups = "mmc1_data8", "mmc1_ctrl";
|
||||
function = "mmc1";
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
msiof1_pins: msiof1 {
|
||||
groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
|
||||
"msiof1_tx";
|
||||
function = "msiof1";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
iic0_pins: iic0 {
|
||||
groups = "iic0";
|
||||
function = "iic0";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
iic1_pins: iic1 {
|
||||
groups = "iic1";
|
||||
function = "iic1";
|
||||
};
|
||||
|
||||
iic2_pins: iic2 {
|
||||
groups = "iic2";
|
||||
function = "iic2";
|
||||
};
|
||||
|
||||
iic3_pins: iic3 {
|
||||
groups = "iic3";
|
||||
function = "iic3";
|
||||
};
|
||||
|
||||
hsusb_pins: hsusb {
|
||||
groups = "usb0_ovc_vbus";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
usb2_pins: usb2 {
|
||||
groups = "usb2";
|
||||
function = "usb2";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
vin1_pins: vin1 {
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmcif1 {
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&fixedregulator3v3>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash: flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scifa1 {
|
||||
pinctrl-0 = <&scifa1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&msiof1 {
|
||||
pinctrl-0 = <&msiof1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@0 {
|
||||
compatible = "renesas,r2a11302ft";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <6000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_dvfs>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "i2c-exio0";
|
||||
};
|
||||
|
||||
&iic0 {
|
||||
pinctrl-0 = <&iic0_pins>;
|
||||
pinctrl-names = "i2c-exio0";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "i2c-exio1";
|
||||
};
|
||||
|
||||
&iic1 {
|
||||
pinctrl-0 = <&iic1_pins>;
|
||||
pinctrl-names = "i2c-exio1";
|
||||
};
|
||||
|
||||
&iic2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&iic2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin1ep0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
adv7612_out: endpoint {
|
||||
remote-endpoint = <&vin0ep2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iic3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&iic3_pins>;
|
||||
status = "okay";
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dlg,da9063";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
|
||||
rtc {
|
||||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_dvfs: regulator@68 {
|
||||
compatible = "dlg,da9210";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&xhci {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hsusb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* HDMI video input */
|
||||
&vin0 {
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
vin0ep2: endpoint {
|
||||
remote-endpoint = <&adv7612_out>;
|
||||
bus-width = <24>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
data-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin1 {
|
||||
pinctrl-0 = <&vin1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin1ep0: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
10
arch/arm/dts/r8a7790-stout-u-boot.dts
Normal file
10
arch/arm/dts/r8a7790-stout-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Stout board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7790-stout.dts"
|
||||
#include "r8a7790-u-boot.dtsi"
|
||||
54
arch/arm/dts/r8a7790-stout.dts
Normal file
54
arch/arm/dts/r8a7790-stout.dts
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Device Tree Source for the Stout board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7790.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Stout";
|
||||
compatible = "renesas,stout", "renesas,r8a7790";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
13
arch/arm/dts/r8a7790-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7790-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7790 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&usb_extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
1665
arch/arm/dts/r8a7790.dtsi
Normal file
1665
arch/arm/dts/r8a7790.dtsi
Normal file
File diff suppressed because it is too large
Load diff
10
arch/arm/dts/r8a7791-koelsch-u-boot.dts
Normal file
10
arch/arm/dts/r8a7791-koelsch-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Koelsch board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7791-koelsch.dts"
|
||||
#include "r8a7791-u-boot.dtsi"
|
||||
840
arch/arm/dts/r8a7791-koelsch.dts
Normal file
840
arch/arm/dts/r8a7791-koelsch.dts
Normal file
|
|
@ -0,0 +1,840 @@
|
|||
/*
|
||||
* Device Tree Source for the Koelsch board
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
* Copyright (C) 2013-2014 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014 Cogent Embedded, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 1: AK4643
|
||||
* 2: CN22
|
||||
* 3: ADV7511
|
||||
*
|
||||
* This command is required when Playback/Capture
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
* amixer set "DVC Out" 100%
|
||||
* amixer set "DVC In" 100%
|
||||
*
|
||||
* You can use Mute
|
||||
*
|
||||
* amixer set "DVC Out Mute" on
|
||||
* amixer set "DVC In Mute" on
|
||||
*
|
||||
* You can use Volume Ramp
|
||||
*
|
||||
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
|
||||
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
|
||||
* amixer set "DVC Out Ramp" on
|
||||
* aplay xxx.wav &
|
||||
* amixer set "DVC Out" 80% // Volume Down
|
||||
* amixer set "DVC Out" 100% // Volume Up
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7791.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Koelsch";
|
||||
compatible = "renesas,koelsch", "renesas,r8a7791";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif1;
|
||||
i2c9 = &gpioi2c1;
|
||||
i2c12 = &i2cexio1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
memory@200000000 {
|
||||
device_type = "memory";
|
||||
reg = <2 0x00000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
lbsc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-2 {
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-3 {
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-4 {
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-a {
|
||||
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_A>;
|
||||
label = "SW30";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-b {
|
||||
gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_B>;
|
||||
label = "SW31";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-c {
|
||||
gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_C>;
|
||||
label = "SW32";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-d {
|
||||
gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_D>;
|
||||
label = "SW33";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-e {
|
||||
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_E>;
|
||||
label = "SW34";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-f {
|
||||
gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_F>;
|
||||
label = "SW35";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-g {
|
||||
gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_G>;
|
||||
label = "SW36";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led6 {
|
||||
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED6";
|
||||
};
|
||||
led7 {
|
||||
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED7";
|
||||
};
|
||||
led8 {
|
||||
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED8";
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator-vcc-sdhi2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator-vccq-sdhi2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcodec>;
|
||||
simple-audio-card,frame-master = <&sndcodec>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&audio_clock>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x13_clk: x13-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
gpioi2c1: i2c-9 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "i2c-gpio";
|
||||
status = "disabled";
|
||||
gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
|
||||
&gpio7 15 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <5>;
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
|
||||
* A fallback to GPIO is provided.
|
||||
*/
|
||||
i2cexio1: i2c-12 {
|
||||
compatible = "i2c-demux-pinctrl";
|
||||
i2c-parent = <&i2c1>, <&gpioi2c1>;
|
||||
i2c-bus-name = "i2c-exio1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "lvds.0",
|
||||
"dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif1_pins: scif1 {
|
||||
groups = "scif1_data_d";
|
||||
function = "scif1";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
msiof0_pins: msiof0 {
|
||||
groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
|
||||
"msiof0_tx";
|
||||
function = "msiof0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
vin1_pins: vin1 {
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif1 {
|
||||
pinctrl-0 = <&scif1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash: flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "user";
|
||||
reg = <0x00080000 0x00580000>;
|
||||
read-only;
|
||||
};
|
||||
partition@600000 {
|
||||
label = "flash";
|
||||
reg = <0x00600000 0x03a00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&msiof0 {
|
||||
pinctrl-0 = <&msiof0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@0 {
|
||||
compatible = "renesas,r2a11302ft";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <6000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "i2c-exio1";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin1ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cec_clock: cec-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&cec_clock>;
|
||||
clock-names = "cec";
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
adv7612_out: endpoint {
|
||||
remote-endpoint = <&vin0ep2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "renesas,24c02", "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dlg,da9063";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
|
||||
rtc {
|
||||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_dvfs: regulator@68 {
|
||||
compatible = "dlg,da9210";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_dvfs>;
|
||||
};
|
||||
|
||||
/* HDMI video input */
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep2: endpoint {
|
||||
remote-endpoint = <&adv7612_out>;
|
||||
bus-width = <24>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
data-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin1ep: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
10
arch/arm/dts/r8a7791-porter-u-boot.dts
Normal file
10
arch/arm/dts/r8a7791-porter-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Porter board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7791-porter.dts"
|
||||
#include "r8a7791-u-boot.dtsi"
|
||||
452
arch/arm/dts/r8a7791-porter.dts
Normal file
452
arch/arm/dts/r8a7791-porter.dts
Normal file
|
|
@ -0,0 +1,452 @@
|
|||
/*
|
||||
* Device Tree Source for the Porter board
|
||||
*
|
||||
* Copyright (C) 2015 Cogent Embedded, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4642
|
||||
*
|
||||
* JP3: 2-1: AK4642
|
||||
* 2-3: ADV7511
|
||||
*
|
||||
* This command is required before playback/capture:
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7791.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Porter";
|
||||
compatible = "renesas,porter", "renesas,r8a7791";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
memory@200000000 {
|
||||
device_type = "memory";
|
||||
reg = <2 0x00000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator-vcc-sdhi2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator-vccq-sdhi2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x3_clk: x3-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
x16_clk: x16-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x14_clk: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&soundcodec>;
|
||||
simple-audio-card,frame-master = <&soundcodec>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
soundcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4642>;
|
||||
clocks = <&x14_clk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
groups = "can0_data";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
ssi_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
audio_clk_pins: audio_clk {
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader_prg";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user_prg";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash_fs";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ak4642: codec@12 {
|
||||
compatible = "asahi-kasei,ak4642";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin0ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can0 {
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
||||
<&x3_clk>, <&x16_clk>;
|
||||
clock-names = "du.0", "du.1", "lvds.0",
|
||||
"dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0>;
|
||||
capture = <&ssi1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
13
arch/arm/dts/r8a7791-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7791-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7791 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&usb_extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
1665
arch/arm/dts/r8a7791.dtsi
Normal file
1665
arch/arm/dts/r8a7791.dtsi
Normal file
File diff suppressed because it is too large
Load diff
10
arch/arm/dts/r8a7792-blanche-u-boot.dts
Normal file
10
arch/arm/dts/r8a7792-blanche-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Blanche board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7792-blanche.dts"
|
||||
#include "r8a7792-u-boot.dtsi"
|
||||
327
arch/arm/dts/r8a7792-blanche.dts
Normal file
327
arch/arm/dts/r8a7792-blanche.dts
Normal file
|
|
@ -0,0 +1,327 @@
|
|||
/*
|
||||
* Device Tree Source for the Blanche board
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7792.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Blanche";
|
||||
compatible = "renesas,blanche", "renesas,r8a7792";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
d3_3v: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ethernet@18000000 {
|
||||
compatible = "smsc,lan89218", "smsc,lan9115";
|
||||
reg = <0 0x18000000 0 0x100>;
|
||||
phy-mode = "mii";
|
||||
interrupt-parent = <&irqc>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
|
||||
smsc,irq-push-pull;
|
||||
reg-io-width = <4>;
|
||||
vddvario-supply = <&d3_3v>;
|
||||
vdd33a-supply = <&d3_3v>;
|
||||
|
||||
pinctrl-0 = <&lan89218_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb1>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x1_clk: x1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x2_clk: x2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <65000000>;
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-1 {
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-2 {
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-3 {
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-4 {
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-a {
|
||||
linux,code = <KEY_A>;
|
||||
label = "SW24";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
key-b {
|
||||
linux,code = <KEY_B>;
|
||||
label = "SW25";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led17 {
|
||||
gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led18 {
|
||||
gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led19 {
|
||||
gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led20 {
|
||||
gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&can_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif3_pins: scif3 {
|
||||
groups = "scif3_data";
|
||||
function = "scif3";
|
||||
};
|
||||
|
||||
lan89218_pins: lan89218 {
|
||||
intc {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
lbsc {
|
||||
groups = "lbsc_ex_cs0";
|
||||
function = "lbsc";
|
||||
};
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
groups = "can0_data", "can_clk";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
sdhi0_pins: sdhi0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
du0_pins: du0 {
|
||||
groups = "du0_rgb888", "du0_sync", "du0_disp";
|
||||
function = "du0";
|
||||
};
|
||||
|
||||
du1_pins: du1 {
|
||||
groups = "du1_rgb666", "du1_sync", "du1_disp";
|
||||
function = "du1";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif3 {
|
||||
pinctrl-0 = <&scif3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can0 {
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&irqc>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du0_pins &du1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
9
arch/arm/dts/r8a7792-u-boot.dtsi
Normal file
9
arch/arm/dts/r8a7792-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7792 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
857
arch/arm/dts/r8a7792.dtsi
Normal file
857
arch/arm/dts/r8a7792.dtsi
Normal file
|
|
@ -0,0 +1,857 @@
|
|||
/*
|
||||
* Device Tree Source for the r8a7792 SoC
|
||||
*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7792-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7792";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
spi0 = &qspi;
|
||||
spi1 = &msiof0;
|
||||
spi2 = &msiof1;
|
||||
vin0 = &vin0;
|
||||
vin1 = &vin1;
|
||||
vin2 = &vin2;
|
||||
vin3 = &vin3;
|
||||
vin4 = &vin4;
|
||||
vin5 = &vin5;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "renesas,apmu";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
|
||||
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
|
||||
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
L2_CA15: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
power-domains = <&sysc R8A7792_PD_CA15_SCU>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
apmu@e6152000 {
|
||||
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
|
||||
reg = <0 0xe6152000 0 0x188>;
|
||||
cpus = <&cpu0 &cpu1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1001000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xf1001000 0 0x1000>,
|
||||
<0 0xf1002000 0 0x2000>,
|
||||
<0 0xf1004000 0 0x2000>,
|
||||
<0 0xf1006000 0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
irqc: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,irqc-r8a7792", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a7792-rst";
|
||||
reg = <0 0xe6160000 0 0x0100>;
|
||||
};
|
||||
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7792-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7792";
|
||||
reg = <0 0xe6060000 0 0x144>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6050000 0 0x50>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 0 29>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 912>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 912>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6051000 0 0x50>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 23>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 911>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 911>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 32>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 910>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 910>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 28>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 909>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 909>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 908>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 908>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 907>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055100 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055100 0 0x50>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 192 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 905>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055200 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055200 0 0x50>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 224 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 904>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 904>;
|
||||
};
|
||||
|
||||
gpio8: gpio@e6055300 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055300 0 0x50>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 256 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 921>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 921>;
|
||||
};
|
||||
|
||||
gpio9: gpio@e6055400 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055400 0 0x50>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 288 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 919>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 919>;
|
||||
};
|
||||
|
||||
gpio10: gpio@e6055500 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055500 0 0x50>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 320 32>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 914>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
};
|
||||
|
||||
gpio11: gpio@e6055600 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055600 0 0x50>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 352 30>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 913>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 913>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a7792",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x20000>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e6720000 {
|
||||
compatible = "renesas,dmac-r8a7792",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6720000 0 0x20000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e60000 0 64>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
||||
<&dmac1 0x29>, <&dmac1 0x2a>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 721>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif1: serial@e6e68000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e68000 0 64>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 720>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
||||
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 720>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif2: serial@e6e58000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e58000 0 64>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 719>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
||||
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 719>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif3: serial@e6ea8000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6ea8000 0 64>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 718>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
||||
<&dmac1 0x2f>, <&dmac1 0x30>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 718>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@e62c0000 {
|
||||
compatible = "renesas,hscif-r8a7792",
|
||||
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||
reg = <0 0xe62c0000 0 96>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 717>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
||||
<&dmac1 0x39>, <&dmac1 0x3a>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 717>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif1: serial@e62c8000 {
|
||||
compatible = "renesas,hscif-r8a7792",
|
||||
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||
reg = <0 0xe62c8000 0 96>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 716>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
||||
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 716>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
icram0: sram@e63a0000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0 0xe63a0000 0 0x12000>;
|
||||
};
|
||||
|
||||
icram1: sram@e63c0000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0 0xe63c0000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xe63c0000 0x1000>;
|
||||
|
||||
smp-sram@0 {
|
||||
compatible = "renesas,smp-sram";
|
||||
reg = <0 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7792";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
||||
<&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
jpu: jpeg-codec@fe980000 {
|
||||
compatible = "renesas,jpu-r8a7792",
|
||||
"renesas,rcar-gen2-jpu";
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 106>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 106>;
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a7792",
|
||||
"renesas,etheravb-rcar-gen2";
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I2C doesn't need pinmux */
|
||||
i2c0: i2c@e6508000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 931>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 931>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@e6518000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 930>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 930>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@e6530000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 929>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 929>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@e6540000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 928>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 928>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@e6520000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 927>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 927>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@e6528000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 925>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 925>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi: spi@e6b10000 {
|
||||
compatible = "renesas,qspi-r8a7792", "renesas,qspi";
|
||||
reg = <0 0xe6b10000 0 0x2c>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
|
||||
<&dmac1 0x17>, <&dmac1 0x18>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof0: spi@e6e20000 {
|
||||
compatible = "renesas,msiof-r8a7792",
|
||||
"renesas,rcar-gen2-msiof";
|
||||
reg = <0 0xe6e20000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 000>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
|
||||
<&dmac1 0x51>, <&dmac1 0x52>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof1: spi@e6e10000 {
|
||||
compatible = "renesas,msiof-r8a7792",
|
||||
"renesas,rcar-gen2-msiof";
|
||||
reg = <0 0xe6e10000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 208>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
|
||||
<&dmac1 0x55>, <&dmac1 0x56>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 208>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7792";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
reg-names = "du";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb0: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_rgb1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 811>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 811>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 810>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 810>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 809>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 809>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 808>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin4: video@e6ef4000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 805>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 805>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin5: video@e6ef5000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 804>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 804>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vsp@fe928000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 131>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 131>;
|
||||
};
|
||||
|
||||
vsp@fe930000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 128>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 128>;
|
||||
};
|
||||
|
||||
vsp@fe938000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 127>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 127>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7792-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-names = "extal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* External root clock */
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
10
arch/arm/dts/r8a7793-gose-u-boot.dts
Normal file
10
arch/arm/dts/r8a7793-gose-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Gose board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7793-gose.dts"
|
||||
#include "r8a7793-u-boot.dtsi"
|
||||
727
arch/arm/dts/r8a7793-gose.dts
Normal file
727
arch/arm/dts/r8a7793-gose.dts
Normal file
|
|
@ -0,0 +1,727 @@
|
|||
/*
|
||||
* Device Tree Source for the Gose board
|
||||
*
|
||||
* Copyright (C) 2014-2015 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 1: AK4643
|
||||
* 2: CN22
|
||||
* 3: ADV7511
|
||||
*
|
||||
* This command is required when Playback/Capture
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
* amixer set "DVC Out" 100%
|
||||
* amixer set "DVC In" 100%
|
||||
*
|
||||
* You can use Mute
|
||||
*
|
||||
* amixer set "DVC Out Mute" on
|
||||
* amixer set "DVC In Mute" on
|
||||
*
|
||||
* You can use Volume Ramp
|
||||
*
|
||||
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
|
||||
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
|
||||
* amixer set "DVC Out Ramp" on
|
||||
* aplay xxx.wav &
|
||||
* amixer set "DVC Out" 80% // Volume Down
|
||||
* amixer set "DVC Out" 100% // Volume Up
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7793.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Gose";
|
||||
compatible = "renesas,gose", "renesas,r8a7793";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-2 {
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-3 {
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-4 {
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-a {
|
||||
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_A>;
|
||||
label = "SW30";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-b {
|
||||
gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_B>;
|
||||
label = "SW31";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-c {
|
||||
gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_C>;
|
||||
label = "SW32";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-d {
|
||||
gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_D>;
|
||||
label = "SW33";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-e {
|
||||
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_E>;
|
||||
label = "SW34";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-f {
|
||||
gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_F>;
|
||||
label = "SW35";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-g {
|
||||
gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_G>;
|
||||
label = "SW36";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led6 {
|
||||
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED6";
|
||||
};
|
||||
led7 {
|
||||
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED7";
|
||||
};
|
||||
led8 {
|
||||
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED8";
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator-vcc-sdhi2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator-vccq-sdhi2 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcodec>;
|
||||
simple-audio-card,frame-master = <&sndcodec>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&audio_clock>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
composite-in {
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
port {
|
||||
composite_con_in: endpoint {
|
||||
remote-endpoint = <&adv7180_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x13_clk: x13-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "lvds.0",
|
||||
"dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif1_pins: scif1 {
|
||||
groups = "scif1_data_d";
|
||||
function = "scif1";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
vin1_pins: vin1 {
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif1 {
|
||||
pinctrl-0 = <&scif1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180cp";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7180_in: endpoint {
|
||||
remote-endpoint = <&composite_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
adv7180_out: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin1ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
default-input = <0>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
adv7612_out: endpoint {
|
||||
remote-endpoint = <&vin0ep2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "renesas,r1ex24002", "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dlg,da9063";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
|
||||
rtc {
|
||||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
/* HDMI video input */
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep2: endpoint {
|
||||
remote-endpoint = <&adv7612_out>;
|
||||
bus-width = <24>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
data-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin1 {
|
||||
pinctrl-0 = <&vin1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin1ep: endpoint {
|
||||
remote-endpoint = <&adv7180_out>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
13
arch/arm/dts/r8a7793-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7793-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7793 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&usb_extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
1332
arch/arm/dts/r8a7793.dtsi
Normal file
1332
arch/arm/dts/r8a7793.dtsi
Normal file
File diff suppressed because it is too large
Load diff
10
arch/arm/dts/r8a7794-alt-u-boot.dts
Normal file
10
arch/arm/dts/r8a7794-alt-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Alt board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7794-alt.dts"
|
||||
#include "r8a7794-u-boot.dtsi"
|
||||
414
arch/arm/dts/r8a7794-alt.dts
Normal file
414
arch/arm/dts/r8a7794-alt.dts
Normal file
|
|
@ -0,0 +1,414 @@
|
|||
/*
|
||||
* Device Tree Source for the Alt board
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7794.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Alt";
|
||||
compatible = "renesas,alt", "renesas,r8a7794";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
i2c10 = &gpioi2c4;
|
||||
i2c12 = &i2cexio4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
d3_3v: regulator-d3-3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
lbsc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb1>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x13_clk: x13-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
gpioi2c4: i2c-10 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "i2c-gpio";
|
||||
status = "disabled";
|
||||
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
|
||||
&gpio4 8 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <5>;
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
|
||||
* A fallback to GPIO is provided.
|
||||
*/
|
||||
i2cexio4: i2c-14 {
|
||||
compatible = "i2c-demux-pinctrl";
|
||||
i2c-parent = <&i2c4>, <&gpioi2c4>;
|
||||
i2c-bus-name = "i2c-exio4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
du_pins: du {
|
||||
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
|
||||
function = "du1";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq8";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4 {
|
||||
groups = "i2c4";
|
||||
function = "i2c4";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
mmcif0_pins: mmcif0 {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmcif0 {
|
||||
pinctrl-0 = <&mmcif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&d3_3v>;
|
||||
vqmmc-supply = <&d3_3v>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin0ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "i2c-exio4";
|
||||
};
|
||||
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "system";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "user";
|
||||
reg = <0x00080000 0x03f80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
10
arch/arm/dts/r8a7794-silk-u-boot.dts
Normal file
10
arch/arm/dts/r8a7794-silk-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Silk board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7794-silk.dts"
|
||||
#include "r8a7794-u-boot.dtsi"
|
||||
460
arch/arm/dts/r8a7794-silk.dts
Normal file
460
arch/arm/dts/r8a7794-silk.dts
Normal file
|
|
@ -0,0 +1,460 @@
|
|||
/*
|
||||
* Device Tree Source for the SILK board
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright (C) 2014-2015 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014-2015 Cogent Embedded, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4643
|
||||
*
|
||||
* SW1: 2-1: AK4643
|
||||
* 2-3: ADV7511
|
||||
*
|
||||
* This command is required before playback/capture:
|
||||
*
|
||||
* amixer set "LINEOUT Mixer DACL" on
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7794.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "SILK";
|
||||
compatible = "renesas,silk", "renesas,r8a7794";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
d3_3v: regulator-d3-3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb1>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x2_clk: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
x3_clk: x3-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x9_clk: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&soundcodec>;
|
||||
simple-audio-card,frame-master = <&soundcodec>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
soundcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4643>;
|
||||
clocks = <&x9_clk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <20000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
groups = "intc_irq8";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
mmcif0_pins: mmcif0 {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
};
|
||||
|
||||
qspi_pins: qspi {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
du0_pins: du0 {
|
||||
groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
|
||||
function = "du0";
|
||||
};
|
||||
|
||||
du1_pins: du1 {
|
||||
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
|
||||
function = "du1";
|
||||
};
|
||||
|
||||
ssi_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
audio_clk_pins: audio_clk {
|
||||
groups = "audio_clkc";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin0ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmcif0 {
|
||||
pinctrl-0 = <&mmcif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&d3_3v>;
|
||||
vqmmc-supply = <&d3_3v>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin0ep: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du0_pins &du1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&x2_clk>, <&x3_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0>;
|
||||
capture = <&ssi1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
13
arch/arm/dts/r8a7794-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7794-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7794 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&usb_extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
1347
arch/arm/dts/r8a7794.dtsi
Normal file
1347
arch/arm/dts/r8a7794.dtsi
Normal file
File diff suppressed because it is too large
Load diff
10
arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
Normal file
10
arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the ULCB board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7795-h3ulcb.dts"
|
||||
#include "r8a7795-u-boot.dtsi"
|
||||
|
|
@ -4,13 +4,9 @@
|
|||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7795.dtsi"
|
||||
#include "ulcb.dtsi"
|
||||
|
|
@ -40,3 +36,17 @@
|
|||
reg = <0x7 0x00000000 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 4>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
|
||||
};
|
||||
|
|
|
|||
10
arch/arm/dts/r8a7795-salvator-x-u-boot.dts
Normal file
10
arch/arm/dts/r8a7795-salvator-x-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Salvator-X board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7795-salvator-x.dts"
|
||||
#include "r8a7795-u-boot.dtsi"
|
||||
|
|
@ -3,13 +3,9 @@
|
|||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7795.dtsi"
|
||||
#include "salvator-x.dtsi"
|
||||
|
|
|
|||
13
arch/arm/dts/r8a7795-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7795-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7795 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -3,15 +3,15 @@
|
|||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7795-sysc.h>
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7795";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -129,7 +129,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
|
|
@ -137,7 +136,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -191,7 +189,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
|
|
@ -383,7 +380,6 @@
|
|||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -394,7 +390,6 @@
|
|||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
|
|
@ -696,6 +691,126 @@
|
|||
};
|
||||
};
|
||||
|
||||
drif00: rif@e6f40000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f40000 0 0x64>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 515>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 515>;
|
||||
renesas,bonding = <&drif01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif01: rif@e6f50000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f50000 0 0x64>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 514>;
|
||||
renesas,bonding = <&drif00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif10: rif@e6f60000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f60000 0 0x64>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 513>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 513>;
|
||||
renesas,bonding = <&drif11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif11: rif@e6f70000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f70000 0 0x64>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 512>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 512>;
|
||||
renesas,bonding = <&drif10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif20: rif@e6f80000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f80000 0 0x64>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 511>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 511>;
|
||||
renesas,bonding = <&drif21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif21: rif@e6f90000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f90000 0 0x64>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 510>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 510>;
|
||||
renesas,bonding = <&drif20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif30: rif@e6fa0000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fa0000 0 0x64>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 509>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 509>;
|
||||
renesas,bonding = <&drif31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif31: rif@e6fb0000 {
|
||||
compatible = "renesas,r8a7795-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fb0000 0 0x64>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 508>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 508>;
|
||||
renesas,bonding = <&drif30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@e6540000 {
|
||||
compatible = "renesas,hscif-r8a7795",
|
||||
"renesas,rcar-gen3-hscif",
|
||||
|
|
@ -781,6 +896,68 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof0: spi@e6e90000 {
|
||||
compatible = "renesas,msiof-r8a7795",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6e90000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 211>;
|
||||
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
||||
<&dmac2 0x41>, <&dmac2 0x40>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 211>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof1: spi@e6ea0000 {
|
||||
compatible = "renesas,msiof-r8a7795",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6ea0000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 210>;
|
||||
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
||||
<&dmac2 0x43>, <&dmac2 0x42>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 210>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof2: spi@e6c00000 {
|
||||
compatible = "renesas,msiof-r8a7795",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6c00000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 209>;
|
||||
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 209>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof3: spi@e6c10000 {
|
||||
compatible = "renesas,msiof-r8a7795",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6c10000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 208>;
|
||||
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 208>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a7795",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
|
|
@ -1272,7 +1449,8 @@
|
|||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a7795";
|
||||
compatible = "renesas,sata-r8a7795",
|
||||
"renesas,rcar-gen3-sata";
|
||||
reg = <0 0xee300000 0 0x200000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 815>;
|
||||
|
|
@ -1319,6 +1497,34 @@
|
|||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac2: dma-controller@e6460000 {
|
||||
compatible = "renesas,r8a7795-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe6460000 0 0x100>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 326>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 326>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac3: dma-controller@e6470000 {
|
||||
compatible = "renesas,r8a7795-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe6470000 0 0x100>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 329>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 329>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
|
|
@ -1397,6 +1603,18 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy3: usb-phy@ee0e0200 {
|
||||
compatible = "renesas,usb2-phy-r8a7795",
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
reg = <0 0xee0e0200 0 0x700>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@ee080100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
|
|
@ -1404,6 +1622,7 @@
|
|||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
|
|
@ -1416,6 +1635,7 @@
|
|||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci1>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 702>;
|
||||
status = "disabled";
|
||||
|
|
@ -1428,11 +1648,25 @@
|
|||
clocks = <&cpg CPG_MOD 701>;
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci2>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 701>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci3: usb@ee0e0100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee0e0100 0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci3>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
|
|
@ -1469,6 +1703,18 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci3: usb@ee0e0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee0e0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a7795",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
|
|
@ -1486,6 +1732,23 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb3: usb@e659c000 {
|
||||
compatible = "renesas,usbhs-r8a7795",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe659c000 0 0x100>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 705>;
|
||||
dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
|
||||
<&usb_dmac3 0>, <&usb_dmac3 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
renesas,buswait = <11>;
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 705>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0: pcie@fe000000 {
|
||||
compatible = "renesas,pcie-r8a7795",
|
||||
"renesas,pcie-rcar-gen3";
|
||||
|
|
@ -1540,6 +1803,46 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
imr-lx4@fe860000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe860000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 823>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VC>;
|
||||
resets = <&cpg 823>;
|
||||
};
|
||||
|
||||
imr-lx4@fe870000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe870000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 822>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VC>;
|
||||
resets = <&cpg 822>;
|
||||
};
|
||||
|
||||
imr-lx4@fe880000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe880000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 821>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VC>;
|
||||
resets = <&cpg 821>;
|
||||
};
|
||||
|
||||
imr-lx4@fe890000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe890000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 820>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VC>;
|
||||
resets = <&cpg 820>;
|
||||
};
|
||||
|
||||
vspbc: vsp@fe920000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe920000 0 0x8000>;
|
||||
|
|
@ -1760,6 +2063,7 @@
|
|||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7795";
|
||||
reg = <0 0xfeb00000 0 0x80000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
reg-names = "du", "lvds.0";
|
||||
|
|
@ -1773,6 +2077,7 @@
|
|||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
|
||||
vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
10
arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
Normal file
10
arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the ULCB board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7796-m3ulcb.dts"
|
||||
#include "r8a7796-u-boot.dtsi"
|
||||
|
|
@ -4,13 +4,9 @@
|
|||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7796.dtsi"
|
||||
#include "ulcb.dtsi"
|
||||
|
|
@ -30,3 +26,15 @@
|
|||
reg = <0x6 0x00000000 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
|
|
|||
10
arch/arm/dts/r8a7796-salvator-x-u-boot.dts
Normal file
10
arch/arm/dts/r8a7796-salvator-x-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Salvator-X board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a7796-salvator-x.dts"
|
||||
#include "r8a7796-u-boot.dtsi"
|
||||
|
|
@ -3,13 +3,9 @@
|
|||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7796.dtsi"
|
||||
#include "salvator-x.dtsi"
|
||||
|
|
@ -29,3 +25,32 @@
|
|||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&x21_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
|
|
|||
13
arch/arm/dts/r8a7796-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a7796-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A7796 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -3,15 +3,15 @@
|
|||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7796-sysc.h>
|
||||
|
||||
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7796";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -111,7 +111,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
|
|
@ -119,7 +118,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -172,7 +170,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
|
|
@ -366,7 +363,6 @@
|
|||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -377,7 +373,6 @@
|
|||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
|
|
@ -644,6 +639,126 @@
|
|||
};
|
||||
};
|
||||
|
||||
drif00: rif@e6f40000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f40000 0 0x64>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 515>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 515>;
|
||||
renesas,bonding = <&drif01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif01: rif@e6f50000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f50000 0 0x64>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 514>;
|
||||
renesas,bonding = <&drif00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif10: rif@e6f60000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f60000 0 0x64>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 513>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 513>;
|
||||
renesas,bonding = <&drif11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif11: rif@e6f70000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f70000 0 0x64>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 512>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 512>;
|
||||
renesas,bonding = <&drif10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif20: rif@e6f80000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f80000 0 0x64>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 511>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 511>;
|
||||
renesas,bonding = <&drif21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif21: rif@e6f90000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f90000 0 0x64>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 510>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 510>;
|
||||
renesas,bonding = <&drif20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif30: rif@e6fa0000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fa0000 0 0x64>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 509>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 509>;
|
||||
renesas,bonding = <&drif31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif31: rif@e6fb0000 {
|
||||
compatible = "renesas,r8a7796-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fb0000 0 0x64>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 508>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 508>;
|
||||
renesas,bonding = <&drif30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a7796",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
|
|
@ -882,7 +997,7 @@
|
|||
clocks = <&cpg CPG_MOD 211>;
|
||||
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
||||
<&dmac2 0x41>, <&dmac2 0x40>;
|
||||
dma-names = "tx", "rx";
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 211>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -898,7 +1013,7 @@
|
|||
clocks = <&cpg CPG_MOD 210>;
|
||||
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
||||
<&dmac2 0x43>, <&dmac2 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 210>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1106,12 +1221,43 @@
|
|||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a7796-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe65a0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 330>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 330>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac1: dma-controller@e65b0000 {
|
||||
compatible = "renesas,r8a7796-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe65b0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 331>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 331>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a7796",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 704>;
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
renesas,buswait = <11>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
|
|
@ -1121,7 +1267,8 @@
|
|||
};
|
||||
|
||||
xhci0: usb@ee000000 {
|
||||
compatible = "renesas,xhci-r8a7796", "renesas,rcar-gen3-xhci";
|
||||
compatible = "renesas,xhci-r8a7796",
|
||||
"renesas,rcar-gen3-xhci";
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 328>;
|
||||
|
|
@ -1131,7 +1278,15 @@
|
|||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
/* placeholder */
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@ee080100 {
|
||||
|
|
@ -1141,6 +1296,7 @@
|
|||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
companion= <&ohci0>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
|
|
@ -1159,7 +1315,15 @@
|
|||
};
|
||||
|
||||
ohci1: usb@ee0a0000 {
|
||||
/* placeholder */
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee0a0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 702>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@ee0a0100 {
|
||||
|
|
@ -1169,6 +1333,7 @@
|
|||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
companion= <&ohci1>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 702>;
|
||||
status = "disabled";
|
||||
|
|
@ -1492,8 +1657,150 @@
|
|||
/* placeholder */
|
||||
};
|
||||
|
||||
fcpf0: fcp@fe950000 {
|
||||
compatible = "renesas,fcpf";
|
||||
reg = <0 0xfe950000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 615>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 615>;
|
||||
};
|
||||
|
||||
vspb: vsp@fe960000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe960000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 626>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 626>;
|
||||
|
||||
renesas,fcp = <&fcpvb0>;
|
||||
};
|
||||
|
||||
fcpvb0: fcp@fe96f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe96f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 607>;
|
||||
};
|
||||
|
||||
vspi0: vsp@fe9a0000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe9a0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 631>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 631>;
|
||||
|
||||
renesas,fcp = <&fcpvi0>;
|
||||
};
|
||||
|
||||
fcpvi0: fcp@fe9af000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe9af000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 611>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 611>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 623>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 623>;
|
||||
|
||||
renesas,fcp = <&fcpvd0>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
};
|
||||
|
||||
vspd1: vsp@fea28000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea28000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 622>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 622>;
|
||||
|
||||
renesas,fcp = <&fcpvd1>;
|
||||
};
|
||||
|
||||
fcpvd1: fcp@fea2f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea2f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 602>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 602>;
|
||||
};
|
||||
|
||||
vspd2: vsp@fea30000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea30000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 621>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 621>;
|
||||
|
||||
renesas,fcp = <&fcpvd2>;
|
||||
};
|
||||
|
||||
fcpvd2: fcp@fea37000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea37000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 601>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 601>;
|
||||
};
|
||||
|
||||
hdmi0: hdmi@fead0000 {
|
||||
compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
|
||||
reg = <0 0xfead0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
|
||||
clock-names = "iahb", "isfr";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 729>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dw_hdmi0_in: endpoint {
|
||||
remote-endpoint = <&du_out_hdmi0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
/* placeholder */
|
||||
compatible = "renesas,du-r8a7796";
|
||||
reg = <0 0xfeb00000 0 0x70000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
reg-names = "du", "lvds.0";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0";
|
||||
status = "disabled";
|
||||
|
||||
vsps = <&vspd0 &vspd1 &vspd2>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1504,7 +1811,38 @@
|
|||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_hdmi0: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_in>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_lvds0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
imr-lx4@fe860000 {
|
||||
compatible = "renesas,r8a7796-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe860000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 823>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 823>;
|
||||
};
|
||||
|
||||
imr-lx4@fe870000 {
|
||||
compatible = "renesas,r8a7796-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
reg = <0 0xfe870000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 822>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 822>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
10
arch/arm/dts/r8a77970-eagle-u-boot.dts
Normal file
10
arch/arm/dts/r8a77970-eagle-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Eagle board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a77970-eagle.dts"
|
||||
#include "r8a77970-u-boot.dtsi"
|
||||
|
|
@ -4,9 +4,7 @@
|
|||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
13
arch/arm/dts/r8a77970-u-boot.dtsi
Normal file
13
arch/arm/dts/r8a77970-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A77970 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -4,9 +4,7 @@
|
|||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
|
@ -50,7 +48,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
|
|
@ -58,7 +55,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
|
|
@ -75,7 +71,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
|
|
@ -114,7 +109,6 @@
|
|||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -152,7 +146,6 @@
|
|||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
|
|
|
|||
10
arch/arm/dts/r8a77995-draak-u-boot.dts
Normal file
10
arch/arm/dts/r8a77995-draak-u-boot.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot for the Draak board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a77995-draak.dts"
|
||||
#include "r8a77995-u-boot.dtsi"
|
||||
|
|
@ -4,9 +4,7 @@
|
|||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
9
arch/arm/dts/r8a77995-u-boot.dtsi
Normal file
9
arch/arm/dts/r8a77995-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A77995 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
|
@ -4,9 +4,7 @@
|
|||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
|
||||
|
|
@ -49,7 +47,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
scif_clk: scif {
|
||||
|
|
@ -64,7 +61,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
|
|
@ -118,7 +114,6 @@
|
|||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -134,7 +129,6 @@
|
|||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
|
|
|
|||
25
arch/arm/dts/r8a779x-u-boot.dtsi
Normal file
25
arch/arm/dts/r8a779x-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar Gen3
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&cpg {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&prr {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -62,6 +62,7 @@
|
|||
brightness-levels = <256 128 64 16 8 4 0>;
|
||||
default-brightness-level = <6>;
|
||||
|
||||
power-supply = <®_12v>;
|
||||
enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
|
|
@ -83,6 +84,15 @@
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_12v: regulator2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-12V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
rsnd_ak4613: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
|
|
@ -247,7 +257,6 @@
|
|||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
|
|
@ -269,10 +278,6 @@
|
|||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,16 @@
|
|||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
hdmi0-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi0_con: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
@ -129,6 +139,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
x23_clk: x23-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_clk_a {
|
||||
|
|
@ -140,7 +156,6 @@
|
|||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
|
|
@ -163,6 +178,23 @@
|
|||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -199,6 +231,20 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
versaclock5: clock-generator@6a {
|
||||
compatible = "idt,5p49v5925";
|
||||
reg = <0x6a>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&x23_clk>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_dvfs {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,31 @@
|
|||
if RCAR_32
|
||||
|
||||
config RCAR_GEN2
|
||||
bool "Renesas RCar Gen2"
|
||||
|
||||
config R8A7740
|
||||
bool "Renesas SoC R8A7740"
|
||||
|
||||
config R8A7790
|
||||
bool "Renesas SoC R8A7790"
|
||||
select RCAR_GEN2
|
||||
|
||||
config R8A7791
|
||||
bool "Renesas SoC R8A7791"
|
||||
select RCAR_GEN2
|
||||
|
||||
config R8A7792
|
||||
bool "Renesas SoC R8A7792"
|
||||
select RCAR_GEN2
|
||||
|
||||
config R8A7793
|
||||
bool "Renesas SoC R8A7793"
|
||||
select RCAR_GEN2
|
||||
|
||||
config R8A7794
|
||||
bool "Renesas SoC R8A7794"
|
||||
select RCAR_GEN2
|
||||
|
||||
choice
|
||||
prompt "Renesas ARM SoCs board select"
|
||||
optional
|
||||
|
|
|
|||
|
|
@ -7,4 +7,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
|
||||
obj-y := porter.o qos.o ../rcar-common/common.o
|
||||
obj-y := porter.o qos.o
|
||||
|
|
|
|||
|
|
@ -47,11 +47,7 @@ void s_init(void)
|
|||
qos_init();
|
||||
}
|
||||
|
||||
#define TMU0_MSTP125 (1 << 25)
|
||||
#define SDHI0_MSTP314 (1 << 14)
|
||||
#define SDHI2_MSTP311 (1 << 11)
|
||||
#define SCIF0_MSTP721 (1 << 21)
|
||||
#define ETHER_MSTP813 (1 << 13)
|
||||
#define TMU0_MSTP125 BIT(25)
|
||||
|
||||
#define SD2CKCR 0xE615026C
|
||||
#define SD_97500KHZ 0x7
|
||||
|
|
@ -60,15 +56,6 @@ int board_early_init_f(void)
|
|||
{
|
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
|
||||
/* SCIF0 */
|
||||
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
|
||||
|
||||
/* ETHER */
|
||||
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
|
||||
|
||||
/* SDHI */
|
||||
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP311);
|
||||
|
||||
/*
|
||||
* SD0 clock is set to 97.5MHz by default.
|
||||
* Set SD2 to the 97.5MHz as well.
|
||||
|
|
@ -78,112 +65,25 @@ int board_early_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* LSI pin pull-up control */
|
||||
#define PUPR5 0xe6060114
|
||||
#define PUPR5_ETH 0x3FFC0000
|
||||
#define PUPR5_ETH_MAGIC (1 << 27)
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
/* Init PFC controller */
|
||||
r8a7791_pinmux_init();
|
||||
|
||||
/* Ether Enable */
|
||||
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RXD0, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RXD1, NULL);
|
||||
gpio_request(GPIO_FN_ETH_LINK, NULL);
|
||||
gpio_request(GPIO_FN_ETH_REFCLK, NULL);
|
||||
gpio_request(GPIO_FN_ETH_MDIO, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TXD1, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TX_EN, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TXD0, NULL);
|
||||
gpio_request(GPIO_FN_ETH_MDC, NULL);
|
||||
gpio_request(GPIO_FN_IRQ0, NULL);
|
||||
|
||||
mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
|
||||
gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
|
||||
mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
|
||||
|
||||
gpio_direction_output(GPIO_GP_5_22, 0);
|
||||
mdelay(20);
|
||||
gpio_set_value(GPIO_GP_5_22, 1);
|
||||
udelay(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define CXR24 0xEE7003C0 /* MAC address high register */
|
||||
#define CXR25 0xEE7003C8 /* MAC address low register */
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_SH_ETHER
|
||||
int ret = -ENODEV;
|
||||
u32 val;
|
||||
unsigned char enetaddr[6];
|
||||
|
||||
ret = sh_eth_initialize(bis);
|
||||
if (!eth_env_get_enetaddr("ethaddr", enetaddr))
|
||||
return ret;
|
||||
|
||||
/* Set Mac address */
|
||||
val = enetaddr[0] << 24 | enetaddr[1] << 16 |
|
||||
enetaddr[2] << 8 | enetaddr[3];
|
||||
writel(val, CXR24);
|
||||
|
||||
val = enetaddr[4] << 8 | enetaddr[5];
|
||||
writel(val, CXR25);
|
||||
|
||||
return ret;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
|
||||
#ifdef CONFIG_SH_SDHI
|
||||
gpio_request(GPIO_FN_SD0_DATA0, NULL);
|
||||
gpio_request(GPIO_FN_SD0_DATA1, NULL);
|
||||
gpio_request(GPIO_FN_SD0_DATA2, NULL);
|
||||
gpio_request(GPIO_FN_SD0_DATA3, NULL);
|
||||
gpio_request(GPIO_FN_SD0_CLK, NULL);
|
||||
gpio_request(GPIO_FN_SD0_CMD, NULL);
|
||||
gpio_request(GPIO_FN_SD0_CD, NULL);
|
||||
gpio_request(GPIO_FN_SD2_DATA0, NULL);
|
||||
gpio_request(GPIO_FN_SD2_DATA1, NULL);
|
||||
gpio_request(GPIO_FN_SD2_DATA2, NULL);
|
||||
gpio_request(GPIO_FN_SD2_DATA3, NULL);
|
||||
gpio_request(GPIO_FN_SD2_CLK, NULL);
|
||||
gpio_request(GPIO_FN_SD2_CMD, NULL);
|
||||
gpio_request(GPIO_FN_SD2_CD, NULL);
|
||||
|
||||
/* SDHI 0 */
|
||||
gpio_request(GPIO_GP_2_12, NULL);
|
||||
gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
|
||||
|
||||
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
|
||||
SH_SDHI_QUIRK_16BIT_BUF);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* SDHI 2 */
|
||||
gpio_request(GPIO_GP_2_26, NULL);
|
||||
gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
|
||||
|
||||
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
||||
if (fdtdec_setup_memory_size() != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
fdtdec_setup_memory_banksize();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -215,14 +115,3 @@ void reset_cpu(ulong addr)
|
|||
val |= 0x02;
|
||||
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
|
||||
}
|
||||
|
||||
static const struct sh_serial_platdata serial_platdata = {
|
||||
.base = SCIF0_BASE,
|
||||
.type = PORT_SCIF,
|
||||
.clk = CONFIG_P_CLK_FREQ,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(porter_serials) = {
|
||||
.name = "serial_sh",
|
||||
.platdata = &serial_platdata,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_R8A7794=y
|
||||
CONFIG_TARGET_ALT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
@ -20,6 +22,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
# CONFIG_SYS_THUMB_BUILD is not set
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_R8A7740=y
|
||||
CONFIG_TARGET_ARMADILLO_800EVA=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_R8A7792=y
|
||||
CONFIG_TARGET_BLANCHE=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche-u-boot"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_IMI is not set
|
||||
|
|
@ -15,6 +17,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_R8A7793=y
|
||||
CONFIG_TARGET_GOSE=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
@ -20,6 +22,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_R8A7791=y
|
||||
CONFIG_TARGET_KOELSCH=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
@ -20,6 +22,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_R8A7790=y
|
||||
CONFIG_TARGET_LAGER=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
@ -20,6 +22,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
|
|
|
|||
|
|
@ -1,14 +1,18 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_R8A7791=y
|
||||
CONFIG_TARGET_PORTER=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
|
|
@ -20,15 +24,32 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_UNIPHIER=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_SH_ETHER=y
|
||||
CONFIG_BAUDRATE=38400
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_PCI_RCAR_GEN2=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_PFC=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_PCI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ CONFIG_ARCH_RMOBILE=y
|
|||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_SALVATOR_X=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ CONFIG_ARCH_RMOBILE=y
|
|||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_ULCB=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
|
|||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_R8A7796=y
|
||||
CONFIG_TARGET_SALVATOR_X=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
|
|||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_R8A7796=y
|
||||
CONFIG_TARGET_ULCB=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
|
|||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_R8A77970=y
|
||||
CONFIG_TARGET_EAGLE=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
|
|||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_R8A77995=y
|
||||
CONFIG_TARGET_DRAAK=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_R8A7794=y
|
||||
CONFIG_TARGET_SILK=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
@ -20,6 +22,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_R8A7790=y
|
||||
CONFIG_TARGET_STOUT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
@ -20,6 +22,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
|
|
|
|||
|
|
@ -4,9 +4,79 @@ config CLK_RENESAS
|
|||
help
|
||||
Enable support for clock present on Renesas RCar SoCs.
|
||||
|
||||
config CLK_RCAR_GEN2
|
||||
bool "Renesas RCar Gen2 clock driver"
|
||||
def_bool y if RCAR_32
|
||||
depends on CLK_RENESAS
|
||||
help
|
||||
Enable this to support the clocks on Renesas RCar Gen2 SoC.
|
||||
|
||||
config CLK_R8A7790
|
||||
bool "Renesas R8A7790 clock driver"
|
||||
def_bool y if R8A7790
|
||||
depends on CLK_RCAR_GEN2
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7790 SoC.
|
||||
|
||||
config CLK_R8A7791
|
||||
bool "Renesas R8A7791 clock driver"
|
||||
def_bool y if R8A7791
|
||||
depends on CLK_RCAR_GEN2
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7791 SoC.
|
||||
|
||||
config CLK_R8A7792
|
||||
bool "Renesas R8A7792 clock driver"
|
||||
def_bool y if R8A7792
|
||||
depends on CLK_RCAR_GEN2
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7792 SoC.
|
||||
|
||||
config CLK_R8A7793
|
||||
bool "Renesas R8A7793 clock driver"
|
||||
def_bool y if R8A7793
|
||||
depends on CLK_RCAR_GEN2
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7793 SoC.
|
||||
|
||||
config CLK_R8A7794
|
||||
bool "Renesas R8A7794 clock driver"
|
||||
def_bool y if R8A7794
|
||||
depends on CLK_RCAR_GEN2
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7794 SoC.
|
||||
|
||||
config CLK_RCAR_GEN3
|
||||
bool "Renesas RCar Gen3 clock driver"
|
||||
def_bool y if RCAR_GEN3
|
||||
depends on CLK_RENESAS
|
||||
help
|
||||
Enable this to support the clocks on Renesas RCar Gen3 SoC.
|
||||
|
||||
config CLK_R8A7795
|
||||
bool "Renesas R8A7795 clock driver"
|
||||
def_bool y if R8A7795
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7795 SoC.
|
||||
|
||||
config CLK_R8A7796
|
||||
bool "Renesas R8A7796 clock driver"
|
||||
def_bool y if R8A7796
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7796 SoC.
|
||||
|
||||
config CLK_R8A77970
|
||||
bool "Renesas R8A77970 clock driver"
|
||||
def_bool y if R8A77970
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A77970 SoC.
|
||||
|
||||
config CLK_R8A77995
|
||||
bool "Renesas R8A77995 clock driver"
|
||||
def_bool y if R8A77995
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A77995 SoC.
|
||||
|
|
|
|||
|
|
@ -1 +1,12 @@
|
|||
obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
|
||||
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
|
||||
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
|
||||
|
|
|
|||
279
drivers/clk/renesas/clk-rcar-gen2.c
Normal file
279
drivers/clk/renesas/clk-rcar-gen2.c
Normal file
|
|
@ -0,0 +1,279 @@
|
|||
/*
|
||||
* Renesas RCar Gen2 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
#define CPG_RST_MODEMR 0x0060
|
||||
|
||||
#define CPG_PLL0CR 0x00d8
|
||||
#define CPG_SDCKCR 0x0074
|
||||
|
||||
struct clk_div_table {
|
||||
u8 val;
|
||||
u8 div;
|
||||
};
|
||||
|
||||
/* SDHI divisors */
|
||||
static const struct clk_div_table cpg_sdh_div_table[] = {
|
||||
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table cpg_sd01_div_table[] = {
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div)
|
||||
{
|
||||
while ((*table++).val) {
|
||||
if ((*table).div == div)
|
||||
return div;
|
||||
}
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
static int gen2_clk_enable(struct clk *clk)
|
||||
{
|
||||
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
return renesas_clk_endisable(clk, priv->base, true);
|
||||
}
|
||||
|
||||
static int gen2_clk_disable(struct clk *clk)
|
||||
{
|
||||
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
return renesas_clk_endisable(clk, priv->base, false);
|
||||
}
|
||||
|
||||
static ulong gen2_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
struct cpg_mssr_info *info = priv->info;
|
||||
struct clk parent;
|
||||
const struct cpg_core_clk *core;
|
||||
const struct rcar_gen2_cpg_pll_config *pll_config =
|
||||
priv->cpg_pll_config;
|
||||
u32 value, mult, div, rate = 0;
|
||||
int ret;
|
||||
|
||||
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
|
||||
|
||||
ret = renesas_clk_get_parent(clk, info, &parent);
|
||||
if (ret) {
|
||||
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (renesas_clk_is_mod(clk)) {
|
||||
rate = gen2_clk_get_rate(&parent);
|
||||
debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
|
||||
__func__, __LINE__, parent.id, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
ret = renesas_clk_get_core(clk, info, &core);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_IN:
|
||||
if (core->id == info->clk_extal_id) {
|
||||
rate = clk_get_rate(&priv->clk_extal);
|
||||
debug("%s[%i] EXTAL clk: rate=%u\n",
|
||||
__func__, __LINE__, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
if (core->id == info->clk_extal_usb_id) {
|
||||
rate = clk_get_rate(&priv->clk_extal_usb);
|
||||
debug("%s[%i] EXTALR clk: rate=%u\n",
|
||||
__func__, __LINE__, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
|
||||
case CLK_TYPE_FF:
|
||||
rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
|
||||
debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, core->mult, core->div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */
|
||||
value = (readl(priv->base + core->offset) & 0x3f) + 1;
|
||||
rate = gen2_clk_get_rate(&parent) / value;
|
||||
debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, value, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN2_MAIN:
|
||||
rate = gen2_clk_get_rate(&parent) / pll_config->extal_div;
|
||||
debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, pll_config->extal_div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN2_PLL0:
|
||||
/*
|
||||
* PLL0 is a configurable multiplier clock except on R-Car
|
||||
* V2H/E2. Register the PLL0 clock as a fixed factor clock for
|
||||
* now as there's no generic multiplier clock implementation and
|
||||
* we currently have no need to change the multiplier value.
|
||||
*/
|
||||
mult = pll_config->pll0_mult;
|
||||
if (!mult) {
|
||||
value = readl(priv->base + CPG_PLL0CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
}
|
||||
|
||||
rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div;
|
||||
debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
|
||||
__func__, __LINE__, core->parent, mult, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN2_PLL1:
|
||||
rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2;
|
||||
debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, pll_config->pll1_mult, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN2_PLL3:
|
||||
rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult;
|
||||
debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, pll_config->pll3_mult, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN2_SDH:
|
||||
value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf;
|
||||
div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value);
|
||||
rate = gen2_clk_get_rate(&parent) / div;
|
||||
debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN2_SD0:
|
||||
value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf;
|
||||
div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
|
||||
rate = gen2_clk_get_rate(&parent) / div;
|
||||
debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN2_SD1:
|
||||
value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf;
|
||||
div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
|
||||
rate = gen2_clk_get_rate(&parent) / div;
|
||||
debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, div, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
printf("%s[%i] unknown fail\n", __func__, __LINE__);
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
return gen2_clk_get_rate(clk);
|
||||
}
|
||||
|
||||
static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
|
||||
{
|
||||
if (args->args_count != 2) {
|
||||
debug("Invaild args_count: %d\n", args->args_count);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
clk->id = (args->args[0] << 16) | args->args[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops gen2_clk_ops = {
|
||||
.enable = gen2_clk_enable,
|
||||
.disable = gen2_clk_disable,
|
||||
.get_rate = gen2_clk_get_rate,
|
||||
.set_rate = gen2_clk_set_rate,
|
||||
.of_xlate = gen2_clk_of_xlate,
|
||||
};
|
||||
|
||||
int gen2_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct gen2_clk_priv *priv = dev_get_priv(dev);
|
||||
struct cpg_mssr_info *info =
|
||||
(struct cpg_mssr_info *)dev_get_driver_data(dev);
|
||||
fdt_addr_t rst_base;
|
||||
u32 cpg_mode;
|
||||
int ret;
|
||||
|
||||
priv->base = (struct gen2_base *)devfdt_get_addr(dev);
|
||||
if (!priv->base)
|
||||
return -EINVAL;
|
||||
|
||||
priv->info = info;
|
||||
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
|
||||
if (rst_base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
cpg_mode = readl(rst_base + CPG_RST_MODEMR);
|
||||
|
||||
priv->cpg_pll_config =
|
||||
(struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode);
|
||||
if (!priv->cpg_pll_config->extal_div)
|
||||
return -EINVAL;
|
||||
|
||||
ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (info->extal_usb_node) {
|
||||
ret = clk_get_by_name(dev, info->extal_usb_node,
|
||||
&priv->clk_extal_usb);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int gen2_clk_remove(struct udevice *dev)
|
||||
{
|
||||
struct gen2_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return renesas_clk_remove(priv->base, priv->info);
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
295
drivers/clk/renesas/r8a7790-cpg-mssr.c
Normal file
295
drivers/clk/renesas/r8a7790-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,295 @@
|
|||
/*
|
||||
* r8a7790 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7790_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_USB_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7790_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
|
||||
DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7790_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
DEF_BASE("rcan", R8A7790_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
|
||||
|
||||
DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7790_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("imp", R8A7790_CLK_IMP, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zb3", R8A7790_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7790_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7790_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("mp", R8A7790_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cp", R8A7790_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("r", R8A7790_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7790_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
|
||||
DEF_DIV6P1("sd2", R8A7790_CLK_SD2, CLK_PLL1_DIV2, 0x078),
|
||||
DEF_DIV6P1("sd3", R8A7790_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
|
||||
DEF_DIV6P1("mmc0", R8A7790_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
|
||||
DEF_DIV6P1("mmc1", R8A7790_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
|
||||
DEF_DIV6P1("ssp", R8A7790_CLK_SSP, CLK_PLL1_DIV2, 0x248),
|
||||
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
|
||||
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
|
||||
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
|
||||
DEF_MOD("jpu", 106, R8A7790_CLK_M2),
|
||||
DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
|
||||
DEF_MOD("tmu1", 111, R8A7790_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7790_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
|
||||
DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
|
||||
DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
|
||||
DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7790_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7790_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7790_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
|
||||
DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
|
||||
DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
|
||||
DEF_MOD("msiof2", 205, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifb0", 206, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifb1", 207, R8A7790_CLK_MP),
|
||||
DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
|
||||
DEF_MOD("msiof3", 215, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifb2", 216, R8A7790_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7790_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7790_CLK_ZS),
|
||||
DEF_MOD("iic2", 300, R8A7790_CLK_HP),
|
||||
DEF_MOD("tpu0", 304, R8A7790_CLK_CP),
|
||||
DEF_MOD("mmcif1", 305, R8A7790_CLK_MMC1),
|
||||
DEF_MOD("scif2", 310, R8A7790_CLK_P),
|
||||
DEF_MOD("sdhi3", 311, R8A7790_CLK_SD3),
|
||||
DEF_MOD("sdhi2", 312, R8A7790_CLK_SD2),
|
||||
DEF_MOD("sdhi1", 313, R8A7790_CLK_SD1),
|
||||
DEF_MOD("sdhi0", 314, R8A7790_CLK_SD0),
|
||||
DEF_MOD("mmcif0", 315, R8A7790_CLK_MMC0),
|
||||
DEF_MOD("iic0", 318, R8A7790_CLK_HP),
|
||||
DEF_MOD("pciec", 319, R8A7790_CLK_MP),
|
||||
DEF_MOD("iic1", 323, R8A7790_CLK_HP),
|
||||
DEF_MOD("usb3.0", 328, R8A7790_CLK_MP),
|
||||
DEF_MOD("cmt1", 329, R8A7790_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
|
||||
DEF_MOD("irqc", 407, R8A7790_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
|
||||
DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7790_CLK_HP),
|
||||
DEF_MOD("adsp_mod", 506, R8A7790_CLK_ADSP),
|
||||
DEF_MOD("thermal", 522, CLK_EXTAL),
|
||||
DEF_MOD("pwm", 523, R8A7790_CLK_P),
|
||||
DEF_MOD("usb-ehci", 703, R8A7790_CLK_MP),
|
||||
DEF_MOD("usbhs", 704, R8A7790_CLK_HP),
|
||||
DEF_MOD("hscif1", 716, R8A7790_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7790_CLK_ZS),
|
||||
DEF_MOD("scif1", 720, R8A7790_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7790_CLK_P),
|
||||
DEF_MOD("du2", 722, R8A7790_CLK_ZX),
|
||||
DEF_MOD("du1", 723, R8A7790_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7790_CLK_ZX),
|
||||
DEF_MOD("lvds1", 725, R8A7790_CLK_ZX),
|
||||
DEF_MOD("lvds0", 726, R8A7790_CLK_ZX),
|
||||
DEF_MOD("mlb", 802, R8A7790_CLK_HP),
|
||||
DEF_MOD("vin3", 808, R8A7790_CLK_ZG),
|
||||
DEF_MOD("vin2", 809, R8A7790_CLK_ZG),
|
||||
DEF_MOD("vin1", 810, R8A7790_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7790_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7790_CLK_HP),
|
||||
DEF_MOD("ether", 813, R8A7790_CLK_P),
|
||||
DEF_MOD("sata1", 814, R8A7790_CLK_ZS),
|
||||
DEF_MOD("sata0", 815, R8A7790_CLK_ZS),
|
||||
DEF_MOD("gyro-adc", 901, R8A7790_CLK_P),
|
||||
DEF_MOD("gpio5", 907, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7790_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7790_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7790_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7790_CLK_QSPI),
|
||||
DEF_MOD("iicdvfs", 926, R8A7790_CLK_CP),
|
||||
DEF_MOD("i2c3", 928, R8A7790_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7790_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7790_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7790_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7790_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7790_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *1
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x172/2 x208/2 x106
|
||||
* 0 0 1 15 x172/2 x208/2 x88
|
||||
* 0 1 0 20 x130/2 x156/2 x80
|
||||
* 0 1 1 20 x130/2 x156/2 x66
|
||||
* 1 0 0 26 / 2 x200/2 x240/2 x122
|
||||
* 1 0 1 26 / 2 x200/2 x240/2 x102
|
||||
* 1 1 0 30 / 2 x172/2 x208/2 x106
|
||||
* 1 1 1 30 / 2 x172/2 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
|
||||
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
|
||||
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7790_mstp_table[] = {
|
||||
{ 0x00640801, 0x400000, 0x00640801, 0x0 },
|
||||
{ 0xDB6E9BDF, 0x0, 0xDB6E9BDF, 0x0 },
|
||||
{ 0x300DA1FC, 0x2010, 0x300DA1FC, 0x0 },
|
||||
{ 0xF08CF831, 0x0, 0xF08CF831, 0x0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0x0 },
|
||||
{ 0x44C00046, 0x0, 0x44C00046, 0x0 },
|
||||
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
|
||||
{ 0x07F30718, 0x200000, 0x07F30718, 0x0 },
|
||||
{ 0x01F0FF84, 0x0, 0x01F0FF84, 0x0 },
|
||||
{ 0xF5979FCF, 0x0, 0xF5979FCF, 0x0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x00000000, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a7790_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7790_cpg_mssr_info = {
|
||||
.core_clk = r8a7790_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7790_core_clks),
|
||||
.mod_clk = r8a7790_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7790_mod_clks),
|
||||
.mstp_table = r8a7790_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7790_mstp_table),
|
||||
.reset_node = "renesas,r8a7790-rst",
|
||||
.extal_usb_node = "usb_extal",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extal_usb_id = CLK_USB_EXTAL,
|
||||
.pll0_div = 2,
|
||||
.get_pll_config = r8a7790_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7790_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7790-cpg-mssr",
|
||||
.data = (ulong)&r8a7790_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7790) = {
|
||||
.name = "clk_r8a7790",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7790_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
|
||||
.ops = &gen2_clk_ops,
|
||||
.probe = gen2_clk_probe,
|
||||
.remove = gen2_clk_remove,
|
||||
};
|
||||
292
drivers/clk/renesas/r8a7791-cpg-mssr.c
Normal file
292
drivers/clk/renesas/r8a7791-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/*
|
||||
* Renesas R8A7791 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7791 Clock Pulse Generator / Module Standby and Software Reset
|
||||
* Copyright (C) 2015-2017 Glider bvba
|
||||
* Based on clk-rcar-gen2.c
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7791_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_USB_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7791_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
|
||||
DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
|
||||
|
||||
DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
|
||||
DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),
|
||||
DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
|
||||
DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
|
||||
DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),
|
||||
DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7791_mod_clks[] = {
|
||||
DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
|
||||
DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
|
||||
DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
|
||||
DEF_MOD("jpu", 106, R8A7791_CLK_M2),
|
||||
DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
|
||||
DEF_MOD("tmu1", 111, R8A7791_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
|
||||
DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
|
||||
DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7791_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7791_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7791_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
|
||||
DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
|
||||
DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
|
||||
DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
|
||||
DEF_MOD("msiof2", 205, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifb0", 206, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifb1", 207, R8A7791_CLK_MP),
|
||||
DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifb2", 216, R8A7791_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS),
|
||||
DEF_MOD("tpu0", 304, R8A7791_CLK_CP),
|
||||
DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3),
|
||||
DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2),
|
||||
DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0),
|
||||
DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0),
|
||||
DEF_MOD("iic0", 318, R8A7791_CLK_HP),
|
||||
DEF_MOD("pciec", 319, R8A7791_CLK_MP),
|
||||
DEF_MOD("iic1", 323, R8A7791_CLK_HP),
|
||||
DEF_MOD("usb3.0", 328, R8A7791_CLK_MP),
|
||||
DEF_MOD("cmt1", 329, R8A7791_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
|
||||
DEF_MOD("irqc", 407, R8A7791_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
|
||||
DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP),
|
||||
DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP),
|
||||
DEF_MOD("thermal", 522, CLK_EXTAL),
|
||||
DEF_MOD("pwm", 523, R8A7791_CLK_P),
|
||||
DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP),
|
||||
DEF_MOD("usbhs", 704, R8A7791_CLK_HP),
|
||||
DEF_MOD("hscif2", 713, R8A7791_CLK_ZS),
|
||||
DEF_MOD("scif5", 714, R8A7791_CLK_P),
|
||||
DEF_MOD("scif4", 715, R8A7791_CLK_P),
|
||||
DEF_MOD("hscif1", 716, R8A7791_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7791_CLK_ZS),
|
||||
DEF_MOD("scif3", 718, R8A7791_CLK_P),
|
||||
DEF_MOD("scif2", 719, R8A7791_CLK_P),
|
||||
DEF_MOD("scif1", 720, R8A7791_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7791_CLK_P),
|
||||
DEF_MOD("du1", 723, R8A7791_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7791_CLK_ZX),
|
||||
DEF_MOD("lvds0", 726, R8A7791_CLK_ZX),
|
||||
DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX),
|
||||
DEF_MOD("mlb", 802, R8A7791_CLK_HP),
|
||||
DEF_MOD("vin2", 809, R8A7791_CLK_ZG),
|
||||
DEF_MOD("vin1", 810, R8A7791_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7791_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7791_CLK_HP),
|
||||
DEF_MOD("ether", 813, R8A7791_CLK_P),
|
||||
DEF_MOD("sata1", 814, R8A7791_CLK_ZS),
|
||||
DEF_MOD("sata0", 815, R8A7791_CLK_ZS),
|
||||
DEF_MOD("gyro-adc", 901, R8A7791_CLK_P),
|
||||
DEF_MOD("gpio7", 904, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio6", 905, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio5", 907, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7791_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7791_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7791_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI),
|
||||
DEF_MOD("i2c5", 925, R8A7791_CLK_HP),
|
||||
DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A7791_CLK_HP),
|
||||
DEF_MOD("i2c3", 928, R8A7791_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7791_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7791_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7791_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7791_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7791_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scifa3", 1106, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifa4", 1107, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifa5", 1108, R8A7791_CLK_MP),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *1
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x172/2 x208/2 x106
|
||||
* 0 0 1 15 x172/2 x208/2 x88
|
||||
* 0 1 0 20 x130/2 x156/2 x80
|
||||
* 0 1 1 20 x130/2 x156/2 x66
|
||||
* 1 0 0 26 / 2 x200/2 x240/2 x122
|
||||
* 1 0 1 26 / 2 x200/2 x240/2 x102
|
||||
* 1 1 0 30 / 2 x172/2 x208/2 x106
|
||||
* 1 1 1 30 / 2 x172/2 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
|
||||
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
|
||||
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7791_mstp_table[] = {
|
||||
{ 0x00640801, 0x400000, 0x00640801, 0x0 },
|
||||
{ 0x9B6C9B5A, 0x0, 0x9B6C9B5A, 0x0 },
|
||||
{ 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
|
||||
{ 0xF08CD810, 0x0, 0xF08CD810, 0x0 },
|
||||
{ 0x800001C4, 0x180, 0x800001C4, 0x0 },
|
||||
{ 0x44C00046, 0x0, 0x44C00046, 0x0 },
|
||||
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
|
||||
{ 0x05BFE618, 0x200000, 0x05BFE618, 0x0 },
|
||||
{ 0x40C0FE85, 0x0, 0x40C0FE85, 0x0 },
|
||||
{ 0xFF979FFF, 0x0, 0xFF979FFF, 0x0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
|
||||
{ 0x000001C0, 0x0, 0x000001C0, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a7791_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7791_cpg_mssr_info = {
|
||||
.core_clk = r8a7791_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7791_core_clks),
|
||||
.mod_clk = r8a7791_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7791_mod_clks),
|
||||
.mstp_table = r8a7791_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table),
|
||||
.reset_node = "renesas,r8a7791-rst",
|
||||
.extal_usb_node = "usb_extal",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extal_usb_id = CLK_USB_EXTAL,
|
||||
.pll0_div = 2,
|
||||
.get_pll_config = r8a7791_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7791_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7791-cpg-mssr",
|
||||
.data = (ulong)&r8a7791_cpg_mssr_info
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r8a7793-cpg-mssr",
|
||||
.data = (ulong)&r8a7791_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7791) = {
|
||||
.name = "clk_r8a7791",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7791_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
|
||||
.ops = &gen2_clk_ops,
|
||||
.probe = gen2_clk_probe,
|
||||
.remove = gen2_clk_remove,
|
||||
};
|
||||
249
drivers/clk/renesas/r8a7792-cpg-mssr.c
Normal file
249
drivers/clk/renesas/r8a7792-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* r8a7792 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
|
||||
DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
|
||||
DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
|
||||
DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
|
||||
DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
|
||||
DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
|
||||
DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
|
||||
DEF_MOD("jpu", 106, R8A7792_CLK_M2),
|
||||
DEF_MOD("tmu1", 111, R8A7792_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7792_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7792_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7792_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
|
||||
DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
|
||||
DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
|
||||
DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
|
||||
DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
|
||||
DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
|
||||
DEF_MOD("cmt1", 329, R8A7792_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7792_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
|
||||
DEF_MOD("thermal", 522, CLK_EXTAL),
|
||||
DEF_MOD("pwm", 523, R8A7792_CLK_P),
|
||||
DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
|
||||
DEF_MOD("scif3", 718, R8A7792_CLK_P),
|
||||
DEF_MOD("scif2", 719, R8A7792_CLK_P),
|
||||
DEF_MOD("scif1", 720, R8A7792_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7792_CLK_P),
|
||||
DEF_MOD("du1", 723, R8A7792_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7792_CLK_ZX),
|
||||
DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
|
||||
DEF_MOD("imr-lx3", 821, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-1", 822, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-5", 825, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-4", 826, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-3", 827, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-2", 828, R8A7792_CLK_ZG),
|
||||
DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
|
||||
DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7792_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7792_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
|
||||
DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
|
||||
DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
|
||||
DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
|
||||
DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *2
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x200/3 x208/2 x106
|
||||
* 0 0 1 15 x200/3 x208/2 x88
|
||||
* 0 1 0 20 x150/3 x156/2 x80
|
||||
* 0 1 1 20 x150/3 x156/2 x66
|
||||
* 1 0 0 26 / 2 x230/3 x240/2 x122
|
||||
* 1 0 1 26 / 2 x230/3 x240/2 x102
|
||||
* 1 1 0 30 / 2 x200/3 x208/2 x106
|
||||
* 1 1 1 30 / 2 x200/3 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
|
||||
* *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
|
||||
{ 1, 208, 106, 200 },
|
||||
{ 1, 208, 88, 200 },
|
||||
{ 1, 156, 80, 150 },
|
||||
{ 1, 156, 66, 150 },
|
||||
{ 2, 240, 122, 230 },
|
||||
{ 2, 240, 102, 230 },
|
||||
{ 2, 208, 106, 200 },
|
||||
{ 2, 208, 88, 200 },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7792_mstp_table[] = {
|
||||
{ 0x00400801, 0x400000, 0x00400801, 0x0 },
|
||||
{ 0x9B6F987F, 0x0, 0x9B6F987F, 0x0 },
|
||||
{ 0x108CE100, 0x0, 0x108CE100, 0x80000 },
|
||||
{ 0x20004010, 0x4000, 0x20004010, 0x0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0x0 },
|
||||
{ 0x44C00004, 0x0, 0x44C00004, 0x0 },
|
||||
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
|
||||
{ 0x01BF0000, 0x200000, 0x01BF0000, 0x0 },
|
||||
{ 0x1FE01FB0, 0x0, 0x1FE01FB0, 0x0 },
|
||||
{ 0xFE2BFFB2, 0x20000, 0xFE2BFFB2, 0x0 },
|
||||
{ 0x00001820, 0x0, 0x00001820, 0x0 },
|
||||
{ 0x00000008, 0x0, 0x00000008, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a7792_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7792_cpg_mssr_info = {
|
||||
.core_clk = r8a7792_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7792_core_clks),
|
||||
.mod_clk = r8a7792_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7792_mod_clks),
|
||||
.mstp_table = r8a7792_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table),
|
||||
.reset_node = "renesas,r8a7792-rst",
|
||||
.extal_usb_node = "usb_extal",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extal_usb_id = CLK_USB_EXTAL,
|
||||
.pll0_div = 2,
|
||||
.get_pll_config = r8a7792_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7792_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7792-cpg-mssr",
|
||||
.data = (ulong)&r8a7792_cpg_mssr_info
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r8a7793-cpg-mssr",
|
||||
.data = (ulong)&r8a7792_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7792) = {
|
||||
.name = "clk_r8a7792",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7792_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
|
||||
.ops = &gen2_clk_ops,
|
||||
.probe = gen2_clk_probe,
|
||||
.remove = gen2_clk_remove,
|
||||
};
|
||||
276
drivers/clk/renesas/r8a7794-cpg-mssr.c
Normal file
276
drivers/clk/renesas/r8a7794-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,276 @@
|
|||
/*
|
||||
* r8a7794 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7794_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_USB_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
|
||||
|
||||
DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1),
|
||||
DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
|
||||
DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078),
|
||||
DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
|
||||
DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
|
||||
DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
|
||||
DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
|
||||
DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
|
||||
DEF_MOD("jpu", 106, R8A7794_CLK_M2),
|
||||
DEF_MOD("tmu1", 111, R8A7794_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7794_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
|
||||
DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7794_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7794_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7794_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
|
||||
DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
|
||||
DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
|
||||
DEF_MOD("msiof2", 205, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifb0", 206, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifb1", 207, R8A7794_CLK_MP),
|
||||
DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifb2", 216, R8A7794_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS),
|
||||
DEF_MOD("tpu0", 304, R8A7794_CLK_CP),
|
||||
DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3),
|
||||
DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2),
|
||||
DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0),
|
||||
DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0),
|
||||
DEF_MOD("iic0", 318, R8A7794_CLK_HP),
|
||||
DEF_MOD("iic1", 323, R8A7794_CLK_HP),
|
||||
DEF_MOD("cmt1", 329, R8A7794_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
|
||||
DEF_MOD("irqc", 407, R8A7794_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
|
||||
DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP),
|
||||
DEF_MOD("pwm", 523, R8A7794_CLK_P),
|
||||
DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP),
|
||||
DEF_MOD("usbhs", 704, R8A7794_CLK_HP),
|
||||
DEF_MOD("hscif2", 713, R8A7794_CLK_ZS),
|
||||
DEF_MOD("scif5", 714, R8A7794_CLK_P),
|
||||
DEF_MOD("scif4", 715, R8A7794_CLK_P),
|
||||
DEF_MOD("hscif1", 716, R8A7794_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7794_CLK_ZS),
|
||||
DEF_MOD("scif3", 718, R8A7794_CLK_P),
|
||||
DEF_MOD("scif2", 719, R8A7794_CLK_P),
|
||||
DEF_MOD("scif1", 720, R8A7794_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7794_CLK_P),
|
||||
DEF_MOD("du1", 723, R8A7794_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7794_CLK_ZX),
|
||||
DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX),
|
||||
DEF_MOD("mlb", 802, R8A7794_CLK_HP),
|
||||
DEF_MOD("vin1", 810, R8A7794_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7794_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7794_CLK_HP),
|
||||
DEF_MOD("ether", 813, R8A7794_CLK_P),
|
||||
DEF_MOD("gyro-adc", 901, R8A7794_CLK_P),
|
||||
DEF_MOD("gpio6", 905, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio5", 907, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7794_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7794_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7794_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI),
|
||||
DEF_MOD("i2c5", 925, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c4", 927, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c3", 928, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7794_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7794_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7794_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scifa3", 1106, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifa4", 1107, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
|
||||
};
|
||||
|
||||
static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *2
|
||||
*---------------------------------------------------
|
||||
* 0 0 1 15 x200/3 x208/2 x88
|
||||
* 0 1 1 20 x150/3 x156/2 x66
|
||||
* 1 0 1 26 / 2 x230/3 x240/2 x102
|
||||
* 1 1 1 30 / 2 x200/3 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3)
|
||||
* *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
|
||||
{ 1, 208, 88, 200 },
|
||||
{ 1, 156, 66, 150 },
|
||||
{ 2, 240, 102, 230 },
|
||||
{ 2, 208, 88, 200 },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7794_mstp_table[] = {
|
||||
{ 0x00440801, 0x400000, 0x00440801, 0x0 },
|
||||
{ 0x936899DA, 0x0, 0x936899DA, 0x0 },
|
||||
{ 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
|
||||
{ 0xE084D810, 0x0, 0xE084D810, 0x0 },
|
||||
{ 0x800001C4, 0x180, 0x800001C4, 0x0 },
|
||||
{ 0x40C00044, 0x0, 0x40C00044, 0x0 },
|
||||
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
|
||||
{ 0x013FE618, 0x80000, 0x013FE618, 0x0 },
|
||||
{ 0x40803C05, 0x0, 0x40803C05, 0x0 },
|
||||
{ 0xFB879FEE, 0x0, 0xFB879FEE, 0x0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
|
||||
{ 0x000001C0, 0x0, 0x000001C0, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a7794_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7794_cpg_mssr_info = {
|
||||
.core_clk = r8a7794_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7794_core_clks),
|
||||
.mod_clk = r8a7794_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7794_mod_clks),
|
||||
.mstp_table = r8a7794_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table),
|
||||
.reset_node = "renesas,r8a7794-rst",
|
||||
.extal_usb_node = "usb_extal",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extal_usb_id = CLK_USB_EXTAL,
|
||||
.pll0_div = 2,
|
||||
.get_pll_config = r8a7794_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7794_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7794-cpg-mssr",
|
||||
.data = (ulong)&r8a7794_cpg_mssr_info
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r8a7793-cpg-mssr",
|
||||
.data = (ulong)&r8a7794_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7794) = {
|
||||
.name = "clk_r8a7794",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7794_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
|
||||
.ops = &gen2_clk_ops,
|
||||
.probe = gen2_clk_probe,
|
||||
.remove = gen2_clk_remove,
|
||||
};
|
||||
369
drivers/clk/renesas/r8a7795-cpg-mssr.c
Normal file
369
drivers/clk/renesas/r8a7795-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,369 @@
|
|||
/*
|
||||
* Renesas R8A7795 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7795_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
|
||||
|
||||
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7795_mod_clks[] = {
|
||||
DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A7795_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
|
||||
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
|
||||
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
|
||||
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
|
||||
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
|
||||
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
|
||||
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 160, 1, 106, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 1, 128, 1, 84, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
{ 2, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7795_mstp_table[] = {
|
||||
{ 0x00640800, 0x0, 0x00640800, 0 },
|
||||
{ 0xF3EE9390, 0x0, 0xF3EE9390, 0 },
|
||||
{ 0x340FAFDC, 0x2040, 0x340FAFDC, 0 },
|
||||
{ 0xD80C7CDF, 0x400, 0xD80C7CDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0x40BFFF46, 0x0, 0x40BFFF46, 0 },
|
||||
{ 0xE5FBEECF, 0x0, 0xE5FBEECF, 0 },
|
||||
{ 0x39FFFF0E, 0x0, 0x39FFFF0E, 0 },
|
||||
{ 0x01F19FF4, 0x0, 0x01F19FF4, 0 },
|
||||
{ 0xFFDFFFFF, 0x0, 0xFFDFFFFF, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x00000000, 0x0, 0x00000000, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a7795_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
|
||||
.core_clk = r8a7795_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7795_core_clks),
|
||||
.mod_clk = r8a7795_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks),
|
||||
.mstp_table = r8a7795_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table),
|
||||
.reset_node = "renesas,r8a7795-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a7795_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7795_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7795-cpg-mssr",
|
||||
.data = (ulong)&r8a7795_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7795) = {
|
||||
.name = "clk_r8a7795",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7795_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
342
drivers/clk/renesas/r8a7796-cpg-mssr.c
Normal file
342
drivers/clk/renesas/r8a7796-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,342 @@
|
|||
/*
|
||||
* Renesas R8A7796 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7796_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
|
||||
|
||||
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7796_mod_clks[] = {
|
||||
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A7796_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A7796_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A7796_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
|
||||
DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
|
||||
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
|
||||
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 160, 1, 106, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 1, 128, 1, 84, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
{ 2, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7796_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x00200000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a7796_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
|
||||
.core_clk = r8a7796_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
|
||||
.mod_clk = r8a7796_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
|
||||
.mstp_table = r8a7796_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
|
||||
.reset_node = "renesas,r8a7796-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a7796_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7796_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7796-cpg-mssr",
|
||||
.data = (ulong)&r8a7796_cpg_mssr_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7796) = {
|
||||
.name = "clk_r8a7796",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7796_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
233
drivers/clk/renesas/r8a77970-cpg-mssr.c
Normal file
233
drivers/clk/renesas/r8a77970-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,233 @@
|
|||
/*
|
||||
* Renesas R8A77970 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_PLL0D2,
|
||||
CLK_PLL0D3,
|
||||
CLK_PLL0D5,
|
||||
CLK_PLL1D2,
|
||||
CLK_PE,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77970_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
|
||||
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
|
||||
|
||||
DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77970_mod_clks[] = {
|
||||
DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
|
||||
DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
|
||||
DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
|
||||
DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
|
||||
DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
|
||||
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
|
||||
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
|
||||
DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("thermal", 522, R8A77970_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
|
||||
DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
|
||||
DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
|
||||
DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
|
||||
DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz)
|
||||
*-------------------------------------------------
|
||||
* 0 0 0 16.66 x 1 x192 x192 x96
|
||||
* 0 0 1 16.66 x 1 x192 x192 x80
|
||||
* 0 1 0 20 x 1 x160 x160 x80
|
||||
* 0 1 1 20 x 1 x160 x160 x66
|
||||
* 1 0 0 27 / 2 x236 x236 x118
|
||||
* 1 0 1 27 / 2 x236 x236 x98
|
||||
* 1 1 0 33.33 / 2 x192 x192 x96
|
||||
* 1 1 1 33.33 / 2 x192 x192 x80
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 96, 1, },
|
||||
{ 1, 192, 1, 80, 1, },
|
||||
{ 1, 160, 1, 80, 1, },
|
||||
{ 1, 160, 1, 66, 1, },
|
||||
{ 2, 236, 1, 118, 1, },
|
||||
{ 2, 236, 1, 98, 1, },
|
||||
{ 2, 192, 1, 96, 1, },
|
||||
{ 2, 192, 1, 80, 1, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77970_mstp_table[] = {
|
||||
{ 0x00230000, 0x0, 0x00230000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x14062FD8, 0x2040, 0x14062FD8, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
|
||||
{ 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77970_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
|
||||
.core_clk = r8a77970_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77970_core_clks),
|
||||
.mod_clk = r8a77970_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks),
|
||||
.mstp_table = r8a77970_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
|
||||
.reset_node = "renesas,r8a77970-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a77970_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77970_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77970-cpg-mssr",
|
||||
.data = (ulong)&r8a77970_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77970) = {
|
||||
.name = "clk_r8a77970",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77970_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
241
drivers/clk/renesas/r8a77995-cpg-mssr.c
Normal file
241
drivers/clk/renesas/r8a77995-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Renesas R8A77995 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77995_CLK_CP,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL0D2,
|
||||
CLK_PLL0D3,
|
||||
CLK_PLL0D5,
|
||||
CLK_PLL1D2,
|
||||
CLK_PE,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77995_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
|
||||
DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
|
||||
DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
|
||||
DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
|
||||
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
|
||||
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
|
||||
DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
|
||||
|
||||
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
||||
DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("cmt3", 300, R8A77995_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77995_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77995_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77995_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
|
||||
DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A77995_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
|
||||
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
|
||||
DEF_MOD("thermal", 522, R8A77995_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
|
||||
DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
|
||||
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x250/4 x100/3 x100/3
|
||||
* 1 48 x 1 x250/4 x100/3 x116/6
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 116, 6, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77995_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x00200000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77995_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
|
||||
.core_clk = r8a77995_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
|
||||
.mod_clk = r8a77995_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks),
|
||||
.mstp_table = r8a77995_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
|
||||
.reset_node = "renesas,r8a77995-rst",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = ~0,
|
||||
.get_pll_config = r8a77995_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77995_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77995-cpg-mssr",
|
||||
.data = (ulong)&r8a77995_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77995) = {
|
||||
.name = "clk_r8a77995",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77995_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
49
drivers/clk/renesas/rcar-gen2-cpg.h
Normal file
49
drivers/clk/renesas/rcar-gen2-cpg.h
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* R-Car Gen2 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
|
||||
#define __CLK_RENESAS_RCAR_GEN2_CPG_H__
|
||||
|
||||
enum rcar_gen2_clk_types {
|
||||
CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN2_PLL0,
|
||||
CLK_TYPE_GEN2_PLL1,
|
||||
CLK_TYPE_GEN2_PLL3,
|
||||
CLK_TYPE_GEN2_Z,
|
||||
CLK_TYPE_GEN2_LB,
|
||||
CLK_TYPE_GEN2_ADSP,
|
||||
CLK_TYPE_GEN2_SDH,
|
||||
CLK_TYPE_GEN2_SD0,
|
||||
CLK_TYPE_GEN2_SD1,
|
||||
CLK_TYPE_GEN2_QSPI,
|
||||
CLK_TYPE_GEN2_RCAN,
|
||||
};
|
||||
|
||||
struct rcar_gen2_cpg_pll_config {
|
||||
unsigned int extal_div;
|
||||
unsigned int pll1_mult;
|
||||
unsigned int pll3_mult;
|
||||
unsigned int pll0_mult; /* leave as zero if PLL0CR exists */
|
||||
};
|
||||
|
||||
struct gen2_clk_priv {
|
||||
void __iomem *base;
|
||||
struct cpg_mssr_info *info;
|
||||
struct clk clk_extal;
|
||||
struct clk clk_extal_usb;
|
||||
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
|
||||
};
|
||||
|
||||
int gen2_clk_probe(struct udevice *dev);
|
||||
int gen2_clk_remove(struct udevice *dev);
|
||||
|
||||
extern const struct clk_ops gen2_clk_ops;
|
||||
|
||||
#endif
|
||||
60
drivers/clk/renesas/rcar-gen3-cpg.h
Normal file
60
drivers/clk/renesas/rcar-gen3-cpg.h
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* R-Car Gen3 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2015-2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
||||
#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
||||
|
||||
enum rcar_gen3_clk_types {
|
||||
CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN3_PLL0,
|
||||
CLK_TYPE_GEN3_PLL1,
|
||||
CLK_TYPE_GEN3_PLL2,
|
||||
CLK_TYPE_GEN3_PLL3,
|
||||
CLK_TYPE_GEN3_PLL4,
|
||||
CLK_TYPE_GEN3_SD,
|
||||
CLK_TYPE_GEN3_RPC,
|
||||
CLK_TYPE_GEN3_R,
|
||||
CLK_TYPE_GEN3_PE,
|
||||
CLK_TYPE_GEN3_Z2,
|
||||
};
|
||||
|
||||
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
|
||||
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
|
||||
_div_clean) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_FF, \
|
||||
(_parent_clean), .div = (_div_clean), 1)
|
||||
|
||||
struct rcar_gen3_cpg_pll_config {
|
||||
u8 extal_div;
|
||||
u8 pll1_mult;
|
||||
u8 pll1_div;
|
||||
u8 pll3_mult;
|
||||
u8 pll3_div;
|
||||
};
|
||||
|
||||
#define CPG_RCKCR 0x240
|
||||
|
||||
struct gen3_clk_priv {
|
||||
void __iomem *base;
|
||||
struct cpg_mssr_info *info;
|
||||
struct clk clk_extal;
|
||||
struct clk clk_extalr;
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
};
|
||||
|
||||
int gen3_clk_probe(struct udevice *dev);
|
||||
int gen3_clk_remove(struct udevice *dev);
|
||||
|
||||
extern const struct clk_ops gen3_clk_ops;
|
||||
|
||||
#endif
|
||||
175
drivers/clk/renesas/renesas-cpg-mssr.c
Normal file
175
drivers/clk/renesas/renesas-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* Renesas RCar Gen3 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <wait_bit.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
|
||||
/*
|
||||
* Module Standby and Software Reset register offets.
|
||||
*
|
||||
* If the registers exist, these are valid for SH-Mobile, R-Mobile,
|
||||
* R-Car Gen2, R-Car Gen3, and RZ/G1.
|
||||
* These are NOT valid for R-Car Gen1 and RZ/A1!
|
||||
*/
|
||||
|
||||
/*
|
||||
* Module Stop Status Register offsets
|
||||
*/
|
||||
|
||||
static const u16 mstpsr[] = {
|
||||
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
|
||||
0x9A0, 0x9A4, 0x9A8, 0x9AC,
|
||||
};
|
||||
|
||||
#define MSTPSR(i) mstpsr[i]
|
||||
|
||||
|
||||
/*
|
||||
* System Module Stop Control Register offsets
|
||||
*/
|
||||
|
||||
static const u16 smstpcr[] = {
|
||||
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
|
||||
0x990, 0x994, 0x998, 0x99C,
|
||||
};
|
||||
|
||||
#define SMSTPCR(i) smstpcr[i]
|
||||
|
||||
|
||||
/* Realtime Module Stop Control Register offsets */
|
||||
#define RMSTPCR(i) (smstpcr[i] - 0x20)
|
||||
|
||||
/* Modem Module Stop Control Register offsets (r8a73a4) */
|
||||
#define MMSTPCR(i) (smstpcr[i] + 0x20)
|
||||
|
||||
/* Software Reset Clearing Register offsets */
|
||||
#define SRSTCLR(i) (0x940 + (i) * 4)
|
||||
|
||||
bool renesas_clk_is_mod(struct clk *clk)
|
||||
{
|
||||
return (clk->id >> 16) == CPG_MOD;
|
||||
}
|
||||
|
||||
int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
|
||||
const struct mssr_mod_clk **mssr)
|
||||
{
|
||||
const unsigned long clkid = clk->id & 0xffff;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < info->mod_clk_size; i++) {
|
||||
if (info->mod_clk[i].id !=
|
||||
(info->mod_clk_base + MOD_CLK_PACK(clkid)))
|
||||
continue;
|
||||
|
||||
*mssr = &info->mod_clk[i];
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
|
||||
const struct cpg_core_clk **core)
|
||||
{
|
||||
const unsigned long clkid = clk->id & 0xffff;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < info->core_clk_size; i++) {
|
||||
if (info->core_clk[i].id != clkid)
|
||||
continue;
|
||||
|
||||
*core = &info->core_clk[i];
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
|
||||
struct clk *parent)
|
||||
{
|
||||
const struct cpg_core_clk *core;
|
||||
const struct mssr_mod_clk *mssr;
|
||||
int ret;
|
||||
|
||||
if (renesas_clk_is_mod(clk)) {
|
||||
ret = renesas_clk_get_mod(clk, info, &mssr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
parent->id = mssr->parent;
|
||||
} else {
|
||||
ret = renesas_clk_get_core(clk, info, &core);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (core->type == CLK_TYPE_IN)
|
||||
parent->id = ~0; /* Top-level clock */
|
||||
else
|
||||
parent->id = core->parent;
|
||||
}
|
||||
|
||||
parent->dev = clk->dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
|
||||
{
|
||||
const unsigned long clkid = clk->id & 0xffff;
|
||||
const unsigned int reg = clkid / 100;
|
||||
const unsigned int bit = clkid % 100;
|
||||
const u32 bitmask = BIT(bit);
|
||||
|
||||
if (!renesas_clk_is_mod(clk))
|
||||
return -EINVAL;
|
||||
|
||||
debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
|
||||
clkid, reg, bit, enable ? "ON" : "OFF");
|
||||
|
||||
if (enable) {
|
||||
clrbits_le32(base + SMSTPCR(reg), bitmask);
|
||||
return wait_for_bit_le32(base + MSTPSR(reg),
|
||||
bitmask, 0, 100, 0);
|
||||
} else {
|
||||
setbits_le32(base + SMSTPCR(reg), bitmask);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* Stop TMU0 */
|
||||
clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
|
||||
|
||||
/* Stop module clock */
|
||||
for (i = 0; i < info->mstp_table_size; i++) {
|
||||
clrsetbits_le32(base + SMSTPCR(i),
|
||||
info->mstp_table[i].sdis,
|
||||
info->mstp_table[i].sen);
|
||||
clrsetbits_le32(base + RMSTPCR(i),
|
||||
info->mstp_table[i].rdis,
|
||||
info->mstp_table[i].ren);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
117
drivers/clk/renesas/renesas-cpg-mssr.h
Normal file
117
drivers/clk/renesas/renesas-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* Renesas RCar Gen3 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
|
||||
#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
|
||||
|
||||
struct cpg_mssr_info {
|
||||
const struct cpg_core_clk *core_clk;
|
||||
unsigned int core_clk_size;
|
||||
const struct mssr_mod_clk *mod_clk;
|
||||
unsigned int mod_clk_size;
|
||||
const struct mstp_stop_table *mstp_table;
|
||||
unsigned int mstp_table_size;
|
||||
const char *reset_node;
|
||||
const char *extalr_node;
|
||||
const char *extal_usb_node;
|
||||
unsigned int mod_clk_base;
|
||||
unsigned int clk_extal_id;
|
||||
unsigned int clk_extalr_id;
|
||||
unsigned int clk_extal_usb_id;
|
||||
unsigned int pll0_div;
|
||||
const void *(*get_pll_config)(const u32 cpg_mode);
|
||||
};
|
||||
|
||||
/*
|
||||
* Definitions of CPG Core Clocks
|
||||
*
|
||||
* These include:
|
||||
* - Clock outputs exported to DT
|
||||
* - External input clocks
|
||||
* - Internal CPG clocks
|
||||
*/
|
||||
struct cpg_core_clk {
|
||||
/* Common */
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int type;
|
||||
/* Depending on type */
|
||||
unsigned int parent; /* Core Clocks only */
|
||||
unsigned int div;
|
||||
unsigned int mult;
|
||||
unsigned int offset;
|
||||
};
|
||||
|
||||
enum clk_types {
|
||||
/* Generic */
|
||||
CLK_TYPE_IN, /* External Clock Input */
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
|
||||
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
|
||||
|
||||
/* Custom definitions start here */
|
||||
CLK_TYPE_CUSTOM,
|
||||
};
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
{ .name = _name, .id = _id, .type = _type }
|
||||
#define DEF_BASE(_name, _id, _type, _parent...) \
|
||||
DEF_TYPE(_name, _id, _type, .parent = _parent)
|
||||
|
||||
#define DEF_INPUT(_name, _id) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_IN)
|
||||
#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
|
||||
#define DEF_DIV6P1(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
|
||||
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
|
||||
|
||||
/*
|
||||
* Definitions of Module Clocks
|
||||
*/
|
||||
struct mssr_mod_clk {
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
|
||||
};
|
||||
|
||||
/* Convert from sparse base-100 to packed index space */
|
||||
#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
|
||||
|
||||
#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
|
||||
|
||||
#define DEF_MOD(_name, _mod, _parent...) \
|
||||
{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
|
||||
|
||||
struct mstp_stop_table {
|
||||
u32 sdis;
|
||||
u32 sen;
|
||||
u32 rdis;
|
||||
u32 ren;
|
||||
};
|
||||
|
||||
#define TSTR0 0x04
|
||||
#define TSTR0_STR0 BIT(0)
|
||||
|
||||
bool renesas_clk_is_mod(struct clk *clk);
|
||||
int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
|
||||
const struct mssr_mod_clk **mssr);
|
||||
int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
|
||||
const struct cpg_core_clk **core);
|
||||
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
|
||||
struct clk *parent);
|
||||
int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
|
||||
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
|
||||
|
||||
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
|
||||
|
|
@ -176,6 +176,7 @@ static const struct udevice_id rcar_gpio_ids[] = {
|
|||
{ .compatible = "renesas,gpio-r8a7796" },
|
||||
{ .compatible = "renesas,gpio-r8a77970" },
|
||||
{ .compatible = "renesas,gpio-r8a77995" },
|
||||
{ .compatible = "renesas,rcar-gen2-gpio" },
|
||||
{ .compatible = "renesas,rcar-gen3-gpio" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -438,7 +438,7 @@ static int ravb_config(struct udevice *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int ravb_start(struct udevice *dev)
|
||||
static int ravb_start(struct udevice *dev)
|
||||
{
|
||||
struct ravb_priv *eth = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,13 @@
|
|||
#include <linux/errno.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_DM_ETH
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <linux/mii.h>
|
||||
#include <asm/gpio.h>
|
||||
#endif
|
||||
|
||||
#include "sh_eth.h"
|
||||
|
||||
#ifndef CONFIG_SH_ETHER_USE_PORT
|
||||
|
|
@ -54,9 +61,8 @@
|
|||
|
||||
#define TIMEOUT_CNT 1000
|
||||
|
||||
int sh_eth_send(struct eth_device *dev, void *packet, int len)
|
||||
static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
|
||||
{
|
||||
struct sh_eth_dev *eth = dev->priv;
|
||||
int port = eth->port, ret = 0, timeout;
|
||||
struct sh_eth_info *port_info = ð->port_info[port];
|
||||
|
||||
|
|
@ -112,48 +118,45 @@ err:
|
|||
return ret;
|
||||
}
|
||||
|
||||
int sh_eth_recv(struct eth_device *dev)
|
||||
static int sh_eth_recv_start(struct sh_eth_dev *eth)
|
||||
{
|
||||
struct sh_eth_dev *eth = dev->priv;
|
||||
int port = eth->port, len = 0;
|
||||
struct sh_eth_info *port_info = ð->port_info[port];
|
||||
uchar *packet;
|
||||
|
||||
/* Check if the rx descriptor is ready */
|
||||
invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
|
||||
if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
|
||||
/* Check for errors */
|
||||
if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
|
||||
len = port_info->rx_desc_cur->rd1 & 0xffff;
|
||||
packet = (uchar *)
|
||||
ADDR_TO_P2(port_info->rx_desc_cur->rd2);
|
||||
invalidate_cache(packet, len);
|
||||
net_process_received_packet(packet, len);
|
||||
}
|
||||
if (port_info->rx_desc_cur->rd0 & RD_RACT)
|
||||
return -EINVAL;
|
||||
|
||||
/* Make current descriptor available again */
|
||||
if (port_info->rx_desc_cur->rd0 & RD_RDLE)
|
||||
port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
|
||||
else
|
||||
port_info->rx_desc_cur->rd0 = RD_RACT;
|
||||
/* Check for errors */
|
||||
if (port_info->rx_desc_cur->rd0 & RD_RFE)
|
||||
return -EINVAL;
|
||||
|
||||
flush_cache_wback(port_info->rx_desc_cur,
|
||||
sizeof(struct rx_desc_s));
|
||||
|
||||
/* Point to the next descriptor */
|
||||
port_info->rx_desc_cur++;
|
||||
if (port_info->rx_desc_cur >=
|
||||
port_info->rx_desc_base + NUM_RX_DESC)
|
||||
port_info->rx_desc_cur = port_info->rx_desc_base;
|
||||
}
|
||||
|
||||
/* Restart the receiver if disabled */
|
||||
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
||||
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
||||
len = port_info->rx_desc_cur->rd1 & 0xffff;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static void sh_eth_recv_finish(struct sh_eth_dev *eth)
|
||||
{
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
|
||||
/* Make current descriptor available again */
|
||||
if (port_info->rx_desc_cur->rd0 & RD_RDLE)
|
||||
port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
|
||||
else
|
||||
port_info->rx_desc_cur->rd0 = RD_RACT;
|
||||
|
||||
flush_cache_wback(port_info->rx_desc_cur,
|
||||
sizeof(struct rx_desc_s));
|
||||
|
||||
/* Point to the next descriptor */
|
||||
port_info->rx_desc_cur++;
|
||||
if (port_info->rx_desc_cur >=
|
||||
port_info->rx_desc_base + NUM_RX_DESC)
|
||||
port_info->rx_desc_cur = port_info->rx_desc_base;
|
||||
}
|
||||
|
||||
static int sh_eth_reset(struct sh_eth_dev *eth)
|
||||
{
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
|
|
@ -360,29 +363,21 @@ err_tx_init:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int sh_eth_phy_config(struct sh_eth_dev *eth)
|
||||
static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
|
||||
unsigned char *mac)
|
||||
{
|
||||
int port = eth->port, ret = 0;
|
||||
struct sh_eth_info *port_info = ð->port_info[port];
|
||||
struct eth_device *dev = port_info->dev;
|
||||
struct phy_device *phydev;
|
||||
u32 val;
|
||||
|
||||
phydev = phy_connect(
|
||||
miiphy_get_dev_by_name(dev->name),
|
||||
port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
|
||||
port_info->phydev = phydev;
|
||||
phy_config(phydev);
|
||||
val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
|
||||
sh_eth_write(port_info, val, MAHR);
|
||||
|
||||
return ret;
|
||||
val = (mac[4] << 8) | mac[5];
|
||||
sh_eth_write(port_info, val, MALR);
|
||||
}
|
||||
|
||||
static int sh_eth_config(struct sh_eth_dev *eth)
|
||||
static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
|
||||
{
|
||||
int port = eth->port, ret = 0;
|
||||
u32 val;
|
||||
struct sh_eth_info *port_info = ð->port_info[port];
|
||||
struct eth_device *dev = port_info->dev;
|
||||
struct phy_device *phy;
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
|
||||
/* Configure e-dmac registers */
|
||||
sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
|
||||
|
|
@ -402,12 +397,7 @@ static int sh_eth_config(struct sh_eth_dev *eth)
|
|||
sh_eth_write(port_info, 0, ECSIPR);
|
||||
|
||||
/* Set Mac address */
|
||||
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
|
||||
dev->enetaddr[2] << 8 | dev->enetaddr[3];
|
||||
sh_eth_write(port_info, val, MAHR);
|
||||
|
||||
val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
|
||||
sh_eth_write(port_info, val, MALR);
|
||||
sh_eth_write_hwaddr(port_info, mac);
|
||||
|
||||
sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
|
||||
#if defined(SH_ETH_TYPE_GETHER)
|
||||
|
|
@ -421,24 +411,17 @@ static int sh_eth_config(struct sh_eth_dev *eth)
|
|||
|
||||
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
|
||||
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
|
||||
#endif
|
||||
/* Configure phy */
|
||||
ret = sh_eth_phy_config(eth);
|
||||
if (ret) {
|
||||
printf(SHETHER_NAME ": phy config timeout\n");
|
||||
goto err_phy_cfg;
|
||||
}
|
||||
phy = port_info->phydev;
|
||||
ret = phy_startup(phy);
|
||||
if (ret) {
|
||||
printf(SHETHER_NAME ": phy startup failure\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
val = 0;
|
||||
static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
|
||||
{
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
struct phy_device *phy = port_info->phydev;
|
||||
int ret = 0;
|
||||
u32 val = 0;
|
||||
|
||||
/* Set the transfer speed */
|
||||
if (phy->speed == 100) {
|
||||
|
|
@ -447,9 +430,7 @@ static int sh_eth_config(struct sh_eth_dev *eth)
|
|||
sh_eth_write(port_info, GECMR_100B, GECMR);
|
||||
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
|
||||
sh_eth_write(port_info, 1, RTRATE);
|
||||
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
|
||||
defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
|
||||
defined(CONFIG_R8A7794)
|
||||
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
|
||||
val = ECMR_RTM;
|
||||
#endif
|
||||
} else if (phy->speed == 10) {
|
||||
|
|
@ -481,9 +462,6 @@ static int sh_eth_config(struct sh_eth_dev *eth)
|
|||
}
|
||||
|
||||
return ret;
|
||||
|
||||
err_phy_cfg:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sh_eth_start(struct sh_eth_dev *eth)
|
||||
|
|
@ -504,36 +482,123 @@ static void sh_eth_stop(struct sh_eth_dev *eth)
|
|||
sh_eth_write(port_info, ~EDRRR_R, EDRRR);
|
||||
}
|
||||
|
||||
int sh_eth_init(struct eth_device *dev, bd_t *bd)
|
||||
static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
|
||||
{
|
||||
int ret = 0;
|
||||
struct sh_eth_dev *eth = dev->priv;
|
||||
|
||||
ret = sh_eth_reset(eth);
|
||||
if (ret)
|
||||
goto err;
|
||||
return ret;
|
||||
|
||||
ret = sh_eth_desc_init(eth);
|
||||
if (ret)
|
||||
goto err;
|
||||
return ret;
|
||||
|
||||
ret = sh_eth_config(eth);
|
||||
sh_eth_mac_regs_config(eth, mac);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_eth_start_common(struct sh_eth_dev *eth)
|
||||
{
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
int ret;
|
||||
|
||||
ret = phy_startup(port_info->phydev);
|
||||
if (ret) {
|
||||
printf(SHETHER_NAME ": phy startup failure\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = sh_eth_phy_regs_config(eth);
|
||||
if (ret)
|
||||
goto err_config;
|
||||
return ret;
|
||||
|
||||
sh_eth_start(eth);
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
err_config:
|
||||
sh_eth_tx_desc_free(eth);
|
||||
sh_eth_rx_desc_free(eth);
|
||||
#ifndef CONFIG_DM_ETH
|
||||
static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
|
||||
{
|
||||
int port = eth->port, ret = 0;
|
||||
struct sh_eth_info *port_info = ð->port_info[port];
|
||||
struct eth_device *dev = port_info->dev;
|
||||
struct phy_device *phydev;
|
||||
|
||||
phydev = phy_connect(
|
||||
miiphy_get_dev_by_name(dev->name),
|
||||
port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
|
||||
port_info->phydev = phydev;
|
||||
phy_config(phydev);
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void sh_eth_halt(struct eth_device *dev)
|
||||
static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
|
||||
{
|
||||
struct sh_eth_dev *eth = dev->priv;
|
||||
|
||||
return sh_eth_send_common(eth, packet, len);
|
||||
}
|
||||
|
||||
static int sh_eth_recv_common(struct sh_eth_dev *eth)
|
||||
{
|
||||
int port = eth->port, len = 0;
|
||||
struct sh_eth_info *port_info = ð->port_info[port];
|
||||
uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
|
||||
|
||||
len = sh_eth_recv_start(eth);
|
||||
if (len > 0) {
|
||||
invalidate_cache(packet, len);
|
||||
net_process_received_packet(packet, len);
|
||||
sh_eth_recv_finish(eth);
|
||||
} else
|
||||
len = 0;
|
||||
|
||||
/* Restart the receiver if disabled */
|
||||
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
||||
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static int sh_eth_recv_legacy(struct eth_device *dev)
|
||||
{
|
||||
struct sh_eth_dev *eth = dev->priv;
|
||||
|
||||
return sh_eth_recv_common(eth);
|
||||
}
|
||||
|
||||
static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
|
||||
{
|
||||
struct sh_eth_dev *eth = dev->priv;
|
||||
int ret;
|
||||
|
||||
ret = sh_eth_init_common(eth, dev->enetaddr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = sh_eth_phy_config_legacy(eth);
|
||||
if (ret) {
|
||||
printf(SHETHER_NAME ": phy config timeout\n");
|
||||
goto err_start;
|
||||
}
|
||||
|
||||
ret = sh_eth_start_common(eth);
|
||||
if (ret)
|
||||
goto err_start;
|
||||
|
||||
return 0;
|
||||
|
||||
err_start:
|
||||
sh_eth_tx_desc_free(eth);
|
||||
sh_eth_rx_desc_free(eth);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void sh_eth_halt_legacy(struct eth_device *dev)
|
||||
{
|
||||
struct sh_eth_dev *eth = dev->priv;
|
||||
|
||||
|
|
@ -570,10 +635,10 @@ int sh_eth_initialize(bd_t *bd)
|
|||
|
||||
dev->priv = (void *)eth;
|
||||
dev->iobase = 0;
|
||||
dev->init = sh_eth_init;
|
||||
dev->halt = sh_eth_halt;
|
||||
dev->send = sh_eth_send;
|
||||
dev->recv = sh_eth_recv;
|
||||
dev->init = sh_eth_init_legacy;
|
||||
dev->halt = sh_eth_halt_legacy;
|
||||
dev->send = sh_eth_send_legacy;
|
||||
dev->recv = sh_eth_recv_legacy;
|
||||
eth->port_info[eth->port].dev = dev;
|
||||
|
||||
strcpy(dev->name, SHETHER_NAME);
|
||||
|
|
@ -609,6 +674,266 @@ err:
|
|||
return ret;
|
||||
}
|
||||
|
||||
#else /* CONFIG_DM_ETH */
|
||||
|
||||
struct sh_ether_priv {
|
||||
struct sh_eth_dev shdev;
|
||||
|
||||
struct mii_dev *bus;
|
||||
void __iomem *iobase;
|
||||
struct clk clk;
|
||||
struct gpio_desc reset_gpio;
|
||||
};
|
||||
|
||||
static int sh_ether_send(struct udevice *dev, void *packet, int len)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
|
||||
return sh_eth_send_common(eth, packet, len);
|
||||
}
|
||||
|
||||
static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
|
||||
int len;
|
||||
|
||||
len = sh_eth_recv_start(eth);
|
||||
if (len > 0) {
|
||||
invalidate_cache(packet, len);
|
||||
*packetp = packet;
|
||||
|
||||
return len;
|
||||
} else {
|
||||
len = 0;
|
||||
|
||||
/* Restart the receiver if disabled */
|
||||
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
||||
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
||||
|
||||
return -EAGAIN;
|
||||
}
|
||||
}
|
||||
|
||||
static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
|
||||
sh_eth_recv_finish(eth);
|
||||
|
||||
/* Restart the receiver if disabled */
|
||||
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
||||
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_ether_write_hwaddr(struct udevice *dev)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
|
||||
sh_eth_write_hwaddr(port_info, pdata->enetaddr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_eth_phy_config(struct udevice *dev)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
int port = eth->port, ret = 0;
|
||||
struct sh_eth_info *port_info = ð->port_info[port];
|
||||
struct phy_device *phydev;
|
||||
int mask = 0xffffffff;
|
||||
|
||||
phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
|
||||
if (!phydev)
|
||||
return -ENODEV;
|
||||
|
||||
phy_connect_dev(phydev, dev);
|
||||
|
||||
port_info->phydev = phydev;
|
||||
phy_config(phydev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sh_ether_start(struct udevice *dev)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(&priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = sh_eth_init_common(eth, pdata->enetaddr);
|
||||
if (ret)
|
||||
goto err_clk;
|
||||
|
||||
ret = sh_eth_phy_config(dev);
|
||||
if (ret) {
|
||||
printf(SHETHER_NAME ": phy config timeout\n");
|
||||
goto err_start;
|
||||
}
|
||||
|
||||
ret = sh_eth_start_common(eth);
|
||||
if (ret)
|
||||
goto err_start;
|
||||
|
||||
return 0;
|
||||
|
||||
err_start:
|
||||
sh_eth_tx_desc_free(eth);
|
||||
sh_eth_rx_desc_free(eth);
|
||||
err_clk:
|
||||
clk_disable(&priv->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sh_ether_stop(struct udevice *dev)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
|
||||
sh_eth_stop(&priv->shdev);
|
||||
clk_disable(&priv->clk);
|
||||
}
|
||||
|
||||
static int sh_ether_probe(struct udevice *udev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_platdata(udev);
|
||||
struct sh_ether_priv *priv = dev_get_priv(udev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
struct mii_dev *mdiodev;
|
||||
void __iomem *iobase;
|
||||
int ret;
|
||||
|
||||
iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
|
||||
priv->iobase = iobase;
|
||||
|
||||
ret = clk_get_by_index(udev, 0, &priv->clk);
|
||||
if (ret < 0)
|
||||
goto err_mdio_alloc;
|
||||
|
||||
gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
|
||||
GPIOD_IS_OUT);
|
||||
|
||||
mdiodev = mdio_alloc();
|
||||
if (!mdiodev) {
|
||||
ret = -ENOMEM;
|
||||
goto err_mdio_alloc;
|
||||
}
|
||||
|
||||
mdiodev->read = bb_miiphy_read;
|
||||
mdiodev->write = bb_miiphy_write;
|
||||
bb_miiphy_buses[0].priv = eth;
|
||||
snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
|
||||
|
||||
ret = mdio_register(mdiodev);
|
||||
if (ret < 0)
|
||||
goto err_mdio_register;
|
||||
|
||||
priv->bus = miiphy_get_dev_by_name(udev->name);
|
||||
|
||||
eth->port = CONFIG_SH_ETHER_USE_PORT;
|
||||
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
|
||||
eth->port_info[eth->port].iobase =
|
||||
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
|
||||
|
||||
return 0;
|
||||
|
||||
err_mdio_register:
|
||||
mdio_free(mdiodev);
|
||||
err_mdio_alloc:
|
||||
unmap_physmem(priv->iobase, MAP_NOCACHE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sh_ether_remove(struct udevice *udev)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(udev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
|
||||
free(port_info->phydev);
|
||||
mdio_unregister(priv->bus);
|
||||
mdio_free(priv->bus);
|
||||
|
||||
if (dm_gpio_is_valid(&priv->reset_gpio))
|
||||
dm_gpio_free(udev, &priv->reset_gpio);
|
||||
|
||||
unmap_physmem(priv->iobase, MAP_NOCACHE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct eth_ops sh_ether_ops = {
|
||||
.start = sh_ether_start,
|
||||
.send = sh_ether_send,
|
||||
.recv = sh_ether_recv,
|
||||
.free_pkt = sh_ether_free_pkt,
|
||||
.stop = sh_ether_stop,
|
||||
.write_hwaddr = sh_ether_write_hwaddr,
|
||||
};
|
||||
|
||||
int sh_ether_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
const char *phy_mode;
|
||||
const fdt32_t *cell;
|
||||
int ret = 0;
|
||||
|
||||
pdata->iobase = devfdt_get_addr(dev);
|
||||
pdata->phy_interface = -1;
|
||||
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
|
||||
NULL);
|
||||
if (phy_mode)
|
||||
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
||||
if (pdata->phy_interface == -1) {
|
||||
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pdata->max_speed = 1000;
|
||||
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
|
||||
if (cell)
|
||||
pdata->max_speed = fdt32_to_cpu(*cell);
|
||||
|
||||
sprintf(bb_miiphy_buses[0].name, dev->name);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct udevice_id sh_ether_ids[] = {
|
||||
{ .compatible = "renesas,ether-r8a7791" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(eth_sh_ether) = {
|
||||
.name = "sh_ether",
|
||||
.id = UCLASS_ETH,
|
||||
.of_match = sh_ether_ids,
|
||||
.ofdata_to_platdata = sh_ether_ofdata_to_platdata,
|
||||
.probe = sh_ether_probe,
|
||||
.remove = sh_ether_remove,
|
||||
.ops = &sh_ether_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct sh_ether_priv),
|
||||
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
||||
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
||||
};
|
||||
#endif
|
||||
|
||||
/******* for bb_miiphy *******/
|
||||
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -302,8 +302,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
|
|||
#elif defined(CONFIG_R8A7740)
|
||||
#define SH_ETH_TYPE_GETHER
|
||||
#define BASE_IO_ADDR 0xE9A00000
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
#define SH_ETH_TYPE_ETHER
|
||||
#define BASE_IO_ADDR 0xEE700200
|
||||
#elif defined(CONFIG_R7S72100)
|
||||
|
|
@ -514,8 +513,7 @@ enum FELIC_MODE_BIT {
|
|||
ECMR_PRM = 0x00000001,
|
||||
#ifdef CONFIG_CPU_SH7724
|
||||
ECMR_RTM = 0x00000010,
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
ECMR_RTM = 0x00000004,
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -50,6 +50,15 @@ config PCIE_DW_MVEBU
|
|||
Armada-8K SoCs. The PCIe controller on Armada-8K is based on
|
||||
DesignWare hardware.
|
||||
|
||||
config PCI_RCAR_GEN2
|
||||
bool "Renesas RCar Gen2 PCIe driver"
|
||||
depends on DM_PCI
|
||||
depends on RCAR_32
|
||||
help
|
||||
Say Y here if you want to enable PCIe controller support on
|
||||
Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
|
||||
also used to access EHCI USB controller on the SoC.
|
||||
|
||||
config PCI_SANDBOX
|
||||
bool "Sandbox PCI support"
|
||||
depends on SANDBOX && DM_PCI
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
|
|||
obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
|
||||
obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
|
||||
obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
|
||||
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
|
||||
obj-$(CONFIG_SH4_PCI) += pci_sh4.o
|
||||
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
|
||||
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
|
||||
|
|
|
|||
264
drivers/pci/pci-rcar-gen2.c
Normal file
264
drivers/pci/pci-rcar-gen2.c
Normal file
|
|
@ -0,0 +1,264 @@
|
|||
/*
|
||||
* Renesas RCar Gen2 PCIEC driver
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <pci.h>
|
||||
|
||||
/* AHB-PCI Bridge PCI communication registers */
|
||||
#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
|
||||
|
||||
#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
|
||||
#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
|
||||
#define RCAR_PCIAHB_PREFETCH0 0x0
|
||||
#define RCAR_PCIAHB_PREFETCH4 0x1
|
||||
#define RCAR_PCIAHB_PREFETCH8 0x2
|
||||
#define RCAR_PCIAHB_PREFETCH16 0x3
|
||||
|
||||
#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
|
||||
#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
|
||||
#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
|
||||
#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
|
||||
#define RCAR_AHBPCI_WIN1_HOST BIT(30)
|
||||
#define RCAR_AHBPCI_WIN1_DEVICE BIT(31)
|
||||
|
||||
#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
|
||||
#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
|
||||
#define RCAR_PCI_INT_SIGTABORT BIT(0)
|
||||
#define RCAR_PCI_INT_SIGRETABORT BIT(1)
|
||||
#define RCAR_PCI_INT_REMABORT BIT(2)
|
||||
#define RCAR_PCI_INT_PERR BIT(3)
|
||||
#define RCAR_PCI_INT_SIGSERR BIT(4)
|
||||
#define RCAR_PCI_INT_RESERR BIT(5)
|
||||
#define RCAR_PCI_INT_WIN1ERR BIT(12)
|
||||
#define RCAR_PCI_INT_WIN2ERR BIT(13)
|
||||
#define RCAR_PCI_INT_A BIT(16)
|
||||
#define RCAR_PCI_INT_B BIT(17)
|
||||
#define RCAR_PCI_INT_PME BIT(19)
|
||||
#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
|
||||
RCAR_PCI_INT_SIGRETABORT | \
|
||||
RCAR_PCI_INT_SIGRETABORT | \
|
||||
RCAR_PCI_INT_REMABORT | \
|
||||
RCAR_PCI_INT_PERR | \
|
||||
RCAR_PCI_INT_SIGSERR | \
|
||||
RCAR_PCI_INT_RESERR | \
|
||||
RCAR_PCI_INT_WIN1ERR | \
|
||||
RCAR_PCI_INT_WIN2ERR)
|
||||
|
||||
#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
|
||||
#define RCAR_AHB_BUS_MMODE_HTRANS BIT(0)
|
||||
#define RCAR_AHB_BUS_MMODE_BYTE_BURST BIT(1)
|
||||
#define RCAR_AHB_BUS_MMODE_WR_INCR BIT(2)
|
||||
#define RCAR_AHB_BUS_MMODE_HBUS_REQ BIT(7)
|
||||
#define RCAR_AHB_BUS_SMODE_READYCTR BIT(17)
|
||||
#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
|
||||
RCAR_AHB_BUS_MMODE_BYTE_BURST | \
|
||||
RCAR_AHB_BUS_MMODE_WR_INCR | \
|
||||
RCAR_AHB_BUS_MMODE_HBUS_REQ | \
|
||||
RCAR_AHB_BUS_SMODE_READYCTR)
|
||||
|
||||
#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
|
||||
#define RCAR_USBCTR_USBH_RST BIT(0)
|
||||
#define RCAR_USBCTR_PCICLK_MASK BIT(1)
|
||||
#define RCAR_USBCTR_PLL_RST BIT(2)
|
||||
#define RCAR_USBCTR_DIRPD BIT(8)
|
||||
#define RCAR_USBCTR_PCIAHB_WIN2_EN BIT(9)
|
||||
#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
|
||||
#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
|
||||
#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
|
||||
#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
|
||||
#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
|
||||
|
||||
#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
|
||||
#define RCAR_PCI_ARBITER_PCIREQ0 BIT(0)
|
||||
#define RCAR_PCI_ARBITER_PCIREQ1 BIT(1)
|
||||
#define RCAR_PCI_ARBITER_PCIBP_MODE BIT(12)
|
||||
|
||||
#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
|
||||
|
||||
struct rcar_gen2_pci_priv {
|
||||
fdt_addr_t cfg_base;
|
||||
fdt_addr_t mem_base;
|
||||
};
|
||||
|
||||
static int rcar_gen2_pci_addr_valid(pci_dev_t d, uint offset)
|
||||
{
|
||||
u32 slot;
|
||||
|
||||
if (PCI_FUNC(d))
|
||||
return -EINVAL;
|
||||
|
||||
/* Only one EHCI/OHCI device built-in */
|
||||
slot = PCI_DEV(d);
|
||||
if (slot > 2)
|
||||
return -EINVAL;
|
||||
|
||||
/* bridge logic only has registers to 0x40 */
|
||||
if (slot == 0x0 && offset >= 0x40)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 get_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
|
||||
{
|
||||
struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return priv->cfg_base + (PCI_DEV(bdf) >> 1) * 0x100 + (offset & ~3);
|
||||
}
|
||||
|
||||
static u32 setup_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
|
||||
{
|
||||
struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
|
||||
u32 reg;
|
||||
|
||||
reg = PCI_DEV(bdf) ? RCAR_AHBPCI_WIN1_DEVICE : RCAR_AHBPCI_WIN1_HOST;
|
||||
reg |= RCAR_AHBPCI_WIN_CTR_CFG;
|
||||
writel(reg, priv->cfg_base + RCAR_AHBPCI_WIN1_CTR_REG);
|
||||
|
||||
return get_bus_address(dev, bdf, offset);
|
||||
}
|
||||
|
||||
static int rcar_gen2_pci_read_config(struct udevice *dev, pci_dev_t bdf,
|
||||
uint offset, ulong *value,
|
||||
enum pci_size_t size)
|
||||
{
|
||||
u32 addr, reg;
|
||||
int ret;
|
||||
|
||||
ret = rcar_gen2_pci_addr_valid(bdf, offset);
|
||||
if (ret) {
|
||||
*value = pci_get_ff(size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
addr = get_bus_address(dev, bdf, offset);
|
||||
reg = readl(addr);
|
||||
*value = pci_conv_32_to_size(reg, offset, size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_gen2_pci_write_config(struct udevice *dev, pci_dev_t bdf,
|
||||
uint offset, ulong value,
|
||||
enum pci_size_t size)
|
||||
{
|
||||
u32 addr, reg, old;
|
||||
int ret;
|
||||
|
||||
ret = rcar_gen2_pci_addr_valid(bdf, offset);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
addr = get_bus_address(dev, bdf, offset);
|
||||
|
||||
old = readl(addr);
|
||||
reg = pci_conv_size_to_32(old, value, offset, size);
|
||||
writel(reg, addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_gen2_pci_probe(struct udevice *dev)
|
||||
{
|
||||
struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
|
||||
struct clk pci_clk;
|
||||
u32 devad;
|
||||
int ret;
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &pci_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(&pci_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Clock & Reset & Direct Power Down */
|
||||
clrsetbits_le32(priv->cfg_base + RCAR_USBCTR_REG,
|
||||
RCAR_USBCTR_DIRPD | RCAR_USBCTR_PCICLK_MASK |
|
||||
RCAR_USBCTR_USBH_RST,
|
||||
RCAR_USBCTR_PCIAHB_WIN1_1G);
|
||||
clrbits_le32(priv->cfg_base + RCAR_USBCTR_REG, RCAR_USBCTR_PLL_RST);
|
||||
|
||||
/* AHB-PCI Bridge Communication Registers */
|
||||
writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
|
||||
writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
|
||||
priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
|
||||
writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
|
||||
priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
|
||||
writel(priv->mem_base | RCAR_AHBPCI_WIN_CTR_MEM,
|
||||
priv->cfg_base + RCAR_AHBPCI_WIN2_CTR_REG);
|
||||
setbits_le32(priv->cfg_base + RCAR_PCI_ARBITER_CTR_REG,
|
||||
RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
|
||||
RCAR_PCI_ARBITER_PCIBP_MODE);
|
||||
|
||||
/* PCI Configuration Registers for AHBPCI */
|
||||
devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
|
||||
writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
|
||||
writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
|
||||
writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
|
||||
writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
|
||||
devad + PCI_COMMAND);
|
||||
|
||||
/* PCI Configuration Registers for OHCI */
|
||||
devad = setup_bus_address(dev, PCI_BDF(0, 1, 0), 0);
|
||||
writel(priv->mem_base + 0x0, devad + PCI_BASE_ADDRESS_0);
|
||||
writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
|
||||
devad + PCI_COMMAND);
|
||||
|
||||
/* PCI Configuration Registers for EHCI */
|
||||
devad = setup_bus_address(dev, PCI_BDF(0, 2, 0), 0);
|
||||
writel(priv->mem_base + 0x1000, devad + PCI_BASE_ADDRESS_0);
|
||||
writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
|
||||
devad + PCI_COMMAND);
|
||||
|
||||
/* Enable PCI interrupt */
|
||||
setbits_le32(priv->cfg_base + RCAR_PCI_INT_ENABLE_REG,
|
||||
RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_gen2_pci_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->cfg_base = devfdt_get_addr_index(dev, 0);
|
||||
priv->mem_base = devfdt_get_addr_index(dev, 1);
|
||||
if (!priv->cfg_base || !priv->mem_base)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops rcar_gen2_pci_ops = {
|
||||
.read_config = rcar_gen2_pci_read_config,
|
||||
.write_config = rcar_gen2_pci_write_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id rcar_gen2_pci_ids[] = {
|
||||
{ .compatible = "renesas,pci-rcar-gen2" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rcar_gen2_pci) = {
|
||||
.name = "rcar_gen2_pci",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = rcar_gen2_pci_ids,
|
||||
.ops = &rcar_gen2_pci_ops,
|
||||
.probe = rcar_gen2_pci_probe,
|
||||
.ofdata_to_platdata = rcar_gen2_pci_ofdata_to_platdata,
|
||||
.priv_auto_alloc_size = sizeof(struct rcar_gen2_pci_priv),
|
||||
};
|
||||
|
|
@ -6,6 +6,61 @@ config PINCTRL_PFC
|
|||
help
|
||||
Enable support for clock present on Renesas RCar SoCs.
|
||||
|
||||
config PINCTRL_PFC_R8A7790
|
||||
bool "Renesas RCar Gen2 R8A7790 pin control driver"
|
||||
def_bool y if R8A7790
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs.
|
||||
|
||||
The driver is controlled by a device tree node which contains both
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A7791
|
||||
bool "Renesas RCar Gen2 R8A7791 pin control driver"
|
||||
def_bool y if R8A7791
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs.
|
||||
|
||||
The driver is controlled by a device tree node which contains both
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A7792
|
||||
bool "Renesas RCar Gen2 R8A7792 pin control driver"
|
||||
def_bool y if R8A7792
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs.
|
||||
|
||||
The driver is controlled by a device tree node which contains both
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A7793
|
||||
bool "Renesas RCar Gen2 R8A7793 pin control driver"
|
||||
def_bool y if R8A7793
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A7793 SoCs.
|
||||
|
||||
The driver is controlled by a device tree node which contains both
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A7794
|
||||
bool "Renesas RCar Gen2 R8A7794 pin control driver"
|
||||
def_bool y if R8A7794
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A7794 SoCs.
|
||||
|
||||
The driver is controlled by a device tree node which contains both
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A7795
|
||||
bool "Renesas RCar Gen3 R8A7795 pin control driver"
|
||||
def_bool y if R8A7795
|
||||
|
|
|
|||
|
|
@ -1,4 +1,9 @@
|
|||
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
|
||||
|
|
|
|||
5720
drivers/pinctrl/renesas/pfc-r8a7790.c
Normal file
5720
drivers/pinctrl/renesas/pfc-r8a7790.c
Normal file
File diff suppressed because it is too large
Load diff
6605
drivers/pinctrl/renesas/pfc-r8a7791.c
Normal file
6605
drivers/pinctrl/renesas/pfc-r8a7791.c
Normal file
File diff suppressed because it is too large
Load diff
2795
drivers/pinctrl/renesas/pfc-r8a7792.c
Normal file
2795
drivers/pinctrl/renesas/pfc-r8a7792.c
Normal file
File diff suppressed because it is too large
Load diff
5140
drivers/pinctrl/renesas/pfc-r8a7794.c
Normal file
5140
drivers/pinctrl/renesas/pfc-r8a7794.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -24,7 +24,12 @@
|
|||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
enum sh_pfc_model {
|
||||
SH_PFC_R8A7795 = 0,
|
||||
SH_PFC_R8A7790 = 0,
|
||||
SH_PFC_R8A7791,
|
||||
SH_PFC_R8A7792,
|
||||
SH_PFC_R8A7793,
|
||||
SH_PFC_R8A7794,
|
||||
SH_PFC_R8A7795,
|
||||
SH_PFC_R8A7796,
|
||||
SH_PFC_R8A77970,
|
||||
SH_PFC_R8A77995,
|
||||
|
|
@ -772,6 +777,26 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
|
|||
if (!priv->pfc.regs)
|
||||
return -ENOMEM;
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7790
|
||||
if (model == SH_PFC_R8A7790)
|
||||
priv->pfc.info = &r8a7790_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7791
|
||||
if (model == SH_PFC_R8A7791)
|
||||
priv->pfc.info = &r8a7791_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7792
|
||||
if (model == SH_PFC_R8A7792)
|
||||
priv->pfc.info = &r8a7792_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7793
|
||||
if (model == SH_PFC_R8A7793)
|
||||
priv->pfc.info = &r8a7793_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7794
|
||||
if (model == SH_PFC_R8A7794)
|
||||
priv->pfc.info = &r8a7794_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
if (model == SH_PFC_R8A7795)
|
||||
priv->pfc.info = &r8a7795_pinmux_info;
|
||||
|
|
@ -797,6 +822,36 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
|
|||
}
|
||||
|
||||
static const struct udevice_id sh_pfc_pinctrl_ids[] = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7790
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7790",
|
||||
.data = SH_PFC_R8A7790,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7791
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7791",
|
||||
.data = SH_PFC_R8A7791,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7792
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7792",
|
||||
.data = SH_PFC_R8A7792,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7793
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7793",
|
||||
.data = SH_PFC_R8A7793,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7794
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7794",
|
||||
.data = SH_PFC_R8A7794,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7795",
|
||||
|
|
|
|||
|
|
@ -245,6 +245,11 @@ sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
|
|||
unsigned int num, unsigned int pin);
|
||||
int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
|
||||
|
||||
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
|
||||
|
|
|
|||
|
|
@ -219,8 +219,8 @@ static int sh_serial_ofdata_to_platdata(struct udevice *dev)
|
|||
fdt_addr_t addr;
|
||||
int ret;
|
||||
|
||||
addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
addr = devfdt_get_addr(dev);
|
||||
if (!addr)
|
||||
return -EINVAL;
|
||||
|
||||
plat->base = addr;
|
||||
|
|
|
|||
|
|
@ -224,9 +224,8 @@ struct uart_port {
|
|||
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
|
||||
defined(CONFIG_R8A7794) || defined(CONFIG_RCAR_GEN3)
|
||||
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
|
||||
defined(CONFIG_R7S72100)
|
||||
# if defined(CONFIG_SCIF_A)
|
||||
# define SCIF_ORER 0x0200
|
||||
# else
|
||||
|
|
@ -308,8 +307,7 @@ struct uart_port {
|
|||
/* SH7763 SCIF2 support */
|
||||
# define SCIF2_RFDC_MASK 0x001f
|
||||
# define SCIF2_TXROOM_MAX 16
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
|
||||
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
|
||||
# if defined(CONFIG_SCIF_A)
|
||||
# define SCIF_RFDC_MASK 0x007f
|
||||
|
|
@ -566,8 +564,7 @@ SCIF_FNS(SCFCR, 0x18, 16)
|
|||
SCIF_FNS(SCFDR, 0x1c, 16)
|
||||
SCIF_FNS(SCLSR, 0x24, 16)
|
||||
SCIF_FNS(DL, 0x00, 0) /* dummy */
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
|
||||
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
/* SCIFA and SCIF register offsets and size */
|
||||
SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
|
||||
SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
|
||||
|
|
@ -762,8 +759,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
|
|||
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
|
||||
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
|
||||
#if defined(CONFIG_SCIF_A)
|
||||
#define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue