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Merge git://git.denx.de/u-boot-dm

Browse source 
Here with some DM changes as well as the long-standing AT91 DM/DT
conversion patches which I have picked up via dm.
This commit is contained in:
Tom Rini 2017-04-13 17:31:06 -04:00
commit b7b24a7a3c
75 changed files with 7782 additions and 931 deletions
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2
Makefile
View file

@ -348,7 +348,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
AWK = awk
PERL = perl
PYTHON = python
PYTHON ?= python
DTC = dtc
CHECK = sparse

17
arch/arm/dts/Makefile
View file

@ -349,6 +349,23 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
sama5d31ek.dtb \
sama5d33ek.dtb \
sama5d34ek.dtb \
sama5d35ek.dtb \
sama5d36ek.dtb \
sama5d36ek_cmp.dtb
dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
at91-sama5d3_xplained.dtb
dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
at91-sama5d4ek.dtb
dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
at91-sama5d4_xplained.dtb
dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2835-rpi-a-plus.dtb \
bcm2835-rpi-a.dtb \

348
arch/arm/dts/at91-sama5d3_xplained.dts Normal file
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@ -0,0 +1,348 @@
/*
* at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
*
* Copyright (C) 2014 Atmel,
* 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d36.dtsi"
/ {
model = "SAMA5D3 Xplained";
compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
chosen {
u-boot,dm-pre-reloc;
stdout-path = &dbgu;
};
aliases {
spi0 = &spi0;
};
memory {
reg = <0x20000000 0x10000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
mmc0: mmc@f0000000 {
u-boot,dm-pre-reloc;
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
vmmc-supply = <&vcc_mmc0_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <8>;
cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
};
};
mmc1: mmc@f8000000 {
u-boot,dm-pre-reloc;
vmmc-supply = <&vcc_3v3_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
status = "disabled";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>;
};
};
spi0: spi@f0004000 {
cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
status = "okay";
};
can0: can@f000c000 {
status = "okay";
};
i2c0: i2c@f0014000 {
pinctrl-0 = <&pinctrl_i2c0_pu>;
status = "okay";
};
i2c1: i2c@f0018000 {
status = "okay";
pmic: act8865@5b {
compatible = "active-semi,act8865";
reg = <0x5b>;
status = "disabled";
regulators {
vcc_1v8_reg: DCDC_REG1 {
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc_1v2_reg: DCDC_REG2 {
regulator-name = "VCC_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc_3v3_reg: DCDC_REG3 {
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vddfuse_reg: LDO_REG1 {
regulator-name = "FUSE_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
vddana_reg: LDO_REG2 {
regulator-name = "VDDANA";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
macb0: ethernet@f0028000 {
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ethernet-phy@7 {
reg = <0x7>;
};
};
pwm0: pwm@f002c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>;
status = "okay";
};
usart0: serial@f001c000 {
status = "okay";
};
usart1: serial@f0020000 {
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
status = "okay";
};
uart0: serial@f0024000 {
status = "okay";
};
mmc1: mmc@f8000000 {
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>;
};
};
spi1: spi@f8008000 {
cs-gpios = <&pioC 25 0>;
status = "okay";
};
adc0: adc@f8018000 {
pinctrl-0 = <
&pinctrl_adc0_adtrg
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
&pinctrl_adc0_ad5
&pinctrl_adc0_ad6
&pinctrl_adc0_ad7
&pinctrl_adc0_ad8
&pinctrl_adc0_ad9
>;
status = "okay";
};
i2c2: i2c@f801c000 {
dmas = <0>, <0>; /* Do not use DMA for i2c2 */
pinctrl-0 = <&pinctrl_i2c2_pu>;
status = "okay";
};
macb1: ethernet@f802c000 {
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ethernet-phy@1 {
reg = <0x1>;
};
};
dbgu: serial@ffffee00 {
u-boot,dm-pre-reloc;
status = "okay";
};
pinctrl@fffff200 {
board {
u-boot,dm-pre-reloc;
pinctrl_i2c0_pu: i2c0_pu {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_i2c2_pu: i2c2_pu {
atmel,pins =
<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mmc0_cd: mmc0_cd {
u-boot,dm-pre-reloc;
atmel,pins =
<AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mmc1_cd: mmc1_cd {
u-boot,dm-pre-reloc;
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
};
};
};
};
nand0: nand@60000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
usb0: gadget@00500000 {
atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
usb1: ohci@00600000 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioE 3 GPIO_ACTIVE_LOW
&pioE 4 GPIO_ACTIVE_LOW
>;
status = "okay";
};
usb2: ehci@00700000 {
status = "okay";
};
};
vcc_mmc0_reg: fixedregulator@0 {
compatible = "regulator-fixed";
gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
regulator-name = "mmc0-card-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
bp3 {
label = "PB_USER";
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
d2 {
label = "d2";
gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */
linux,default-trigger = "heartbeat";
};
d3 {
label = "d3";
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
};
};
};

286
arch/arm/dts/at91-sama5d4_xplained.dts Normal file
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@ -0,0 +1,286 @@
/*
* at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
*
* Copyright (C) 2015 Atmel,
* 2015 Josh Wu <josh.wu@atmel.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sama5d4.dtsi"
/ {
model = "Atmel SAMA5D4 Xplained";
compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
aliases {
spi0 = &spi0;
};
chosen {
u-boot,dm-pre-reloc;
stdout-path = &usart3;
};
memory {
reg = <0x20000000 0x20000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
spi0: spi@f8010000 {
u-boot,dm-pre-reloc;
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
spi_flash@0 {
u-boot,dm-pre-reloc;
compatible = "spi-flash";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
i2c0: i2c@f8014000 {
status = "okay";
};
macb0: ethernet@f8020000 {
phy-mode = "rmii";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
phy0: ethernet-phy@1 {
interrupt-parent = <&pioE>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
reg = <1>;
};
};
mmc1: mmc@fc000000 {
u-boot,dm-pre-reloc;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
vmmc-supply = <&vcc_mmc1_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 3 0>;
};
};
usart3: serial@fc00c000 {
u-boot,dm-pre-reloc;
status = "okay";
};
usart4: serial@fc010000 {
status = "okay";
};
spi1: spi@fc018000 {
cs-gpios = <&pioB 21 0>;
status = "okay";
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <
/* external trigger conflicts with USBA_VBUS */
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
>;
atmel,adc-vref = <3300>;
status = "okay";
};
watchdog@fc068640 {
status = "okay";
};
pinctrl@fc06a000 {
board {
u-boot,dm-pre-reloc;
pinctrl_mmc1_cd: mmc1_cd {
u-boot,dm-pre-reloc;
atmel,pins =
<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_macb0_phy_irq: macb0_phy_irq_0 {
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
};
usb0: gadget@00400000 {
atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
usb1: ohci@00500000 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioE 11 GPIO_ACTIVE_HIGH
&pioE 14 GPIO_ACTIVE_HIGH
>;
status = "okay";
};
usb2: ehci@00600000 {
status = "okay";
};
nand0: nand@80000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
atmel,has-pmecc;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
pb_user1 {
label = "pb_user1";
gpios = <&pioE 8 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
status = "okay";
d8 {
label = "d8";
gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
d10 {
label = "d10";
gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
vcc_3v3_reg: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "VCC 3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
reg = <0 1>;
};
vcc_mmc1_reg: fixedregulator@1 {
compatible = "regulator-fixed";
gpio = <&pioE 4 GPIO_ACTIVE_LOW>;
regulator-name = "VDD MCI1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_reg>;
regulator-always-on;
reg = <1 1>;
};
};

341
arch/arm/dts/at91-sama5d4ek.dts Normal file
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@ -0,0 +1,341 @@
/*
* at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
*
* Copyright (C) 2014 Atmel,
* 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sama5d4.dtsi"
/ {
model = "Atmel SAMA5D4-EK";
compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
aliases {
spi0 = &spi0;
};
chosen {
u-boot,dm-pre-reloc;
stdout-path = &usart3;
};
memory {
reg = <0x20000000 0x20000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <
/* external trigger conflicts with USBA_VBUS */
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
>;
/* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
atmel,adc-vref = <3300>;
/*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
status = "okay"; /* Enable ADC IIO support */
};
mmc0: mmc@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 5 0>;
};
};
ssc0: ssc@f8008000 {
status = "okay";
};
spi0: spi@f8010000 {
u-boot,dm-pre-reloc;
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
spi_flash@0 {
u-boot,dm-pre-reloc;
compatible = "spi-flash";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
i2c0: i2c@f8014000 {
status = "okay";
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck2>;
clock-names = "mclk";
};
qt1070:keyboard@1b {
compatible = "qt1070";
reg = <0x1b>;
interrupt-parent = <&pioE>;
interrupts = <25 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qt1070_irq>;
wakeup-source;
};
atmel_mxt_ts@4c {
compatible = "atmel,atmel_mxt_ts";
reg = <0x4c>;
interrupt-parent = <&pioE>;
interrupts = <24 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mxt_ts>;
};
};
macb0: ethernet@f8020000 {
pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
phy-mode = "rmii";
status = "okay";
ethernet-phy@1 {
reg = <0x1>;
interrupt-parent = <&pioE>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
};
mmc1: mmc@fc000000 {
u-boot,dm-pre-reloc;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 6 0>;
};
};
usart2: serial@fc008000 {
status = "okay";
};
usart3: serial@fc00c000 {
u-boot,dm-pre-reloc;
status = "okay";
};
usart4: serial@fc010000 {
status = "okay";
};
watchdog@fc068640 {
status = "okay";
};
pinctrl@fc06a000 {
board {
u-boot,dm-pre-reloc;
pinctrl_macb0_phy_irq: macb0_phy_irq {
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mmc1_cd: mmc1_cd {
u-boot,dm-pre-reloc;
atmel,pins =
<AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_pck2_as_audio_mck: pck2_as_audio_mck {
atmel,pins =
<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
};
pinctrl_qt1070_irq: qt1070_irq {
atmel,pins =
<AT91_PIOE 25 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mxt_ts: mxt_irq {
atmel,pins =
<AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
};
usb0: gadget@00400000 {
atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
usb1: ohci@00500000 {
num-ports = <3>;
atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
&pioE 11 GPIO_ACTIVE_LOW
&pioE 12 GPIO_ACTIVE_LOW
>;
status = "okay";
};
usb2: ehci@00600000 {
status = "okay";
};
nand0: nand@80000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
atmel,has-pmecc;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
pb_user1 {
label = "pb_user1";
gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
status = "okay";
d8 {
label = "d8";
/* PE28, conflicts with usart4 rts pin */
gpios = <&pioE 28 GPIO_ACTIVE_LOW>;
};
d9 {
label = "d9";
gpios = <&pioE 9 GPIO_ACTIVE_HIGH>;
};
d10 {
label = "d10";
gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
sound {
compatible = "atmel,asoc-wm8904";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck2_as_audio_mck>;
atmel,model = "wm8904 @ SAMA5D4EK";
atmel,audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN1L", "Line In Jack",
"IN1R", "Line In Jack";
atmel,ssc-controller = <&ssc0>;
atmel,audio-codec = <&wm8904>;
};
};

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16
arch/arm/dts/sama5d31.dtsi Normal file
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/*
* sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_lcd.dtsi"
#include "sama5d3_emac.dtsi"
#include "sama5d3_mci2.dtsi"
#include "sama5d3_uart.dtsi"
/ {
compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
};

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/*
* sama5d31ek.dts - Device Tree file for SAMA5D31-EK board
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d31.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
/ {
model = "Atmel SAMA5D31-EK";
compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
aliases {
spi0 = &spi0;
};
ahb {
apb {
spi0: spi@f0004000 {
status = "okay";
};
ssc0: ssc@f0008000 {
status = "okay";
};
i2c0: i2c@f0014000 {
status = "okay";
};
i2c1: i2c@f0018000 {
status = "okay";
};
macb1: ethernet@f802c000 {
status = "okay";
};
};
};
leds {
d3 {
label = "d3";
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
};
};
sound {
status = "okay";
};
};

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/*
* sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_lcd.dtsi"
#include "sama5d3_gmac.dtsi"
/ {
compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5";
};

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/*
* sama5d33ek.dts - Device Tree file for SAMA5D33-EK board
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d33.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
/ {
model = "Atmel SAMA5D33-EK";
compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5";
aliases {
spi0 = &spi0;
};
ahb {
apb {
spi0: spi@f0004000 {
status = "okay";
};
ssc0: ssc@f0008000 {
status = "okay";
};
i2c0: i2c@f0014000 {
status = "okay";
};
i2c1: i2c@f0018000 {
status = "okay";
};
macb0: ethernet@f0028000 {
status = "okay";
};
};
};
sound {
status = "okay";
};
};

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/*
* sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_lcd.dtsi"
#include "sama5d3_gmac.dtsi"
#include "sama5d3_can.dtsi"
#include "sama5d3_mci2.dtsi"
/ {
compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5";
};

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/*
* sama5d34ek.dts - Device Tree file for SAMA5D34-EK board
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d34.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
/ {
model = "Atmel SAMA5D34-EK";
compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5";
aliases {
spi0 = &spi0;
};
ahb {
apb {
spi0: spi@f0004000 {
status = "okay";
};
ssc0: ssc@f0008000 {
status = "okay";
};
can0: can@f000c000 {
status = "okay";
};
i2c0: i2c@f0014000 {
status = "okay";
};
i2c1: i2c@f0018000 {
status = "okay";
24c256@50 {
compatible = "24c256";
reg = <0x50>;
pagesize = <64>;
};
};
macb0: ethernet@f0028000 {
status = "okay";
};
};
};
leds {
d3 {
label = "d3";
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
};
};
sound {
status = "okay";
};
};

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/*
* sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_gmac.dtsi"
#include "sama5d3_emac.dtsi"
#include "sama5d3_can.dtsi"
#include "sama5d3_mci2.dtsi"
#include "sama5d3_uart.dtsi"
#include "sama5d3_tcb1.dtsi"
/ {
compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5";
};

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arch/arm/dts/sama5d35ek.dts Normal file
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/*
* sama5d35ek.dts - Device Tree file for SAMA5D35-EK board
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d35.dtsi"
#include "sama5d3xmb.dtsi"
/ {
model = "Atmel SAMA5D35-EK";
compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5";
aliases {
spi0 = &spi0;
};
ahb {
apb {
spi0: spi@f0004000 {
status = "okay";
};
can0: can@f000c000 {
status = "okay";
};
i2c1: i2c@f0018000 {
status = "okay";
};
macb0: ethernet@f0028000 {
status = "okay";
};
isi: isi@f0034000 {
status = "okay";
};
macb1: ethernet@f802c000 {
status = "okay";
};
};
};
gpio_keys {
compatible = "gpio-keys";
pb_user1 {
label = "pb_user1";
gpios = <&pioE 27 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
wakeup-source;
};
};
};

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arch/arm/dts/sama5d36.dtsi Normal file
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/*
* sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC
*
* Copyright (C) 2013 Atmel,
* 2013 Josh Wu <josh.wu@atmel.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_can.dtsi"
#include "sama5d3_gmac.dtsi"
#include "sama5d3_emac.dtsi"
#include "sama5d3_lcd.dtsi"
#include "sama5d3_mci2.dtsi"
#include "sama5d3_tcb1.dtsi"
#include "sama5d3_uart.dtsi"
/ {
compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
};

57
arch/arm/dts/sama5d36ek.dts Normal file
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/*
* sama5d36ek.dts - Device Tree file for SAMA5D36-EK board
*
* Copyright (C) 2013 Atmel,
* 2013 Josh Wu <josh.wu@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d36.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
/ {
model = "Atmel SAMA5D36-EK";
compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
aliases {
spi0 = &spi0;
};
ahb {
apb {
spi0: spi@f0004000 {
status = "okay";
};
ssc0: ssc@f0008000 {
status = "okay";
};
can0: can@f000c000 {
status = "okay";
};
i2c0: i2c@f0014000 {
status = "okay";
};
i2c1: i2c@f0018000 {
status = "okay";
};
macb0: ethernet@f0028000 {
status = "okay";
};
macb1: ethernet@f802c000 {
status = "okay";
};
};
};
sound {
status = "okay";
};
};

55
arch/arm/dts/sama5d36ek_cmp.dts Normal file
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/*
* sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board
*
* Copyright (C) 2016 Atmel,
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d36.dtsi"
#include "sama5d3xmb_cmp.dtsi"
/ {
model = "Atmel SAMA5D36-EK";
compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
aliases {
spi0 = &spi0;
};
ahb {
apb {
spi0: spi@f0004000 {
status = "okay";
};
ssc0: ssc@f0008000 {
status = "okay";
};
can0: can@f000c000 {
status = "okay";
};
i2c0: i2c@f0014000 {
status = "okay";
};
i2c1: i2c@f0018000 {
status = "okay";
};
macb0: ethernet@f0028000 {
status = "okay";
};
macb1: ethernet@f802c000 {
status = "okay";
};
};
};
sound {
status = "okay";
};
};

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/*
* sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
* CAN support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
can0 {
pinctrl_can0_rx_tx: can0_rx_tx {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
};
};
can1 {
pinctrl_can1_rx_tx: can1_rx_tx {
atmel,pins =
<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
};
};
};
pmc: pmc@fffffc00 {
periphck {
can0_clk: can0_clk@40 {
#clock-cells = <0>;
reg = <40>;
atmel,clk-output-range = <0 66000000>;
};
can1_clk: can1_clk@41 {
#clock-cells = <0>;
reg = <41>;
atmel,clk-output-range = <0 66000000>;
};
};
};
can0: can@f000c000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf000c000 0x300>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
clocks = <&can0_clk>;
clock-names = "can_clk";
status = "disabled";
};
can1: can@f8010000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8010000 0x300>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
clocks = <&can1_clk>;
clock-names = "can_clk";
status = "disabled";
};
};
};
};

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/*
* sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with
* Ethernet.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
macb1 {
pinctrl_macb1_rmii: macb1_rmii-0 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
};
};
};
pmc: pmc@fffffc00 {
periphck {
macb1_clk: macb1_clk@35 {
#clock-cells = <0>;
reg = <35>;
};
};
};
macb1: ethernet@f802c000 {
compatible = "cdns,at91sam9260-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
clocks = <&macb1_clk>, <&macb1_clk>;
clock-names = "hclk", "pclk";
status = "disabled";
};
};
};
};

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/*
* sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with
* Gigabit Ethernet.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
macb0 {
pinctrl_macb0_data_rgmii: macb0_data_rgmii {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
};
pinctrl_macb0_data_gmii: macb0_data_gmii {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
};
pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
};
pinctrl_macb0_signal_gmii: macb0_signal_gmii {
atmel,pins =
<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
};
};
};
pmc: pmc@fffffc00 {
periphck {
macb0_clk: macb0_clk@34 {
#clock-cells = <0>;
reg = <34>;
};
};
};
macb0: ethernet@f0028000 {
compatible = "atmel,sama5d3-gem";
reg = <0xf0028000 0x100>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
clocks = <&macb0_clk>, <&macb0_clk>;
clock-names = "hclk", "pclk";
status = "disabled";
};
};
};
};

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/*
* sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
* LCD support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
hlcdc: hlcdc@f0030000 {
compatible = "atmel,sama5d3-hlcdc";
reg = <0xf0030000 0x2000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
};
hlcdc_pwm: hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_pwm>;
#pwm-cells = <3>;
};
};
pinctrl@fffff200 {
lcd {
pinctrl_lcd_base: lcd-base-0 {
atmel,pins =
<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
};
pinctrl_lcd_pwm: lcd-pwm-0 {
atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
};
pinctrl_lcd_rgb444: lcd-rgb-0 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
};
pinctrl_lcd_rgb565: lcd-rgb-1 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
};
pinctrl_lcd_rgb666: lcd-rgb-2 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
};
pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* LCDD17 pin */
};
pinctrl_lcd_rgb888: lcd-rgb-3 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
};
pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD17 pin */
AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD18 pin */
AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD19 pin */
AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD20 pin */
AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD21 pin */
AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD22 pin */
AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* LCDD23 pin */
};
};
};
pmc: pmc@fffffc00 {
periphck {
lcdc_clk: lcdc_clk@36 {
#clock-cells = <0>;
reg = <36>;
};
};
systemck {
lcdck: lcdck@3 {
#clock-cells = <0>;
reg = <3>;
clocks = <&mck>;
};
};
};
};
};
};

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/*
* sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with
* 3 MMC ports
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
mmc2 {
pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
atmel,pins =
<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
};
pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
atmel,pins =
<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
};
};
};
pmc: pmc@fffffc00 {
periphck {
mci2_clk: mci2_clk@23 {
#clock-cells = <0>;
reg = <23>;
};
};
};
mmc2: mmc@f8004000 {
compatible = "atmel,hsmci";
reg = <0xf8004000 0x600>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
clocks = <&mci2_clk>;
clock-names = "mci_clk";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};

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arch/arm/dts/sama5d3_tcb1.dtsi Normal file
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/*
* sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with
* 2 TC blocks.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
/ {
aliases {
tcb1 = &tcb1;
};
ahb {
apb {
pmc: pmc@fffffc00 {
periphck {
tcb1_clk: tcb1_clk@27 {
#clock-cells = <0>;
reg = <27>;
};
};
};
tcb1: timer@f8014000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8014000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb1_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
};
};
};

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/*
* sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
* UART support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
/ {
aliases {
serial5 = &uart0;
serial6 = &uart1;
};
ahb {
apb {
pinctrl@fffff200 {
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
};
};
};
pmc: pmc@fffffc00 {
periphck {
uart0_clk: uart0_clk@16 {
#clock-cells = <0>;
reg = <16>;
atmel,clk-output-range = <0 66000000>;
};
uart1_clk: uart1_clk@17 {
#clock-cells = <0>;
reg = <17>;
atmel,clk-output-range = <0 66000000>;
};
};
};
uart0: serial@f0024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf0024000 0x200>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart0_clk>;
clock-names = "usart";
status = "disabled";
};
uart1: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart1_clk>;
clock-names = "usart";
status = "disabled";
};
};
};
};

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/*
* sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/ {
compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
chosen {
bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x20000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
spi0: spi@f0004000 {
cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
};
macb0: ethernet@f0028000 {
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
ethernet-phy@1 {
reg = <0x1>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
txen-skew-ps = <800>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <400>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <400>;
rxd1-skew-ps = <400>;
rxd2-skew-ps = <400>;
rxd3-skew-ps = <400>;
};
ethernet-phy@7 {
reg = <0x7>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
txen-skew-ps = <800>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <400>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <400>;
rxd1-skew-ps = <400>;
rxd2-skew-ps = <400>;
rxd3-skew-ps = <400>;
};
};
};
nand0: nand@60000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
leds {
compatible = "gpio-leds";
d2 {
label = "d2";
gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */
linux,default-trigger = "heartbeat";
};
};
};

166
arch/arm/dts/sama5d3xcm_cmp.dtsi Normal file
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/*
* sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module
*
* Copyright (C) 2016 Atmel,
*
* Licensed under GPLv2 or later.
*/
/ {
compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
chosen {
bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x20000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
spi0: spi@f0004000 {
cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
};
macb0: ethernet@f0028000 {
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
ethernet-phy@1 {
reg = <0x1>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
txen-skew-ps = <800>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <400>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <400>;
rxd1-skew-ps = <400>;
rxd2-skew-ps = <400>;
rxd3-skew-ps = <400>;
};
ethernet-phy@7 {
reg = <0x7>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
txen-skew-ps = <800>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <400>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <400>;
rxd1-skew-ps = <400>;
rxd2-skew-ps = <400>;
rxd3-skew-ps = <400>;
};
};
i2c1: i2c@f0018000 {
pmic: act8865@5b {
compatible = "active-semi,act8865";
reg = <0x5b>;
status = "disabled";
regulators {
vcc_1v8_reg: DCDC_REG1 {
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc_1v2_reg: DCDC_REG2 {
regulator-name = "VCC_1V2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
vcc_3v3_reg: DCDC_REG3 {
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vddana_reg: LDO_REG1 {
regulator-name = "VDDANA";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vddfuse_reg: LDO_REG2 {
regulator-name = "FUSE_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
};
};
};
};
nand0: nand@60000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
leds {
compatible = "gpio-leds";
d2 {
label = "d2";
gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */
linux,default-trigger = "heartbeat";
};
};
};

41
arch/arm/dts/sama5d3xdm.dtsi Normal file
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@ -0,0 +1,41 @@
/*
* sama5d3dm.dtsi - Device Tree file for SAMA5 display module
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/ {
ahb {
apb {
i2c1: i2c@f0018000 {
qt1070: keyboard@1b {
compatible = "qt1070";
reg = <0x1b>;
interrupt-parent = <&pioE>;
interrupts = <31 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qt1070_irq>;
wakeup-source;
};
};
adc0: adc@f8018000 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
pinctrl@fffff200 {
board {
pinctrl_qt1070_irq: qt1070_irq {
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pull up deglith */
};
};
};
};
};
};

234
arch/arm/dts/sama5d3xmb.dtsi Normal file
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@ -0,0 +1,234 @@
/*
* sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3xcm.dtsi"
/ {
compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
chosen {
u-boot,dm-pre-reloc;
stdout-path = &dbgu;
};
ahb {
apb {
mmc0: mmc@f0000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
status = "okay";
u-boot,dm-pre-reloc;
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
};
};
spi0: spi@f0004000 {
dmas = <0>, <0>; /* Do not use DMA for spi0 */
u-boot,dm-pre-reloc;
spi_flash@0 {
compatible = "spi-flash";
spi-max-frequency = <50000000>;
reg = <0>;
u-boot,dm-pre-reloc;
};
};
ssc0: ssc@f0008000 {
atmel,clk-from-rk-pin;
};
/*
* i2c0 conflicts with ISI:
* disable it to allow the use of ISI
* can not enable audio when i2c0 disabled
*/
i2c0: i2c@f0014000 {
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck0>;
clock-names = "mclk";
};
};
i2c1: i2c@f0018000 {
ov2640: camera@0x30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
/* use pck1 for the master clock of ov2640 */
clocks = <&pck1>;
clock-names = "xvclk";
assigned-clocks = <&pck1>;
assigned-clock-rates = <25000000>;
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
usart1: serial@f0020000 {
dmas = <0>, <0>; /* Do not use DMA for usart1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
status = "okay";
};
isi: isi@f0034000 {
port {
isi_0: endpoint {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};
mmc1: mmc@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
status = "okay";
u-boot,dm-pre-reloc;
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>;
};
};
adc0: adc@f8018000 {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_adc0_adtrg
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
>;
status = "okay";
};
macb1: ethernet@f802c000 {
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@1 {
/*interrupt-parent = <&pioE>;*/
/*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/
reg = <1>;
};
};
pinctrl@fffff200 {
board {
u-boot,dm-pre-reloc;
pinctrl_mmc0_cd: mmc0_cd {
u-boot,dm-pre-reloc;
atmel,pins =
<AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */
};
pinctrl_mmc1_cd: mmc1_cd {
u-boot,dm-pre-reloc;
atmel,pins =
<AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */
};
pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
atmel,pins =
<AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */
};
pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
atmel,pins =
<AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
};
pinctrl_sensor_reset: sensor_reset-0 {
atmel,pins =
<AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */
};
pinctrl_sensor_power: sensor_power-0 {
atmel,pins =
<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */
};
};
};
dbgu: serial@ffffee00 {
dmas = <0>, <0>; /* Do not use DMA for dbgu */
status = "okay";
u-boot,dm-pre-reloc;
};
watchdog@fffffe40 {
status = "okay";
};
};
usb0: gadget@00500000 {
atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
usb1: ohci@00600000 {
num-ports = <3>;
atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH
&pioD 26 GPIO_ACTIVE_LOW
&pioD 27 GPIO_ACTIVE_LOW
>;
status = "okay";
};
usb2: ehci@00700000 {
status = "okay";
};
};
sound {
compatible = "atmel,asoc-wm8904";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
atmel,model = "wm8904 @ SAMA5D3EK";
atmel,audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Mic", "MICBIAS",
"IN1L", "Mic";
atmel,ssc-controller = <&ssc0>;
atmel,audio-codec = <&wm8904>;
status = "disabled";
};
};

236
arch/arm/dts/sama5d3xmb_cmp.dtsi Normal file
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@ -0,0 +1,236 @@
/*
* sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board
*
* Copyright (C) 2016 Atmel,
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3xcm_cmp.dtsi"
/ {
compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
chosen {
u-boot,dm-pre-reloc;
stdout-path = &dbgu;
};
ahb {
apb {
mmc0: mmc@f0000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
};
};
spi0: spi@f0004000 {
dmas = <0>, <0>; /* Do not use DMA for spi0 */
spi_flash@0 {
compatible = "spi-flash";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
ssc0: ssc@f0008000 {
atmel,clk-from-rk-pin;
};
/*
* i2c0 conflicts with ISI:
* disable it to allow the use of ISI
* can not enable audio when i2c0 disabled
*/
i2c0: i2c@f0014000 {
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck0>;
clock-names = "mclk";
};
};
i2c1: i2c@f0018000 {
ov2640: camera@0x30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
/* use pck1 for the master clock of ov2640 */
clocks = <&pck1>;
clock-names = "xvclk";
assigned-clocks = <&pck1>;
assigned-clock-rates = <25000000>;
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
usart1: serial@f0020000 {
dmas = <0>, <0>; /* Do not use DMA for usart1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
status = "okay";
};
isi: isi@f0034000 {
port {
isi_0: endpoint {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};
mmc1: mmc@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>;
};
};
adc0: adc@f8018000 {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_adc0_adtrg
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
>;
status = "okay";
};
macb1: ethernet@f802c000 {
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@1 {
/*interrupt-parent = <&pioE>;*/
/*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/
reg = <1>;
};
};
pinctrl@fffff200 {
board {
pinctrl_gpio_keys: gpio_keys {
atmel,pins =
<AT91_PIOE 27 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */
};
pinctrl_mmc1_cd: mmc1_cd {
atmel,pins =
<AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */
};
pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
atmel,pins =
<AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */
};
pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
atmel,pins =
<AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
};
pinctrl_sensor_reset: sensor_reset-0 {
atmel,pins =
<AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */
};
pinctrl_sensor_power: sensor_power-0 {
atmel,pins =
<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */
};
};
};
dbgu: serial@ffffee00 {
dmas = <0>, <0>; /* Do not use DMA for dbgu */
status = "okay";
u-boot,dm-pre-reloc;
};
watchdog@fffffe40 {
status = "okay";
};
};
usb0: gadget@00500000 {
atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
};
sound {
compatible = "atmel,asoc-wm8904";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
atmel,model = "wm8904 @ SAMA5D3EK";
atmel,audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Mic", "MICBIAS",
"IN1L", "Mic";
atmel,ssc-controller = <&ssc0>;
atmel,audio-codec = <&wm8904>;
status = "disabled";
};
/* Conflict with LCD pins */
gpio_keys {
compatible = "gpio-keys";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
pb_user1 {
label = "pb_user1";
gpios = <&pioE 27 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
gpio-key,wakeup;
};
};
};

1935
arch/arm/dts/sama5d4.dtsi Normal file
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104
arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c
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@ -18,45 +18,45 @@ unsigned int has_lcdc()
void at91_serial0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void at91_serial3_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
at91_periph_clk_enable(ATMEL_ID_USART3);
}
void at91_seriald_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_periph_clk_enable(ATMEL_ID_SYS);
}
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI0);
@ -72,9 +72,9 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
at91_pio3_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
at91_pio3_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
at91_pio3_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI1);
@ -91,12 +91,12 @@ void at91_spi1_hw_init(unsigned long cs_mask)
void at91_mci_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
at91_periph_clk_enable(ATMEL_ID_HSMCI0);
}
@ -104,37 +104,37 @@ void at91_mci_hw_init(void)
#ifdef CONFIG_LCD
void at91_lcd_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
at91_periph_clk_enable(ATMEL_ID_LCDC);
}

112
arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c
View file

@ -64,32 +64,32 @@ char *get_cpu_name()
void at91_seriald_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
at91_periph_clk_enable(ATMEL_ID_SYS);
}
void at91_serial0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
at91_periph_clk_enable(ATMEL_ID_USART2);
}
@ -97,12 +97,12 @@ void at91_serial2_hw_init(void)
void at91_mci_hw_init(void)
{
/* Initialize the MCI0 */
at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
at91_periph_clk_enable(ATMEL_ID_HSMCI0);
}
@ -110,20 +110,20 @@ void at91_mci_hw_init(void)
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0))
at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);
if (cs_mask & (1 << 1))
at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
at91_pio3_set_b_periph(AT91_PIO_PORTA, 7, 0);
if (cs_mask & (1 << 2))
at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
at91_pio3_set_b_periph(AT91_PIO_PORTA, 1, 0);
if (cs_mask & (1 << 3))
at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
at91_pio3_set_b_periph(AT91_PIO_PORTB, 3, 0);
if (cs_mask & (1 << 4))
at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
if (cs_mask & (1 << 5))
@ -136,20 +136,20 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
at91_pio3_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
at91_pio3_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
at91_pio3_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0))
at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
at91_pio3_set_b_periph(AT91_PIO_PORTA, 8, 0);
if (cs_mask & (1 << 1))
at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
at91_pio3_set_b_periph(AT91_PIO_PORTA, 0, 0);
if (cs_mask & (1 << 2))
at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
at91_pio3_set_b_periph(AT91_PIO_PORTA, 31, 0);
if (cs_mask & (1 << 3))
at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
at91_pio3_set_b_periph(AT91_PIO_PORTA, 30, 0);
if (cs_mask & (1 << 4))
at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
if (cs_mask & (1 << 5))
@ -181,45 +181,45 @@ void at91_macb_hw_init(void)
/* Enable EMAC0 clock */
at91_periph_clk_enable(ATMEL_ID_EMAC0);
/* EMAC0 pins setup */
at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
}
if (has_emac1()) {
/* Enable EMAC1 clock */
at91_periph_clk_enable(ATMEL_ID_EMAC1);
/* EMAC1 pins setup */
at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
}
#ifndef CONFIG_RMII
/* Only emac0 support MII */
if (has_emac0()) {
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
}
#endif
}

136
arch/arm/mach-at91/armv7/sama5d3_devices.c
View file

@ -52,8 +52,8 @@ char *get_cpu_name()
void at91_serial0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART0);
@ -61,8 +61,8 @@ void at91_serial0_hw_init(void)
void at91_serial1_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART1);
@ -70,8 +70,8 @@ void at91_serial1_hw_init(void)
void at91_serial2_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
at91_pio3_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
at91_pio3_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART2);
@ -79,8 +79,8 @@ void at91_serial2_hw_init(void)
void at91_seriald_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_DBGU);
@ -89,9 +89,9 @@ void at91_seriald_hw_init(void)
#if defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
if (cs_mask & (1 << 0))
at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
@ -110,18 +110,18 @@ void at91_spi0_hw_init(unsigned long cs_mask)
#ifdef CONFIG_GENERIC_ATMEL_MCI
void at91_mci_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
#ifdef CONFIG_ATMEL_MCI_8BIT
at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
#endif
at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI0);
@ -131,16 +131,16 @@ void at91_mci_hw_init(void)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_EMAC);
@ -148,23 +148,23 @@ void at91_macb_hw_init(void)
void at91_gmac_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC);
@ -174,30 +174,30 @@ void at91_gmac_hw_init(void)
#ifdef CONFIG_LCD
void at91_lcd_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
/* The lower 16-bit of LCD only available on Port A */
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);

2
arch/arm/mach-at91/armv7/u-boot-spl.lds
View file

@ -47,6 +47,8 @@ SECTIONS
*(.__end)
} >.sram
_image_binary_end = .;
.bss :
{
. = ALIGN(4);

69
arch/arm/mach-at91/include/mach/at91_pio.h
View file

@ -32,6 +32,8 @@
#define AT91_ASM_PIOD_ASR \
(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
#define PIO_SCDR_DIV 0x3fff /* Slow Clock Divider Selection for Debouncing Mask */
#ifndef __ASSEMBLY__
typedef struct at91_port {
@ -63,28 +65,32 @@ typedef struct at91_port {
u32 puer; /* 0x64 Pull-up Enable Register */
u32 pusr; /* 0x68 Pad Pull-up Status Register */
u32 reserved4;
#if defined(CPU_HAS_PIO3)
u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
u32 reserved5[2];
u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
u32 ppder; /* 0x94 Pad Pull-down Enable Register */
u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
u32 reserved6; /* */
#else
u32 asr; /* 0x70 Select A Register */
u32 bsr; /* 0x74 Select B Register */
u32 absr; /* 0x78 AB Select Status Register */
u32 reserved5[9]; /* */
#endif
union {
struct {
u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
u32 reserved5[2];
u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
u32 ppder; /* 0x94 Pad Pull-down Enable Register */
u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
u32 reserved6; /* */
} pio3;
struct {
u32 asr; /* 0x70 Select A Register */
u32 bsr; /* 0x74 Select B Register */
u32 absr; /* 0x78 AB Select Status Register */
u32 reserved5[9]; /* */
} pio2;
} mux;
u32 ower; /* 0xA0 Output Write Enable Register */
u32 owdr; /* 0xA4 Output Write Disable Register */
u32 owsr; /* OxA8 Output Write Status Register */
#if defined(CPU_HAS_PIO3)
u32 reserved7; /* */
u32 aimer; /* 0xB0 Additional INT Modes Enable Register */
u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */
@ -103,10 +109,11 @@ typedef struct at91_port {
u32 wpsr; /* 0xE8 Write Protect Status Register */
u32 reserved11[5]; /* */
u32 schmitt; /* 0x100 Schmitt Trigger Register */
u32 reserved12[63];
#else
u32 reserved6[85];
#endif
u32 reserved12[4]; /* 0x104 ~ 0x110 */
u32 driver1; /* 0x114 I/O Driver Register1(AT91SAM9x5's driver1) */
u32 driver12; /* 0x118 I/O Driver Register12(AT91SAM9x5's driver2 or SAMA5D3x's driver1 ) */
u32 driver2; /* 0x11C I/O Driver Register2(SAMA5D3x's driver2) */
u32 reserved13[12]; /* 0x120 ~ 0x14C */
} at91_port_t;
typedef union at91_pio {
@ -123,13 +130,6 @@ typedef union at91_pio {
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
#if defined(CPU_HAS_PIO3)
int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int value);
@ -138,6 +138,15 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
int at91_set_pio_value(unsigned port, unsigned pin, int value);
int at91_get_pio_value(unsigned port, unsigned pin);
int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup);
int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup);
int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup);
int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
#endif
#endif

2
arch/arm/mach-at91/include/mach/at91sam9x5.h
View file

@ -171,8 +171,6 @@
* Other misc defines
*/
#define ATMEL_PIO_PORTS 4
#define CPU_HAS_PIO3
#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
#define ATMEL_ID_UHP ATMEL_ID_UHPHS

12
arch/arm/mach-at91/include/mach/gpio.h
View file

@ -223,15 +223,13 @@ static inline unsigned pin_to_mask(unsigned pin)
at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_input(x, y) \
at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_value(x, y) \
at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y)
#define at91_get_gpio_value(x) \
at91_get_pio_value((x - PIN_BASE) / 32,(x % 32))
#else
#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y)
#define at91_get_gpio_value(x) at91_get_pio_value(x)
#endif
#define at91_set_gpio_value(x, y) \
at91_set_pio_value((x / 32), (x % 32), y)
#define at91_get_gpio_value(x) \
at91_get_pio_value((x / 32), (x % 32))
#define GPIO_PIOA_BASE (0)
#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)

2
arch/arm/mach-at91/include/mach/sama5d3.h
View file

@ -188,8 +188,6 @@
* Other misc defines
*/
#define ATMEL_PIO_PORTS 5
#define CPU_HAS_PIO3
#define PIO_SCDR_DIV 0x3fff
#define CPU_HAS_PCR
/* Timer */

2
arch/arm/mach-at91/include/mach/sama5d4.h
View file

@ -174,8 +174,6 @@
* Other misc defines
*/
#define ATMEL_PIO_PORTS 5
#define CPU_HAS_PIO3
#define PIO_SCDR_DIV 0x3fff
#define CPU_HAS_PCR
#define CPU_HAS_H32MXDIV

7
arch/arm/mach-at91/spl.c
View file

@ -39,12 +39,16 @@ u32 spl_boot_device(void)
#if defined(CONFIG_SYS_USE_MMC)
if (dev == ATMEL_SAMA5_BOOT_FROM_MCI) {
#if defined(CONFIG_SPL_OF_CONTROL)
return BOOT_DEVICE_MMC1;
#else
if (off == 0)
return BOOT_DEVICE_MMC1;
if (off == 1)
return BOOT_DEVICE_MMC2;
printf("ERROR: MMC controller %i not present!\n", dev);
hang();
#endif
}
#endif
@ -53,6 +57,9 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_SPI;
#endif
if (dev == ATMEL_SAMA5_BOOT_FROM_SMC)
return BOOT_DEVICE_NAND;
if (dev == ATMEL_SAMA5_BOOT_FROM_SAMBA)
return BOOT_DEVICE_USB;

11
arch/arm/mach-at91/spl_atmel.c
View file

@ -77,6 +77,8 @@ void s_init(void)
void board_init_f(ulong dummy)
{
int ret;
switch_to_main_crystal_osc();
#ifdef CONFIG_SAMA5D2
@ -99,7 +101,14 @@ void board_init_f(ulong dummy)
board_early_init_f();
mem_init();
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
mem_init();
}

10
board/atmel/at91sam9n12ek/at91sam9n12ek.c
View file

@ -71,10 +71,10 @@ static void at91sam9n12ek_nand_hw_init(void)
/* Configure ENABLE pin for NandFlash */
at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
}
#endif
@ -194,7 +194,7 @@ void at91sam9n12ek_ks8851_hw_init(void)
&smc->cs[2].mode);
/* Configure NCS2 PIN */
at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
}
#endif

88
board/atmel/at91sam9x5ek/at91sam9x5ek.c
View file

@ -77,18 +77,18 @@ static void at91sam9x5ek_nand_hw_init(void)
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
}
#endif
@ -128,49 +128,49 @@ vidinfo_t panel_info = {
void lcd_enable(void)
{
if (has_lcdc())
at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
}
void lcd_disable(void)
{
if (has_lcdc())
at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
}
static void at91sam9x5ek_lcd_hw_init(void)
{
if (has_lcdc()) {
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
at91_periph_clk_enable(ATMEL_ID_LCDC);
}

64
board/atmel/sama5d3xek/sama5d3xek.c
View file

@ -95,31 +95,31 @@ static void sama5d3xek_nor_hw_init(void)
&smc->cs[0].mode);
/* Address pin (A1 ~ A23) configuration */
at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
/* CS0 pin configuration */
at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
}
#endif
@ -170,14 +170,14 @@ static void sama5d3xek_lcd_hw_init(void)
gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
/* The higher 8 bit of LCD is board related */
at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
/* Configure lower 16 bit of LCD and enable clock */
at91_lcd_hw_init();

239
board/atmel/sama5d4_xplained/sama5d4_xplained.c
View file

@ -10,52 +10,18 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/sama5d4.h>
#include <atmel_hlcdc.h>
#include <atmel_mci.h>
#include <debug_uart.h>
#include <lcd.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <nand.h>
#include <spi.h>
#include <version.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_ATMEL_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}
static void sama5d4_xplained_spi0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_SPI0);
}
#endif /* CONFIG_ATMEL_SPI */
#ifdef CONFIG_NAND_ATMEL
static void sama5d4_xplained_nand_hw_init(void)
{
@ -82,20 +48,20 @@ static void sama5d4_xplained_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
}
#endif
@ -134,39 +100,39 @@ unsigned int has_lcdc(void)
static void sama5d4_xplained_lcd_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
@ -200,109 +166,46 @@ void lcd_show_board_info(void)
#endif /* CONFIG_LCD */
#ifdef CONFIG_GENERIC_ATMEL_MCI
void sama5d4_xplained_mci1_hw_init(void)
{
at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
* external pull up, the pull up resistor will be very small, if so
* the power consumption will increase, so disable the interanl pull
* down to save the power.
*/
at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI1);
}
int board_mmc_init(bd_t *bis)
{
/* Enable the power supply */
at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
return atmel_mci_init((void *)ATMEL_BASE_MCI1);
}
#endif /* CONFIG_GENERIC_ATMEL_MCI */
#ifdef CONFIG_MACB
void sama5d4_xplained_macb0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
}
#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void sama5d4_xplained_serial3_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART3);
}
void board_debug_uart_init(void)
{
sama5d4_xplained_serial3_hw_init();
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
at91_periph_clk_enable(ATMEL_ID_PIOD);
at91_periph_clk_enable(ATMEL_ID_PIOE);
sama5d4_xplained_serial3_hw_init();
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
return 0;
}
#endif
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_ATMEL_SPI
sama5d4_xplained_spi0_hw_init();
#endif
#ifdef CONFIG_NAND_ATMEL
sama5d4_xplained_nand_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d4_xplained_mci1_hw_init();
#endif
#ifdef CONFIG_MACB
sama5d4_xplained_macb0_hw_init();
#endif
#ifdef CONFIG_LCD
sama5d4_xplained_lcd_hw_init();
#endif
#ifdef CONFIG_CMD_USB
sama5d4_xplained_usb_hw_init();
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
at91_udp_hw_init();
#endif
return 0;
}
@ -314,34 +217,12 @@ int dram_init(void)
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
usba_udc_probe(&pdata);
#ifdef CONFIG_USB_ETH_RNDIS
usb_eth_initialize(bis);
#endif
#endif
return rc;
}
/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_MMC
sama5d4_xplained_mci1_hw_init();
#elif CONFIG_SYS_USE_NANDFLASH
#if CONFIG_SYS_USE_NANDFLASH
sama5d4_xplained_nand_hw_init();
#elif CONFIG_SYS_USE_SERIALFLASH
sama5d4_xplained_spi0_hw_init();
#endif
}

227
board/atmel/sama5d4ek/sama5d4ek.c
View file

@ -10,52 +10,18 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/sama5d4.h>
#include <atmel_hlcdc.h>
#include <atmel_mci.h>
#include <debug_uart.h>
#include <lcd.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <nand.h>
#include <spi.h>
#include <version.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_ATMEL_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}
static void sama5d4ek_spi0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_SPI0);
}
#endif /* CONFIG_ATMEL_SPI */
#ifdef CONFIG_NAND_ATMEL
static void sama5d4ek_nand_hw_init(void)
{
@ -82,20 +48,20 @@ static void sama5d4ek_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
}
#endif
@ -135,33 +101,33 @@ unsigned int has_lcdc(void)
static void sama5d4ek_lcd_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
@ -196,109 +162,46 @@ void lcd_show_board_info(void)
#endif /* CONFIG_LCD */
#ifdef CONFIG_GENERIC_ATMEL_MCI
void sama5d4ek_mci1_hw_init(void)
{
at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
* external pull up, the pull up resistor will be very small, if so
* the power consumption will increase, so disable the interanl pull
* down to save the power.
*/
at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI1);
}
int board_mmc_init(bd_t *bis)
{
/* Enable power for MCI1 interface */
at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
return atmel_mci_init((void *)ATMEL_BASE_MCI1);
}
#endif /* CONFIG_GENERIC_ATMEL_MCI */
#ifdef CONFIG_MACB
void sama5d4ek_macb0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
}
#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void sama5d4ek_serial3_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART3);
}
void board_debug_uart_init(void)
{
sama5d4ek_serial3_hw_init();
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
at91_periph_clk_enable(ATMEL_ID_PIOD);
at91_periph_clk_enable(ATMEL_ID_PIOE);
sama5d4ek_serial3_hw_init();
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
return 0;
}
#endif
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_ATMEL_SPI
sama5d4ek_spi0_hw_init();
#endif
#ifdef CONFIG_NAND_ATMEL
sama5d4ek_nand_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d4ek_mci1_hw_init();
#endif
#ifdef CONFIG_MACB
sama5d4ek_macb0_hw_init();
#endif
#ifdef CONFIG_LCD
sama5d4ek_lcd_hw_init();
#endif
#ifdef CONFIG_CMD_USB
sama5d4ek_usb_hw_init();
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
at91_udp_hw_init();
#endif
return 0;
}
@ -310,34 +213,12 @@ int dram_init(void)
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
usba_udc_probe(&pdata);
#ifdef CONFIG_USB_ETH_RNDIS
usb_eth_initialize(bis);
#endif
#endif
return rc;
}
/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_MMC
sama5d4ek_mci1_hw_init();
#elif CONFIG_SYS_USE_NANDFLASH
#if CONFIG_SYS_USE_NANDFLASH
sama5d4ek_nand_hw_init();
#elif CONFIG_SYS_USE_SERIALFLASH
sama5d4ek_spi0_hw_init();
#endif
}

172
board/denx/ma5d4evk/ma5d4evk.c
View file

@ -44,9 +44,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
static void ma5d4evk_spi0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
@ -90,39 +90,39 @@ unsigned int has_lcdc(void)
static void ma5d4evk_lcd_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
@ -134,16 +134,16 @@ static void ma5d4evk_lcd_hw_init(void)
/* On-SoM eMMC */
void ma5d4evk_mci0_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
@ -151,16 +151,16 @@ void ma5d4evk_mci0_hw_init(void)
* the power consumption will increase, so disable the internal pull
* down to save the power.
*/
at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI0);
@ -169,12 +169,12 @@ void ma5d4evk_mci0_hw_init(void)
/* On-board MicroSD slot */
void ma5d4evk_mci1_hw_init(void)
{
at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
@ -182,16 +182,16 @@ void ma5d4evk_mci1_hw_init(void)
* the power consumption will increase, so disable the internal pull
* down to save the power.
*/
at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
/* Deal with WP pin on the microSD slot. */
at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI1);
@ -203,7 +203,7 @@ int board_mmc_init(bd_t *bis)
/* De-assert reset on On-SoM eMMC */
at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
ret = atmel_mci_init((void *)ATMEL_BASE_MCI0);
if (ret) /* eMMC init failed, skip it. */
@ -223,16 +223,16 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MACB
void ma5d4evk_macb0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
@ -242,17 +242,17 @@ void ma5d4evk_macb0_hw_init(void)
static void ma5d4evk_serial_hw_init(void)
{
/* USART0 */
at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
at91_periph_clk_enable(ATMEL_ID_USART0);
/* USART1 */
at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
at91_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
at91_periph_clk_enable(ATMEL_ID_USART1);
}
@ -273,7 +273,7 @@ int board_early_init_f(void)
at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
udelay(100);
at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
ma5d4evk_serial_hw_init();

70
board/l+g/vinco/vinco.c
View file

@ -51,9 +51,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
static void vinco_spi0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
@ -76,16 +76,16 @@ static void vinco_usb_hw_init(void)
#ifdef CONFIG_GENERIC_ATMEL_MCI
void vinco_mci0_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */
at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */
at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */
at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */
at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */
at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */
at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
@ -93,16 +93,16 @@ void vinco_mci0_hw_init(void)
* the power consumption will increase, so disable the interanl pull
* down to save the power.
*/
at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI0);
@ -120,16 +120,16 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MACB
void vinco_macb0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
@ -141,8 +141,8 @@ void vinco_macb0_hw_init(void)
static void vinco_serial3_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART3);

1
configs/rock_defconfig
View file

@ -40,6 +40,7 @@ CONFIG_PMIC_ACT8846=y
CONFIG_REGULATOR_ACT8846=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
# CONFIG_TPL_DM_SERIAL is not set
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000

37
configs/sama5d4_xplained_mmc_defconfig
View file

@ -8,11 +8,15 @@ CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_FIT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@ -26,10 +30,41 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y

36
configs/sama5d4_xplained_nandflash_defconfig
View file

@ -6,7 +6,10 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_FIT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
@ -24,10 +27,41 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y

37
configs/sama5d4_xplained_spiflash_defconfig
View file

@ -4,9 +4,12 @@ CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
@ -25,10 +28,42 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y

37
configs/sama5d4ek_mmc_defconfig
View file

@ -8,6 +8,9 @@ CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
@ -15,6 +18,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@ -28,9 +32,42 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y

38
configs/sama5d4ek_nandflash_defconfig
View file

@ -6,9 +6,13 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
@ -26,11 +30,43 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y

38
configs/sama5d4ek_spiflash_defconfig
View file

@ -4,13 +4,15 @@ CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
@ -27,11 +29,43 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y

30
drivers/core/device.c
View file

@ -255,8 +255,36 @@ static void *alloc_priv(int size, uint flags)
if (flags & DM_FLAG_ALLOC_PRIV_DMA) {
priv = memalign(ARCH_DMA_MINALIGN, size);
if (priv)
if (priv) {
memset(priv, '\0', size);
/*
* Ensure that the zero bytes are flushed to memory.
* This prevents problems if the driver uses this as
* both an input and an output buffer:
*
* 1. Zeroes written to buffer (here) and sit in the
* cache
* 2. Driver issues a read command to DMA
* 3. CPU runs out of cache space and evicts some cache
* data in the buffer, writing zeroes to RAM from
* the memset() above
* 4. DMA completes
* 5. Buffer now has some DMA data and some zeroes
* 6. Data being read is now incorrect
*
* To prevent this, ensure that the cache is clean
* within this range at the start. The driver can then
* use normal flush-after-write, invalidate-before-read
* procedures.
*
* TODO(sjg@chromium.org): Drop this microblaze
* exception.
*/
#ifndef CONFIG_MICROBLAZE
flush_dcache_range((ulong)priv, (ulong)priv + size);
#endif
}
} else {
priv = calloc(1, size);
}

2
drivers/core/uclass.c
View file

@ -250,7 +250,7 @@ int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
return ret;
list_for_each_entry(dev, &uc->dev_head, uclass_node) {
debug(" - %d %d\n", dev->req_seq, dev->seq);
debug(" - %d %d '%s'\n", dev->req_seq, dev->seq, dev->name);
if ((find_req_seq ? dev->req_seq : dev->seq) ==
seq_or_req_seq) {
*devp = dev;

13
drivers/gpio/Kconfig
View file

@ -28,6 +28,19 @@ config DWAPB_GPIO
help
Support for the Designware APB GPIO driver.
config AT91_GPIO
bool "AT91 PIO GPIO driver"
depends on DM_GPIO
default n
help
Say yes here to select AT91 PIO GPIO driver. AT91 PIO
controller manages up to 32 fully programmable input/output
lines. Each I/O line may be dedicated as a general-purpose
I/O or be assigned to a function of an embedded peripheral.
The assignment to a function of an embedded peripheral is
the responsibility of AT91 Pinctrl driver. This driver is
responsible for the general-purpose I/O.
config ATMEL_PIO4
bool "ATMEL PIO4 driver"
depends on DM_GPIO

172
drivers/gpio/at91_gpio.c
View file

@ -10,6 +10,7 @@
#include <config.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <asm/io.h>
#include <linux/sizes.h>
@ -59,11 +60,6 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
#if defined(CPU_HAS_PIO3)
if (use_pullup)
at91_set_pio_pulldown(port, pin, 0);
#endif
if (at91_port && (pin < GPIO_PER_BANK))
at91_set_port_pullup(at91_port, pin, use_pullup);
@ -100,14 +96,7 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
writel(readl(&at91_port->abcdsr1) & ~mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) & ~mask,
&at91_port->abcdsr2);
#else
writel(mask, &at91_port->asr);
#endif
writel(mask, &at91_port->mux.pio2.asr);
writel(mask, &at91_port->pdr);
}
@ -126,25 +115,17 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
writel(readl(&at91_port->abcdsr1) | mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) & ~mask,
&at91_port->abcdsr2);
#else
writel(mask, &at91_port->bsr);
#endif
writel(mask, &at91_port->mux.pio2.bsr);
writel(mask, &at91_port->pdr);
}
return 0;
}
#if defined(CPU_HAS_PIO3)
/*
* mux the pin to the "C" internal peripheral role.
* mux the pin to the "A" internal peripheral role.
*/
int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@ -153,10 +134,55 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(readl(&at91_port->abcdsr1) & ~mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) | mask,
&at91_port->abcdsr2);
writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
&at91_port->mux.pio3.abcdsr1);
writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
&at91_port->mux.pio3.abcdsr2);
writel(mask, &at91_port->pdr);
}
return 0;
}
/*
* mux the pin to the "B" internal peripheral role.
*/
int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
&at91_port->mux.pio3.abcdsr1);
writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
&at91_port->mux.pio3.abcdsr2);
writel(mask, &at91_port->pdr);
}
return 0;
}
/*
* mux the pin to the "C" internal peripheral role.
*/
int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
&at91_port->mux.pio3.abcdsr1);
writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
&at91_port->mux.pio3.abcdsr2);
writel(mask, &at91_port->pdr);
}
@ -166,7 +192,7 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
/*
* mux the pin to the "D" internal peripheral role.
*/
int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@ -175,16 +201,15 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(readl(&at91_port->abcdsr1) | mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) | mask,
&at91_port->abcdsr2);
writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
&at91_port->mux.pio3.abcdsr1);
writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
&at91_port->mux.pio3.abcdsr2);
writel(mask, &at91_port->pdr);
}
return 0;
}
#endif
#ifdef CONFIG_DM_GPIO
static bool at91_get_port_output(struct at91_port *at91_port, int offset)
@ -261,12 +286,29 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
if (is_on)
writel(mask, &at91_port->ifer);
else
writel(mask, &at91_port->ifdr);
}
return 0;
}
/*
* enable/disable the glitch filter. mostly used with IRQ handling.
*/
int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
if (is_on) {
#if defined(CPU_HAS_PIO3)
writel(mask, &at91_port->ifscdr);
#endif
writel(mask, &at91_port->mux.pio3.ifscdr);
writel(mask, &at91_port->ifer);
} else {
writel(mask, &at91_port->ifdr);
@ -276,11 +318,10 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
return 0;
}
#if defined(CPU_HAS_PIO3)
/*
* enable/disable the debounce filter.
*/
int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@ -288,8 +329,8 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
if (is_on) {
writel(mask, &at91_port->ifscer);
writel(div & PIO_SCDR_DIV, &at91_port->scdr);
writel(mask, &at91_port->mux.pio3.ifscer);
writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
writel(mask, &at91_port->ifer);
} else {
writel(mask, &at91_port->ifdr);
@ -303,7 +344,7 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
* enable/disable the pull-down.
* If pull-up already enabled while calling the function, we disable it.
*/
int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@ -312,18 +353,31 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
mask = 1 << pin;
if (is_on) {
at91_set_pio_pullup(port, pin, 0);
writel(mask, &at91_port->ppder);
writel(mask, &at91_port->mux.pio3.ppder);
} else
writel(mask, &at91_port->ppddr);
writel(mask, &at91_port->mux.pio3.ppddr);
}
return 0;
}
int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
if (use_pullup)
at91_pio3_set_pio_pulldown(port, pin, 0);
if (at91_port && (pin < GPIO_PER_BANK))
at91_set_port_pullup(at91_port, pin, use_pullup);
return 0;
}
/*
* disable Schmitt trigger
*/
int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@ -336,7 +390,6 @@ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
return 0;
}
#endif
/*
* enable/disable the multi-driver. This is only valid for output and
@ -517,17 +570,44 @@ static int at91_gpio_probe(struct udevice *dev)
struct at91_port_priv *port = dev_get_priv(dev);
struct at91_port_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk clk;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
ret = clk_enable(&clk);
if (ret)
return ret;
clk_free(&clk);
uc_priv->bank_name = plat->bank_name;
uc_priv->gpio_count = GPIO_PER_BANK;
#if CONFIG_IS_ENABLED(OF_CONTROL)
plat->base_addr = (uint32_t)dev_get_addr_ptr(dev);
#endif
port->regs = (struct at91_port *)plat->base_addr;
return 0;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
static const struct udevice_id at91_gpio_ids[] = {
{ .compatible = "atmel,at91rm9200-gpio" },
{ }
};
#endif
U_BOOT_DRIVER(gpio_at91) = {
.name = "gpio_at91",
.id = UCLASS_GPIO,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = at91_gpio_ids,
.platdata_auto_alloc_size = sizeof(struct at91_port_platdata),
#endif
.ops = &gpio_at91_ops,
.probe = at91_gpio_probe,
.priv_auto_alloc_size = sizeof(struct at91_port_priv),

5
drivers/mtd/nand/atmel_nand.c
View file

@ -1222,7 +1222,8 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
#ifdef CONFIG_SYS_NAND_ENABLE_PIN
gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
!(ctrl & NAND_NCE));
#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
@ -1234,7 +1235,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
#ifdef CONFIG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd)
{
return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
}
#endif

4
drivers/net/at91_emac.c
View file

@ -333,7 +333,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
writel(value, &pio->pioa.pdr);
writel(value, &pio->pioa.asr);
writel(value, &pio->pioa.mux.pio2.asr);
#ifdef CONFIG_RMII
value = ATMEL_PMX_BA_ERXCK;
@ -344,7 +344,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
#endif
writel(value, &pio->piob.pdr);
writel(value, &pio->piob.bsr);
writel(value, &pio->piob.mux.pio2.bsr);
at91_periph_clk_enable(ATMEL_ID_EMAC);

14
drivers/pinctrl/Kconfig
View file

@ -150,6 +150,20 @@ config ROCKCHIP_RK3288_PINCTRL
definitions and pin control functions for each available multiplex
function.
config PINCTRL_AT91
bool "AT91 pinctrl driver"
depends on DM
help
This option is to enable the AT91 pinctrl driver for AT91 PIO
controller. AT91 PIO controller is a combined gpio-controller,
pin-mux and pin-config module. Each I/O pin may be dedicated as
a general-purpose I/O or be assigned to a function of an embedded
peripheral. Each I/O pin has a glitch filter providing rejection of
glitches lower than one-half of peripheral clock cycle and
a debouncing filter providing rejection of unwanted pulses from key
or push button operations. You can also control the multi-driver
capability, pull-up and pull-down feature on each I/O pin.
config PINCTRL_AT91PIO4
bool "AT91 PIO4 pinctrl driver"
depends on DM

1
drivers/pinctrl/Makefile
View file

@ -5,6 +5,7 @@
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-y += nxp/
obj-$(CONFIG_ARCH_ATH79) += ath79/

453
drivers/pinctrl/pinctrl-at91.c Normal file
View file

@ -0,0 +1,453 @@
/*
* Atmel PIO pinctrl driver
*
* Copyright (C) 2016 Atmel Corporation
* Wenyou.Yang <wenyou.yang@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm/device.h>
#include <dm/pinctrl.h>
#include <linux/io.h>
#include <linux/err.h>
#include <mach/at91_pio.h>
DECLARE_GLOBAL_DATA_PTR;
#define MAX_GPIO_BANKS 5
#define MAX_NB_GPIO_PER_BANK 32
#define MAX_PINMUX_ENTRIES 200
struct at91_pinctrl_priv {
struct at91_port *reg_base[MAX_GPIO_BANKS];
u32 nbanks;
};
#define PULL_UP BIT(0)
#define MULTI_DRIVE BIT(1)
#define DEGLITCH BIT(2)
#define PULL_DOWN BIT(3)
#define DIS_SCHMIT BIT(4)
#define DRIVE_STRENGTH_SHIFT 5
#define DRIVE_STRENGTH_MASK 0x3
#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
#define OUTPUT BIT(7)
#define OUTPUT_VAL_SHIFT 8
#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
#define DEBOUNCE BIT(16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
/**
* These defines will translated the dt binding settings to our internal
* settings. They are not necessarily the same value as the register setting.
* The actual drive strength current of low, medium and high must be looked up
* from the corresponding device datasheet. This value is different for pins
* that are even in the same banks. It is also dependent on VCC.
* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
* strength when there is no dt config for it.
*/
#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
enum at91_mux {
AT91_MUX_GPIO = 0,
AT91_MUX_PERIPH_A = 1,
AT91_MUX_PERIPH_B = 2,
AT91_MUX_PERIPH_C = 3,
AT91_MUX_PERIPH_D = 4,
};
/**
* struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
* on new IP with support for periph C and D the way to mux in
* periph A and B has changed
* So provide the right callbacks
* if not present means the IP does not support it
* @mux_A_periph: assign the corresponding pin to the peripheral A function.
* @mux_B_periph: assign the corresponding pin to the peripheral B function.
* @mux_C_periph: assign the corresponding pin to the peripheral C function.
* @mux_D_periph: assign the corresponding pin to the peripheral D function.
* @set_deglitch: enable/disable the deglitch feature.
* @set_debounce: enable/disable the debounce feature.
* @set_pulldown: enable/disable the pulldown feature.
* @disable_schmitt_trig: disable schmitt trigger
*/
struct at91_pinctrl_mux_ops {
void (*mux_A_periph)(struct at91_port *pio, u32 mask);
void (*mux_B_periph)(struct at91_port *pio, u32 mask);
void (*mux_C_periph)(struct at91_port *pio, u32 mask);
void (*mux_D_periph)(struct at91_port *pio, u32 mask);
void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
u32 div);
void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
void (*set_drivestrength)(struct at91_port *pio, u32 pin,
u32 strength);
};
static u32 two_bit_pin_value_shift_amount(u32 pin)
{
/* return the shift value for a pin for "two bit" per pin registers,
* i.e. drive strength */
return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
}
static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
{
writel(mask, &pio->idr);
}
static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
{
if (on)
writel(mask, &pio->mux.pio3.ppddr);
writel(mask, (on ? &pio->puer : &pio->pudr));
}
static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
bool is_on, bool val)
{
writel(mask, (val ? &pio->sodr : &pio->codr));
writel(mask, (is_on ? &pio->oer : &pio->odr));
}
static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
{
writel(mask, (on ? &pio->mder : &pio->mddr));
}
static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
{
writel(mask, &pio->mux.pio2.asr);
}
static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
{
writel(mask, &pio->mux.pio2.bsr);
}
static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
{
writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
}
static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
{
writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
}
static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
{
writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
}
static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
{
writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
}
static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
{
writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
}
static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
u32 mask, bool is_on)
{
if (is_on)
writel(mask, &pio->mux.pio3.ifscdr);
at91_mux_set_deglitch(pio, mask, is_on);
}
static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
bool is_on, u32 div)
{
if (is_on) {
writel(mask, &pio->mux.pio3.ifscer);
writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
writel(mask, &pio->ifer);
} else {
writel(mask, &pio->mux.pio3.ifscdr);
}
}
static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
u32 mask, bool is_on)
{
if (is_on)
writel(mask, &pio->pudr);
writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
}
static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
u32 mask)
{
writel(readl(&pio->schmitt) | mask, &pio->schmitt);
}
static void set_drive_strength(void *reg, u32 pin, u32 strength)
{
u32 shift = two_bit_pin_value_shift_amount(pin);
clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
}
static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
u32 pin, u32 setting)
{
void *reg;
reg = &pio->driver12;
if (pin >= MAX_NB_GPIO_PER_BANK / 2)
reg = &pio->driver2;
/* do nothing if setting is zero */
if (!setting)
return;
/* strength is 1 to 1 with setting for SAMA5 */
set_drive_strength(reg, pin, setting);
}
static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
u32 pin, u32 setting)
{
void *reg;
reg = &pio->driver1;
if (pin >= MAX_NB_GPIO_PER_BANK / 2)
reg = &pio->driver12;
/* do nothing if setting is zero */
if (!setting)
return;
/* strength is inverse on SAM9x5s with our defines
* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
setting = DRIVE_STRENGTH_HI - setting;
set_drive_strength(reg, pin, setting);
}
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.mux_A_periph = at91_mux_set_A_periph,
.mux_B_periph = at91_mux_set_B_periph,
.set_deglitch = at91_mux_set_deglitch,
};
static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
.mux_A_periph = at91_mux_pio3_set_A_periph,
.mux_B_periph = at91_mux_pio3_set_B_periph,
.mux_C_periph = at91_mux_pio3_set_C_periph,
.mux_D_periph = at91_mux_pio3_set_D_periph,
.set_deglitch = at91_mux_pio3_set_deglitch,
.set_debounce = at91_mux_pio3_set_debounce,
.set_pulldown = at91_mux_pio3_set_pulldown,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
};
static struct at91_pinctrl_mux_ops sama5d3_ops = {
.mux_A_periph = at91_mux_pio3_set_A_periph,
.mux_B_periph = at91_mux_pio3_set_B_periph,
.mux_C_periph = at91_mux_pio3_set_C_periph,
.mux_D_periph = at91_mux_pio3_set_D_periph,
.set_deglitch = at91_mux_pio3_set_deglitch,
.set_debounce = at91_mux_pio3_set_debounce,
.set_pulldown = at91_mux_pio3_set_pulldown,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
};
static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
{
writel(mask, &pio->pdr);
}
static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
{
writel(mask, &pio->per);
writel(mask, (input ? &pio->odr : &pio->oer));
}
static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
struct at91_port *pio, u32 mask, enum at91_mux mux)
{
at91_mux_disable_interrupt(pio, mask);
switch (mux) {
case AT91_MUX_GPIO:
at91_mux_gpio_enable(pio, mask, 1);
break;
case AT91_MUX_PERIPH_A:
ops->mux_A_periph(pio, mask);
break;
case AT91_MUX_PERIPH_B:
ops->mux_B_periph(pio, mask);
break;
case AT91_MUX_PERIPH_C:
if (!ops->mux_C_periph)
return -EINVAL;
ops->mux_C_periph(pio, mask);
break;
case AT91_MUX_PERIPH_D:
if (!ops->mux_D_periph)
return -EINVAL;
ops->mux_D_periph(pio, mask);
break;
}
if (mux)
at91_mux_gpio_disable(pio, mask);
return 0;
}
static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
struct at91_port *pio, u32 pin, u32 config)
{
u32 mask = BIT(pin);
if ((config & PULL_UP) && (config & PULL_DOWN))
return -EINVAL;
at91_mux_set_output(pio, mask, config & OUTPUT,
(config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
at91_mux_set_pullup(pio, mask, config & PULL_UP);
at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
if (ops->set_deglitch)
ops->set_deglitch(pio, mask, config & DEGLITCH);
if (ops->set_debounce)
ops->set_debounce(pio, mask, config & DEBOUNCE,
(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
if (ops->set_pulldown)
ops->set_pulldown(pio, mask, config & PULL_DOWN);
if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
ops->disable_schmitt_trig(pio, mask);
if (ops->set_drivestrength)
ops->set_drivestrength(pio, pin,
(config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
return 0;
}
static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
{
struct at91_pinctrl_priv *priv = dev_get_priv(dev);
if (bank >= priv->nbanks) {
debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
return -EINVAL;
}
if (pin >= MAX_NB_GPIO_PER_BANK) {
debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
return -EINVAL;
}
return 0;
}
static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
struct at91_pinctrl_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node = config->of_offset;
u32 cells[MAX_PINMUX_ENTRIES];
const u32 *list = cells;
u32 bank, pin;
u32 conf, mask, count, i;
int size;
int ret;
enum at91_mux mux;
struct at91_port *pio;
struct at91_pinctrl_mux_ops *ops =
(struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
/*
* the binding format is atmel,pins = <bank pin mux CONFIG ...>,
* do sanity check and calculate pins number
*/
size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
cells, ARRAY_SIZE(cells));
/* we do not check return since it's safe node passed down */
count = size >> 2;
if (!count)
return -EINVAL;
for (i = 0; i < count; i++) {
bank = *list++;
pin = *list++;
mux = *list++;
conf = *list++;
ret = at91_pin_check_config(dev, bank, pin);
if (ret)
return ret;
pio = priv->reg_base[bank];
mask = BIT(pin);
ret = at91_pmx_set(ops, pio, mask, mux);
if (ret)
return ret;
ret = at91_pinconf_set(ops, pio, pin, conf);
if (ret)
return ret;
}
return 0;
}
const struct pinctrl_ops at91_pinctrl_ops = {
.set_state = at91_pinctrl_set_state,
};
static int at91_pinctrl_probe(struct udevice *dev)
{
struct at91_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr_base;
int index;
for (index = 0; index < MAX_GPIO_BANKS; index++) {
addr_base = dev_get_addr_index(dev, index);
if (addr_base == FDT_ADDR_T_NONE)
break;
priv->reg_base[index] = (struct at91_port *)addr_base;
}
priv->nbanks = index;
return 0;
}
static const struct udevice_id at91_pinctrl_match[] = {
{ .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
{ .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
{ .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
{}
};
U_BOOT_DRIVER(at91_pinctrl) = {
.name = "pinctrl_at91",
.id = UCLASS_PINCTRL,
.of_match = at91_pinctrl_match,
.probe = at91_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
.ops = &at91_pinctrl_ops,
};

13
drivers/serial/ns16550.c
View file

@ -452,8 +452,7 @@ const struct dm_serial_ops ns16550_serial_ops = {
.setbrg = ns16550_serial_setbrg,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
#if CONFIG_IS_ENABLED(OF_CONTROL)
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
/*
* Please consider existing compatible strings before adding a new
* one to keep this table compact. Or you may add a generic "ns16550"
@ -473,13 +472,16 @@ static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ti,dra742-uart", .data = PORT_NS16550 },
{}
};
#endif
#endif /* OF_CONTROL && !OF_PLATDATA */
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
/* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */
#if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)
U_BOOT_DRIVER(ns16550_serial) = {
.name = "ns16550_serial",
.id = UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL)
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = ns16550_serial_ids,
.ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
@ -490,5 +492,6 @@ U_BOOT_DRIVER(ns16550_serial) = {
.flags = DM_FLAG_PRE_RELOC,
};
#endif
#endif /* !OF_PLATDATA */
#endif /* SERIAL_PRESENT */
#endif /* CONFIG_DM_SERIAL */

2
include/configs/at91-sama5_common.h
View file

@ -27,7 +27,9 @@
#define CONFIG_ENV_VARS_UBOOT_CONFIG
/* general purpose I/O */
#ifndef CONFIG_DM_GPIO
#define CONFIG_AT91_GPIO
#endif
/*

45
include/configs/sama5d4_xplained.h
View file

@ -12,32 +12,21 @@
#include "at91-sama5_common.h"
/* serial console */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_USART3
#define CONFIG_USART_ID ATMEL_ID_USART3
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x210000
#define CONFIG_SYS_INIT_SP_ADDR 0x218000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* SerialFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
@ -58,32 +47,6 @@
#define CONFIG_ATMEL_NAND_HW_PMECC
#endif
/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#endif
/* USB device */
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK"
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
/* LCD */
#ifdef CONFIG_LCD
#define LCD_BPP LCD_COLOR16
@ -107,7 +70,7 @@
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
@ -137,7 +100,7 @@
#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
#endif

45
include/configs/sama5d4ek.h
View file

@ -12,32 +12,21 @@
#include "at91-sama5_common.h"
/* serial console */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_USART3
#define CONFIG_USART_ID ATMEL_ID_USART3
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x210000
#define CONFIG_SYS_INIT_SP_ADDR 0x218000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* SerialFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
@ -58,32 +47,6 @@
#define CONFIG_ATMEL_NAND_HW_PMECC
#endif
/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#endif
/* USB device */
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK"
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
/* LCD */
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 18
@ -105,7 +68,7 @@
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
@ -135,7 +98,7 @@
#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
#endif

2
include/dt-bindings/pinctrl/at91.h
View file

@ -15,6 +15,8 @@
#define AT91_PINCTRL_DEGLITCH (1 << 2)
#define AT91_PINCTRL_PULL_DOWN (1 << 3)
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_OUTPUT (1 << 7)
#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)

40
lib/libfdt/fdt_region.c
View file

@ -63,6 +63,30 @@ static int region_list_contains_offset(struct fdt_region_state *info,
return 0;
}
/**
* fdt_add_alias_regions() - Add regions covering the aliases that we want
*
* The /aliases node is not automatically included by fdtgrep unless the
* command-line arguments cause to be included (or not excluded). However
* aliases are special in that we generally want to include those which
* reference a node that fdtgrep includes.
*
* In fact we want to include only aliases for those nodes still included in
* the fdt, and drop the other aliases since they point to nodes that will not
* be present.
*
* This function scans the aliases and adds regions for those which we want
* to keep.
*
* @fdt: Device tree to scan
* @region: List of regions
* @count: Number of regions in the list so far (i.e. starting point for this
* function)
* @max_regions: Maximum number of regions in @region list
* @info: Place to put the region state
* @return number of regions after processing, or -FDT_ERR_NOSPACE if we did
* not have enough room in the regions table for the regions we wanted to add.
*/
int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
int max_regions, struct fdt_region_state *info)
{
@ -74,11 +98,17 @@ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
if (node < 0)
return -FDT_ERR_NOTFOUND;
/* The aliases node must come before the others */
/*
* Find the next node so that we know where the /aliases node ends. We
* need special handling if /aliases is the last node.
*/
node_end = fdt_next_subnode(fdt, node);
if (node_end <= 0)
return -FDT_ERR_BADLAYOUT;
node_end -= sizeof(fdt32_t);
if (node_end == -FDT_ERR_NOTFOUND)
/* Move back to the FDT_END_NODE tag of '/' */
node_end = fdt_size_dt_struct(fdt) - sizeof(fdt32_t) * 2;
else if (node_end < 0) /* other error */
return node_end;
node_end -= sizeof(fdt32_t); /* Move to FDT_END_NODE tag of /aliases */
did_alias_header = 0;
info->region = region;
@ -109,7 +139,7 @@ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
fdt_add_region(info, base + offset, next - offset);
}
/* Add the 'end' tag */
/* Add the FDT_END_NODE tag */
if (did_alias_header)
fdt_add_region(info, base + node_end, sizeof(fdt32_t));

2
tools/Makefile
View file

@ -120,7 +120,7 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS)
libfdt:
tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c
LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= python $(srctree)/lib/libfdt/setup.py \
LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= ${PYTHON} $(srctree)/lib/libfdt/setup.py \
"$(_hostc_flags)" $^
mv _libfdt.so $@

5
tools/buildman/builder.py
View file

@ -95,8 +95,9 @@ u-boot/ source directory
# Possible build outcomes
OUTCOME_OK, OUTCOME_WARNING, OUTCOME_ERROR, OUTCOME_UNKNOWN = range(4)
# Translate a commit subject into a valid filename
trans_valid_chars = string.maketrans("/: ", "---")
# Translate a commit subject into a valid filename (and handle unicode)
trans_valid_chars = string.maketrans('/: ', '---')
trans_valid_chars = trans_valid_chars.decode('latin-1')
BASE_CONFIG_FILENAMES = [
'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg'

2
tools/dtoc/fdt_util.py
View file

@ -24,6 +24,8 @@ def fdt32_to_cpu(val):
A native-endian integer value
"""
if sys.version_info > (3, 0):
if isinstance(val, bytes):
val = val.decode('utf-8')
val = val.encode('raw_unicode_escape')
return struct.unpack('>I', val)[0]

3
tools/fdtgrep.c
View file

@ -810,9 +810,6 @@ static int do_fdtgrep(struct display_info *disp, const char *filename)
disp->flags);
if (count < 0) {
report_error("fdt_find_regions", count);
if (count == -FDT_ERR_BADLAYOUT)
fprintf(stderr,
"/aliases node must come before all other nodes\n");
return -1;
}
if (count <= max_regions)

4
tools/patman/cros_subprocess.py
View file

@ -190,6 +190,8 @@ class Popen(subprocess.Popen):
# We will get an error on read if the pty is closed
try:
data = os.read(self.stdout.fileno(), 1024)
if isinstance(data, bytes):
data = data.decode('utf-8')
except OSError:
pass
if data == "":
@ -205,6 +207,8 @@ class Popen(subprocess.Popen):
# We will get an error on read if the pty is closed
try:
data = os.read(self.stderr.fileno(), 1024)
if isinstance(data, bytes):
data = data.decode('utf-8')
except OSError:
pass
if data == "":