Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 23:24:38 +00:00
Code Issues Projects Releases Packages Wiki Activity

net: mvpp2x: fix phy connected to wrong mdio issue

Browse source 
A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.

Issue:
Wrong base address is assigned to MDIO interface during probe.

Fix:
Get MDIO address from PHY handler parent base address.

This should be refined in the future when MDIO driver is implemented.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Chulski 2017-08-09 10:37:44 +03:00 committed by Stefan Roese
parent 4189373a3d
commit 377883f16d
1 changed files with 25 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

26
drivers/net/mvpp2.c
View file

@ -31,6 +31,7 @@
#include <linux/compat.h>
#include <linux/mbus.h>
#include <asm-generic/gpio.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
@ -4739,10 +4740,11 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
{
int port_node = dev_of_offset(dev);
const char *phy_mode_str;
int phy_node;
int phy_node, mdio_off, cp_node;
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
u64 mdio_addr;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
@ -4752,6 +4754,28 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
dev_err(&pdev->dev, "could not find phy address\n");
return -1;
}
mdio_off = fdt_parent_offset(gd->fdt_blob, phy_node);
/* TODO: This WA for mdio issue. U-boot 2017 don't have
* mdio driver and on MACHIATOBin board ports from CP1
* connected to mdio on CP0.
* WA is to get mdio address from phy handler parent
* base address. WA should be removed after
* mdio driver implementation.
*/
mdio_addr = fdtdec_get_uint(gd->fdt_blob,
mdio_off, "reg", 0);
cp_node = fdt_parent_offset(gd->fdt_blob, mdio_off);
mdio_addr |= fdt_get_base_address((void *)gd->fdt_blob,
cp_node);
port->priv->mdio_base = (void *)mdio_addr;
if (port->priv->mdio_base < 0) {
dev_err(&pdev->dev, "could not find mdio base address\n");
return -1;
}
} else {
phy_node = 0;
}