Commit graph

14439 commits

Author SHA1 Message Date
Bin Meng
7bdf39cfaf x86: efi: payload: Add default TSC frequency in the device tree
It was observed sometimes U-Boot as the EFI payload fails to boot on
QEMU. This is because TSC calibration fails with no valid frequency.
This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-20 13:52:49 +08:00
Bin Meng
864915561b x86: coreboot: Add default TSC frequency in the device tree
It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-08-20 13:52:49 +08:00
Bin Meng
1cf6825a68 x86: dts: Remove coreboot_fb.dtsi
There is no need to keep a separate coreboot_fb.dtsi since now we
have a generic coreboot payload dts.

While we are here, this also remove the out-of-date description in
the documentation regarding to coreboot framebuffer driver with
U-Boot loaded as a payload from coreboot. As the testing result with
QEMU 2.5.0 shows, the driver just works like a charm.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-20 13:52:49 +08:00
Bin Meng
6e71a6ab2d x86: Remove support for Advantech SOM-6896
Now that we have generic coreboot payload support, remove the
dedicated support for Advantech SOM-6896.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-08-20 13:52:49 +08:00
Bin Meng
ceeee8f7b5 x86: coreboot: Add generic coreboot payload support
Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.

But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-08-20 13:52:06 +08:00
Adam Ford
d7869b2183 Convert CONFIG_MII et al to Kconfig
This converts the following to Kconfig:
   CONFIG_MII
   CONFIG_DRIVER_TI_EMAC

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-17 13:03:54 -04:00
Tom Rini
8297e648b8 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-08-17 07:25:04 -04:00
Tom Rini
719afeb0b3 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-08-17 07:24:34 -04:00
Tom Rini
86cf1c8285 configs: Migrate CONFIG_NR_DRAM_BANKS
We have the following cases:
- CONFIG_NR_DRAM_BANKS was defined, migrate normally
- CONFIG_NR_DRAM_BANKS_MAX was defined and then used for
  CONFIG_NR_DRAM_BANKS after a check, just migrate it over now.
- CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 +
  2), set this to 8.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-16 16:45:02 -04:00
Tom Rini
0bdea7c430 CONFIG_SYS_GENERIC_BOARD: Finish migration
While we have long since migrated to CONFIG_SYS_GENERIC_BOARD being
enabled, we had just a few places left that still referenced or defined
it.  Update.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-16 16:45:02 -04:00
Ley Foon Tan
b0c0a715f9 arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-15 12:41:09 +02:00
Marek Vasut
4f10989280 ARM: rmobile: Enable USB PHY on Gen2
Enable support for USB PHY on the R-Car Gen2. This allows for both
of the USB host ports to be used on such boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-08-14 11:31:25 +02:00
Marek Vasut
d81b5da3fe ARM: socfpga: clk: Convert to clock framework
Use clock framework functions to fetch clock information now that there
is a clock driver for Arria10, instead of custom coded register parsing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
ccc97432ad ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodes
Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
f4c3e0dcf5 ARM: socfpga: clk: Drop unused variables on Arria10
The variables removed in this patch are never used, they are only ever
assigned and then waste precious memory. Drop both the assignment and
the variables.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
49e508e962 ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
934aec71d6 ARM: socfpga: clk: Obtain handoff base clock via DM
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
d6a61da462 ARM: socfpga: Remove adhoc ethernet reset and configuration
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
6385a8a964 ARM: socfpga: Zap unused reset code
Remove code from the reset manager that is never called.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
f9edeb32a9 ARM: socfpga: Zap all the UART handling complexity
The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-08-13 22:35:40 +02:00
Marek Vasut
fe88c2fea7 ARM: socfpga: Enable DM I2C framework on A10
Enable the DM I2C framework on Arria10, so that the DM capable
Designware I2C driver can handle the reset via DM reset framework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:17 +02:00
Marek Vasut
8145c1c299 ARM: socfpga: Enable DM reset framework on A10
Enable the DM reset framework and DM reset driver on Arria10 both
in U-Boot and in SPL. This lets U-Boot parse reset control from DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:17 +02:00
Marek Vasut
c29508045f ARM: dts: socfpga: Add i2c alias to A10 SoCDK
The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign
the I2C bus a bus number. Add the missing alias.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
3d8685f155 ARM: dts: socfpga: Add missing I2C resets
The I2Cx resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
da61e50fc4 ARM: dts: socfpga: Fix Arria10 GMAC resets
Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs
to work and add GMAC2 reset and OCP resets which were missing altogether.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
f5775e69cc ARM: dts: socfpga: Add missing UART resets
The UART0 and UART1 resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
6f96ed7e20 ARM: dts: socfpga: Flag reset manager on A10 as pre-reloc
The Altera reset manager block must be available very early on, since
it controls ie. UART resets. Flag it as pre-reloc.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
af74658e04 ARM: socfpga: Register the FPGA on A10 in SPL again
The restructuring of the SPL dropped registration of the FPGA in SPL,
readd it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Fixes: c859f2a77d ("arm: socfpga: Restructure the SPL file")
2018-08-13 22:35:16 +02:00
Simon Goldschmidt
e4ff8420c5 arm: socfpga: gen5: combine some init code for SPL and U-Boot
Some of the code for low level system initialization in SPL's
board_init_f() and U-Boot's arch_early_init_r() is the same,
so let's combine it into a single function called from both.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 22:35:06 +02:00
Simon Goldschmidt
79a436d568 arm: socfpga: fix device trees to work with DM serial
Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 22:35:06 +02:00
Patrick Delaunay
2deaf5cc63 ARM: dts: stm32f4: Fix DT dtc warnings
This patch fix the following warnings for for stm32f429
evaluation and discovery boards:

unnecessary #address-cells/#size-cells without "ranges" or
child "reg" property

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
638ee5af6b ARM: dts: stm32mp157: Add ADC DT node
Add ADC device tree node. This allows to get analog conversions on
stm32mp157.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
6effb56fbc ARM: dts: stm32: remove cd-inverted for stm32f746-disco
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.

Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
4c55c83989 ARM: dts: stm32: remove cd-inverted for stm32f769-disco
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.

Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Ramon Fried
e0b04a1525 snapdragon: added MAC generation functions
Add support for generation of unique MAC address
that is derived from board serial.
Algorithm for generation of MAC taken from LK.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-13 14:04:04 -04:00
Ramon Fried
86e5e42946 snapdragon: added msm_board_serial() func
This commit adds a function to get the board
serial number.
In snapdragon it's actually the eMMC serial number.

Function added in a new file misc.c that will
include further snapdragon miscellaneous functions.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-13 14:04:04 -04:00
Thomas Fitzsimmons
dc7685e2c5 arm: bcm7445: Fix parallel make race condition
Move the contents of prior_stage.h into bcmstb.h to prevent a build
failure when bcmstb.h is #include'ed before the asm/arch symbolic link
is present.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
2018-08-13 14:03:57 -04:00
Tom Rini
b8a1f47be3 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-08-13 12:34:55 -04:00
Simon Goldschmidt
c0b4fc1a1b arm: socfpga: cyclone5: handle debug uart
If CONFIG_DEBUG_UART is enabled, correctly initialize
the debug uart before console is initialized to debug
early boot problems in SPL.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 15:29:54 +02:00
Simon Goldschmidt
20905f5fa6 arm: socfpga: spl_gen5: clean up malloc_base assignment
In spl_gen5's board_init_f(), gd->malloc_base is manually assigned
at the end of the function to point to sdram.  This code is outdated
as by now, the heap is switched to sdram by the common function
spl_relocate_stack_gd() if the appropriate defines are set.

As it was, the value assigned manually was directly overwritten by
this common code, so remove the manual assignment.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 15:29:54 +02:00
Simon Goldschmidt
40c36f8d49 arm: socfpga: fix SPL on gen5 after moving to DM serial
There were NULL pointers dereferenced because DM was used
too early without correct initialization:
- malloc_simple returned NULL when called from preloader_console_init()
  because gd->malloc_limit was 0
- uclass_add dereferenced gd->uclass_root members which were NULL because
  dm_init (or one of its relatives) has not been called.

All this is fixed by calling spl_early_init before calling
preloader_console_init.

This fixes commit 73172753f4 ("ARM: socfpga: Convert to DM serial")

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 15:29:54 +02:00
Andre Przywara
8094f0cb0c sunxi: A64: fix default DRAM_ODT_EN symbol
"default" lines in Kconfig are processed in order, the first hit will
stop considering subsequent lines. In the case of the DRAM_ODT_EN symbol
that means that everything following the first two lines will never be
checked:
------------
config DRAM_ODT_EN
	bool "sunxi dram odt enable"
	default n if !MACH_SUN8I_A23
	default y if MACH_SUN8I_A23
	default y if MACH_SUN8I_R40
	default y if MACH_SUN50I
------------

Assuming that the "default y" for the A64 and the R40 were a deliberate
choice, fix the Kconfig stanza to take this into account.
Also remove the now redundant lines from the respective defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: droped 'default n' on original change]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # A64, R40
Tested-by: Chen-Yu Tsai <wens@csie.org> # A23
2018-08-13 16:47:38 +05:30
Jagan Teki
25b3d90b2c ARM: dts: sun8i: Update R40/V40 dts(i) files from Linux-v4.18-rc3
Update all R40/V40 devicetree dtsi and dtsi files from Linux-v4.18-rc3
with below commit:

R40:
commit c36fd5a48bd20820855e3e91a89297eeaa31836e
Author: Chen-Yu Tsai <wens@csie.org>
Date:   Wed May 2 00:12:25 2018 +0800

    ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable GMAC ethernet controller

V40:
commit c5f0bb472795170ab5c33be12e29ce7465fb31ed
Author: Icenowy Zheng <icenowy@aosc.io>
Date:   Fri Apr 6 22:03:44 2018 +0800

    ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # BPI-M2-Ultra, BPI-M2-Berry
2018-08-13 13:10:09 +05:30
Jagan Teki
0ca4d40cfe ARM: dts: sun8i: Update A83T dts(i) files from Linux-v4.18-rc3
Update all A83T devicetree dtsi and dtsi files from Linux-v4.18-rc3
with below commit:
commit 221cb9fd2ee3042689fe0e6613d0f34eb46a5af6
Author: Mylène Josserand <mylene.josserand@bootlin.com>
Date:   Fri May 4 21:05:44 2018 +0200

    ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

Note: bananapi-m3 and cubietruck-plus board dts files has
usb_otg enabled in U-Boot which were not present in Linux.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-08-13 13:07:35 +05:30
Tom Rini
8fee226da3 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2018-08-11 19:49:29 -04:00
Tom Rini
282ce6454c Merge branch 'master' of git://git.denx.de/u-boot-video 2018-08-11 19:48:13 -04:00
Mario Six
004e67c216 test: Add tests for misc uclass
Add a set of tests for the misc uclass.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-11 16:00:38 +02:00
Mario Six
957983e00b sandbox: Add and build AXI bus and device
Add test AXI drivers to the sandbox.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-11 08:10:07 +02:00
Mario Six
9a8bcabd8a axi: Add AXI sandbox driver and simple emulator
Add test infrastructure and tests for the AXI uclass.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-11 08:09:39 +02:00
Ramon Fried
36adb7c9e8 snapdragon: Add DRAM detection & FDT fixup
Fixup the Linux FDT with the detection of onboard DRAM as
provided by SBL (Secondary boot loader) by reading
the shared-memory region.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-10 13:45:35 -04:00
Ran Wang
9add5a4b75 armv8: layerscape: Enable EHCI access for LS1012A
Program Central Security Unit (CSU) to grant access to USB 2.0
controller.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: rewrite commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:37:39 -07:00
Ran Wang
cd35855492 armv8: layerscape: move ns_dev[] define from h to c file.
Move ns_dev[] from header file to C file to avoid compiling warning
when header file is included by others.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: rewrite commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:36:03 -07:00
Laurentiu Tudor
5651f438f8 armv8: ls1046a: setup SEC ICIDs and fix up device tree
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.

Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:46 -07:00
Laurentiu Tudor
b50ff5e1b6 armv8: ls1046a: setup fman ports ICIDs and device tree
Add support for ICID setting of fman ports and the required device
tree fixups.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:42 -07:00
Laurentiu Tudor
599a97d49c armv8: ls1046a: add icid setup for qman portals
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:36 -07:00
Laurentiu Tudor
3cb4fe65f9 armv8: ls1046a: initial icid setup support
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:33 -07:00
Laurentiu Tudor
703d18f7fe armv8: fsl-layerscape: add missing debug stream ID
Add a define with a value for the missing debug stream ID.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:29 -07:00
Laurentiu Tudor
92d2e89c8c misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:22 -07:00
Laurentiu Tudor
5bdfdb7d4f armv8: ls1046a: advertise QMan v3 in configuration
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:11 -07:00
Laurentiu Tudor
fa0706ef92 armv8: fsl-layerscape: add missing register blocks base address defines
Add defines for the edma and qdma register block base addresses.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:34:42 -07:00
Patrick Delaunay
8e1665102f stm32mp1: add gpio led support
This patch add the 4 LED available on the ED1 board and activated
gpio led driver.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-08-10 10:27:32 -04:00
Tom Rini
cdec3ea7e4 Merge branch 'master' of git://git.denx.de/u-boot-usb 2018-08-10 07:21:02 -04:00
Tom Rini
b243f41f12 Merge git://git.denx.de/u-boot-dm 2018-08-09 11:10:41 -04:00
Tom Rini
9d17682a57 Merge branch 'master' of git://git.denx.de/u-boot-mips 2018-08-08 20:02:39 -04:00
Alberto Panizzo
f68c8e827c usb: rockchip: implement K_FW_LBA_ERASE_10 command
This command is part of the write partition sequence performed by
rkdeveloptool: one partition is first completely erased and
than wrote.

Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 22:22:07 +02:00
Alberto Panizzo
e11f9166f3 usb: rockchip: implement K_FW_LBA_READ_10 command
This patch implement reading blocks form selected device with
LBA addressing.

Corresponding command on workstation is:
rkdeveloptool rl <start_blk> <blk_cnt> <file>

While we support reading more than one blocks per K_FW_LBA_READ_10
request, rkdeveloptool and original rockchip tool do perform
chunk reads limiting the maximum size per chunk far lower
than max int values.

Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 22:22:07 +02:00
Bin Meng
95e11069b5 test: dm: pci: Add cases for finding PCI capability APIs
Add several PCI capability and extended capability ID registers
in the swap_case driver, so that we can add test case for
dm_pci_find_capability() and dm_pci_find_ext_capability().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
3ed214ac9b test: dm: pci: Add tests for mixed static and dynamic devices on the same bus
In the Sandbox test configuration, PCI bus#0 only has static devices
while bus#1 only has dynamic devices. Create a bus#2 that has both
types of devices and test such.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
490d13a523 sandbox: Update test.dts for dynamic PCI device driver matching
At present we have two PCI buses in the test configuration. Both
buses have static device-tree config devices. Now we switch the
2nd bus to use dynamic PCI devices for testing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
59a160e8b9 pci: sandbox: swap_case: Declare dynamic driver matching
This adds a U_BOOT_PCI_DEVICE() declaration to the swap_case driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
dee4d752be test: dm: pci: Test more than one PCI host controller
So far there is only one PCI host controller in the sandbox test
configuration. This is normally the case for x86, but it can be
common on other architectures like ARM/PPC to have more than one
PCI host controller in the system.

This updates the case to cover such scenario.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
2db7f2b722 test: dm: pci: Test more than one device on the same bus
It's quite common to have more than one device on the same PCI bus.
This updates the test case to test such scenario.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Philippe Reynes
990cebf0a2 bcm968380gerg: add initial support
This add the initial support of the broadcom reference
board bcm968380gerg with a bcm68380 SoC.

This board has 512 MB of RAM, 128 MB of flash (nand),
2 USB port, 1 UART, 4 ethernet ports and BCM43217 (wifi).

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:38:17 +02:00
Philippe Reynes
341032d3f1 bcm6838: add initial support
This adds the initial support of the Broadcom BCM6838 SoC familly,
only cpu, dram, uart and leds are supported.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:38:17 +02:00
Tom Rini
481ea2e39d mips: au1x00: Remove support for these SoCs
The only platform left for the AU1x00 SoCs was the pb1x00 platform, an
apparent clone of the dbau1x00 platform.  As pb1x00 had no listed
maintainer I am assuming that it is also orphaned.  Remove this platform
and then remove the unused SoC support.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:34:27 +02:00
Tom Rini
215b4fae51 mips: dbau1x00: Remove this board
This platform has been marked as orphan since June of 2016 and should
have been removed some time ago.  Do so now.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:33:51 +02:00
Tom Rini
fc82e7684b Merge branch 'master' of git://git.denx.de/u-boot-samsung 2018-08-07 21:36:20 -04:00
Brendan Shanks
e784cf1bf2 arm: ls102xa: Fix RGMII phy-connection-type FDT fixup
In ft_fixup_enet_phy_connect_type(), use strlen() instead of sizeof()
on the pointer result of phy_string_for_interface(). sizeof() was
returning the size of the pointer (4 bytes), resulting in the
phy-connection-type being set to "rgmi" rather than "rgmii-id".

Signed-off-by: Brendan Shanks <brendan.shanks@teradek.com>
Cc: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-07 14:42:15 -07:00
Tom Rini
188ebc7b59 Xilinx fixes for v2018.09-rc2
xilinx:
 - Add support for zybo z7 and ultra96
 - Tune zynq and zynqmp mini configurations
 - Move SYS_MALLOC_LEN to Kconfig
 
 fdt
  - make static funcs
 
 gpio:
 - Fix soft gpio driver
 - Fix Zynq gpio driver by using platdata
 
 microblaze:
 - Fix Kconfig entry
 
 spi
 - Move ISSI to Kconfig
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Merge tag 'xilinx-for-v2018.09-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx fixes for v2018.09-rc2

xilinx:
- Add support for zybo z7 and ultra96
- Tune zynq and zynqmp mini configurations
- Move SYS_MALLOC_LEN to Kconfig

fdt
 - make static funcs

gpio:
- Fix soft gpio driver
- Fix Zynq gpio driver by using platdata

microblaze:
- Fix Kconfig entry

spi
- Move ISSI to Kconfig
2018-08-07 11:32:50 -04:00
Luis Araneda
a492fdffa3 arm: zynq: dts: add spi flash node to zedboard
Add a flash node to fix the detection of the memory IC.
With the changes introduced with commit 8fee8845e7
("enf_sf: reuse setup_flash_device instead of open coding it")
the SPI speed is now read from device-tree or a default value
is applied. This replaced the old behavior of setting the
SPI speed to CONFIG_ENV_SPI_MAX_HZ.

As this board didn't have a flash node, the default value
was applied to the SPI speed, producing an error when probing
the flash memory (speed too slow).

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-07 11:03:43 +02:00
Chris Packham
a6477f7cbc ARM: kirkwood: add SBx81LIFXCAT board
This is a series of line cards for Allied Telesis's SBx8100 chassis
switch. The CPU block is common to the SBx81GP24 and SBx81GT24 cards
cards collectively referred to as SBx81LIFXCAT in u-boot.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Jon Nettleton
14deee2081 arm: mvebu: clearfog: add u-boot, dm-spl tag for spi
This is required so SPL and u-boot can boot from spi
flash devices that use the dm drivers.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: use -u-boot.dtsi]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Baruch Siach
69601ce003 arm: mvebu: helios4: remove duplicate sdhci pins node
The same pinctrl node appears in the solidrun-microsom dtsi. Use that
instead.

Cc: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Dennis Gilmore <dennis@ausil.us>
Tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Jon Nettleton
334eebefc2 arm: mvebu: Better align Clearfog dts file with Linux kernel
This makes changes so the u-boot dts file is structured more
similar to the mainline linux dtsi file.  It provides a minimal
common dts that can work for most boards based on the ClearFog
platform.  Ethernet support is only supported for eth0 however
all devices are left enabled so u-boot can generate and
provide mac addresses for all of the network interfaces.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: rebase on recent changes]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Dennis Gilmore <dennis@ausil.us>
Tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Baruch Siach
a4adb1f576 arm: mvebu: clearfog: use the microsom .dtsi
Use hardware description from the recently introduced microsom .dtsi
file to reduce duplication.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Dennis Gilmore <dennis@ausil.us>
Tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Baruch Siach
bf3eaa3e5c arm: mvebu: solidrun-microsom: update SPI flash compatible
Add the "spi-flash" compatible string so that the generic sf_probe
driver can probe the SPI flash on the SolidRun SOM.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Baruch Siach
72c4e67d08 mvebu: support UART boot image
The kwboot utility can use the generated image to boot mvebu SoCs from
UART.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06 14:07:23 +02:00
Baruch Siach
ca1a4c8632 mvebu: select boot device at SoC level
Move the gdsys Controlcenter DC specific build time kwbimage.cfg
generation code into the mach-mvebu/ directory to be shared by all 32bit
mvebu platforms.

Remove board specific kwbimage.cfg files, and use the generated one
instead. These files are all identical, with two exceptions. Clearfog
and Helios4 use the sdio boot device, whereas all others use spi. Update
the defconfigs for the exceptional boards to generate the same
kwbimage.cfg as before.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06 14:07:23 +02:00
Baruch Siach
ad105f5f86 mvebu: consolidate SPL boot device config symbols
Use MVEBU_SPL_BOOT_DEVICE_* to select between SPI and MMC, instead of
board specific symbols. This commit enables the boot device selection
menu to all mvebu platforms, but it is only effective on Turris Omnia
and gdsys Controlcenter DC platforms. A following commit will enable
boot selection for other platforms.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06 14:07:23 +02:00
Baruch Siach
d38f04f7c2 mvebu: a38x: drop duplicate platform id symbols
Use generic mvebu Kconfig symbols like all other mvebu boards.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06 14:07:23 +02:00
Michal Simek
2570e12960 arm64: zynqmp: Add support for Avnet Ultra96
Avnet Ultra96 is rebranded Xilinx zcu100 revC/D. Add new defconfig files
and point to origin internal board name.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Luis Araneda
58f449676a arm: zynq: add support for the zybo z7 board
The board is manufactured by Digilent
Main features:
- Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20)
- RAM: 1 GB DDR3L
- FLASH: 16 MB QSPI
- 1 Gbps Ethernet
- USB 2.0
- microSD slot
- Pcam camera connector
- HDMI Tx and Rx
- Audio codec: stereo out, stereo in, mic
- 5 (Z7-10) or 6 (Z7-20) Pmod ports
- 6 push-buttons, 4 switches, 5 LEDs
- 1 (Z7-10) or 2 (Z7-20) RGB LEDs

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Siva Durga Prasad Paladugu
01aa5b8f05 Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq
This patch moves the the config SYS_MALLOC_LEN to
Kconfig. It will be just for Zynq arch and to do
will be for all other archs.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Michal Simek
df09969070 arm: zynq: Fix indentation for zynq-cse targets
Trivial DT style fixes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Michal Simek
7996fcca9d arm: zynq: Remove fclk-enable property for cse-nor target
Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Michal Simek
92226b5a6d arm: zynqmp: Fix sdhci clock in emmc1 mini configuration
Add missing clocks property with fix clock-names property to be aligned
with emmc0 configuration and binding doc.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Minkyu Kang
972d8576d2 arm: spring: fix alias of mmc correctly
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06 11:24:48 +09:00
Minkyu Kang
2f43135551 arm: exynos5: fix warning of dts
remove this warning: avoid_unnecessary_addr_size

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06 11:24:45 +09:00
Minkyu Kang
8d93a31014 arm: exynos4: fix warning of dts
remove this warning: avoid_unnecessary_addr_size

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06 11:24:42 +09:00
Tom Rini
0cba6e906a Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-08-04 19:41:30 -04:00
Patrice Chotard
11c1b55827 ARM: dts: stm32: remove cd-inverted for stm32429i-eval
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.

Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-03 19:53:54 -04:00
Andre Przywara
1416e2d225 armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.

On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.

Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03 19:53:54 -04:00
Andre Przywara
15b6184971 armv8: Reduce exception handling code
The arm64 exception handling code is quite big, mostly due to
architectural alignment requirements. Each exception entry spans 32
instructions, which sounds generous, but is too small to fit all of the
save/branch/restore code in there. So at the moment we use only four
instructions, branching into shared save and restore routines.
To not leave the space for those remaining 28 instructions wasted, let's
split the save and restore routines and stuff them into the gaps.
This saves about 250 bytes of code, which is helpful for those tight
SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03 19:53:54 -04:00
Fabrice Gasnier
1fe243a1e4 clk: add clk_valid()
Add clk_valid() to check for optional clocks are valid.
Call clk_valid() in test/dm/clk.c and add relevant test routine to
sandbox clk tests.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-03 19:53:10 -04:00
Tom Rini
a30691a538 Merge git://git.denx.de/u-boot-dm 2018-08-03 10:08:13 -04:00
Stephen Warren
a839c3641e ARM: tegra: align carveout size
Align the size of the carveout region to 2M. This ensures that the size
can be accurately represented by an LPAE page table that uses sections.

This solves a bug (hang at boot time soon after printing the DRAM size)
that only shows up when the following two commits are merged together:
d32e86bde8 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
6e584e633d ARM: tegra: avoid using secure carveout RAM

Cc: Mark Kettenis <kettenis@openbsd.org>
Cc: Alexander Graf <agraf@suse.de>
Acked-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2018-08-01 20:06:10 -04:00
Simon Glass
3ab9598df7 binman: Rename 'position' to 'offset'
After some thought, I believe there is an unfortunate naming flaw in
binman. Entries have a position and size, but now that we support
hierarchical sections it is unclear whether a position should be an
absolute position within the image, or a relative position within its
parent section.

At present 'position' actually means the relative position. This indicates
a need for an 'image position' for code that wants to find the location of
an entry without having to do calculations back through parents to
discover this image position.

A better name for the current 'position' or 'pos' is 'offset'. It is not
always an absolute position, but it is always an offset from its parent
offset.

It is unfortunate to rename this concept now, 18 months after binman was
introduced. However I believe it is the right thing to do. The impact is
mostly limited to binman itself and a few changes to in-tree users to
binman:

   tegra
   sunxi
   x86

The change makes old binman definitions (e.g. downstream or out-of-tree)
incompatible if they use the 'pos = <...>' property. Later work will
adjust binman to generate an error when it is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-08-01 16:30:06 -06:00
Tom Rini
61523dde17 Merge tag 'arc-updates-for-2018.09-rc2' of git://git.denx.de/u-boot-arc
That's a set of prety minor changes and fixes for ARC.

Among them:
 * Improvement in CREG GPIO driver used on ARC dev boards
   that allow us to re-use the driver for SPI's chip select

 * Enable SPI-flsh on AXS10x boards which allows to update
   U-Boot binary that gets loaded by boot-ROM

 * Fix accommodating always utilized unaligned access by
   GCC for ARC starting from 8.1.0
2018-08-01 09:26:15 -04:00
Michal Simek
b3815fc4e5 dm: Fix CMD_DM enabling
The patch "dm: Change CMD_DM enabling"
(sha1: 08a00cba06) was incorrectly updated
and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice.
This patch is fixing it.

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-31 14:46:22 -04:00
Jagan Teki
89a897fc4d board: sun50i: h6: Add OrangePi One Plus initial support
OrangePi One Plus is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- 1Gbps GMAC via RTL8211
- USB 2.0 Host, OTG
- HDMI port
- 5V/2A DC power supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-31 20:50:01 +05:30
Icenowy Zheng
a8407b5642 sunxi: add support for Pine H64 board
Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features
1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port
and a mPCIE slot.

Add support for it.

The device tree is from Linux next-20180720.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
6f796a9bb4 sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe
interfaces.

This patch adds support for it.

The corresponding DTSI file, from Linux next-20180720, is also
introduced.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
da2616543a sunxi: add DRAM support to H6
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo.
Both the controller and the PHY seem to be originate from DesignWare,
and are similar to the ones in ZynqMP SoCs.

This commit introduces an initial DRAM driver for H6, which contains
only LPDDR3 support. The currently known SBCs with H6 all come with
LPDDR3 memory, including Pine H64 and several Orange Pi's.

The BSP DRAM initialization code is closed source and violates GPL. Code
in this commit is written by experimenting, referring the code/document
of other users of the IPs (mainly the ZynqMP, as it's the only found PHY
reference) and disassebling the BSP blob.

Thanks for Jernej Skrabec for review and fix some issues in this driver
(including the most critical one which made it to work), and rewrite
some code from register dump!

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
42956f1b85 sunxi: add MMC support for H6
The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
the MMC2 come with the capability to do crypto by EMCE.

Add MMC support for H6. EMCE support is not added yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
7f51a4020e sunxi: add UART0 setup for H6
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
muxed with SD card).

Add pinmux configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
10196c9627 sunxi: use sun6i-style watchdog for H6
The H6 SoC has a sun6i-style watchdog in its timer part.

Enable the usage of it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
0558676d4b sunxi: add clock code for H6
The new Allwinner H6 SoC has a brand new CCU layout.

Add clock code for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
80197801f4 sunxi: change RMR64's RVBAR address for H6
Allwinner H6 has a different RVBAR address with A64/H5.

Add conditional RVBAR configuration into the code which does RMR switch.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
e77b7496c6 sunxi: add basic memory map definitions of H6 SoC
The Allwinner H6 SoC come with a totally new memory map.

Add basical definition of the new memory map into a header file, and let
the cpu.h header include it in the situation of H6.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
cadc7c20e5 sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS
The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but
it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored
to support this new configuration.

Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM
A1 in the memory map.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Alexey Brodkin
8f590063ba ARC: Enable unaligned access in hardware if compiler uses it
Even if ARC core might handle unaligned access to data this
hardware feature by default is disabled.

But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores.
Which leads to quite strange and fatal run-time failures like the one
below if HW is not configured properly:
| hsdk# sf probe
| Misaligned data access exception @ 0xbff794d4
| ECR:    0x000d0000
| RET:    0xbff794d4
| BLINK:  0xbff79644
| STAT32: 0x00000800
| GP: 0x1003e000   r25: 0xbfd58f08
| BTA: 0xbff794a4  SP: 0xbfd58cd4  FP: 0xbfd58ef0
| LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000
| r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf
| r03: 0x00000000 r04: 0x00000100 r05: 0x00000000
| r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500
| r09: 0x00000000 r10: 0x00200000 r11: 0x00000000
| r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68
| r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000
| r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40
| r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000
| r24: 0xbfd59ba8
| Resetting CPU ...

Now we're checking for __ARC_UNALIGNED__ define emitted by the
compiler if it's going to use unaligned access and then we
force-enable it in hardware too.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Eugeniy Paltsev
cdfe6913c1 AXS10x: add spi flash support
AXS10x boards have n25q512 spi flash IC, so add corresponding
nodes to device tree and enaple corresponding options in
defconfig.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Eugeniy Paltsev
fe3eb7a887 GPIO: CREG: improve flexibility of hsdk-creg-gpio driver
CREG GPIO is a driver for weird soc-specific output ports, which are
controlled by some fields in memory mapped register.

Example:

31                 9        7        5           0   < bit number
|                  |        |        |           |
[     not used     | gpio-1 | gpio-0 | <-shift-> ]   < 32 bit register
                       ^        ^
                       |        |
                write 0x2 == set output to "1" (activate)
                write 0x3 == set output to "0" (deactivate)

As of tooday we only support fixed (hardcoded) bit per gpio line,
activate / deactivatei and shift values. Fix that by read them from
device tree to be able to use this driver for other boards.

Remove "hsdk" prefix from compatible string as this driver can be
used with different boards like HSDK, AXS101, AXS103, etc.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Tom Rini
406fd7e207 Patch queue for efi - 2018-07-25
Highlights this time:
 
   - Many small fixes to improve spec compatibility (found by SCT)
   - Almost enough to run with sandbox target
   - GetTime() improvements
   - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-07-25

Highlights this time:

  - Many small fixes to improve spec compatibility (found by SCT)
  - Almost enough to run with sandbox target
  - GetTime() improvements
  - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
2018-07-30 16:02:29 -04:00
Michal Simek
58008cbab5 Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00
Michal Simek
08a00cba06 dm: Change CMD_DM enabling
CMD_DM is used for debug purpose and it shouldn't be enabled by default
via Kconfig. Unfortunately this is in the tree for quite a long time
that's why solution is to use imply DM for all targets which are
enabling DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00
Michal Simek
5ed063d10f Kconfig: Sort bool, default, select and imply options
Fix Kconfig bool, default, select and imply options to be
alphabetically sorted.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-07-30 07:18:48 -04:00
Michal Simek
6e7bdde4fe Kconfig: Replace spaces with tabs and missing newline
Trivial Kconfig cleanup. Use tabs instead of spaces and every Kconfig
entry should be separated by newline.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:47 -04:00
Tom Rini
0e8a8a3110 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-07-27 13:09:30 -04:00
Tom Rini
53885e76ce Merge branch 'master' of git://git.denx.de/u-boot-tegra 2018-07-26 23:12:39 -04:00
Tom Warren
2eea126916 tegra: beaver/apalis: Fix DTC warning
Fix warning when compiling tegra30-beaver/-apalis.dts with latest DTC:

  "Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary
   #address-cells/#size-cells without "ranges" or child "reg" property"

Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:31 -07:00
Stephen Warren
6e584e633d ARM: tegra: avoid using secure carveout RAM
If a secure carveout exists, U-Boot cannot use that memory. Fix
carveout_size() to reflect this, and hence transitively fix
usable_ram_size_below_4g() and board_get_usable_ram_top(). This change
ensures that when U-Boot copies the secure monitor code to install it, the
copy target is not in-use for U-Boot code/data.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:30 -07:00
Stephen Warren
74c69cdcc0 ARM: PSCI: Enable the PSCI node
When fixing up the DT to report PSCI support, explicitly enable the node.
DTs may ship with the node disabled in case a PSCI implementation is not
present, and expect any PSCI implementation to enable the node if they are
actually present.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:30 -07:00
Stephen Warren
326bd726d0 ARM: PSCI: Support PSCI v0.2
Enhance the PSCI DT editing code to allow setting a PSCI v0.2 compatible
value in the DT. The CONFIG_ option is added to the whitelist to match the
existing PSCI_1_0 option. While not adding new options to Kconfig isn't
ideal, I figure it's better to keep related options together.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:30 -07:00
Stephen Warren
3e3b2b4776 ARM: define MON_MODE
Add a MON_MODE define for ARM's monitor mode. This can be used later by
a secure monitor to avoid hard-coding mode IDs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:30 -07:00
Bibek Basu
3cc7942a4a ARM: tegra: implement RAM repair
RAM repair has a few pre-requisites:
1) PMIC power supply (rail) enabled.
2) PMC CRAIL power partition powered.
3) Fuse clock active (it's the default).
4) PLLP reshift branch enabled (it's the default, when PLLP is active).

RAM repair also only need run whenever specific partitions are powered
(main SoC and CCPLEX respectively); RAM repair does not need to be
triggered when any other partition changes state.

start_cpu() needs to be re-ordered slightly to match these requirements.
Note that C0NC and CE0 aren't required for RAM repair to
operate, but they also do no harm, so the entire of powerup_cpus() is
moved rather than splitting it up. The call to remove_cpu_resets() is
moved last to ensure that all other actions complete before releasing
reset; since the PMC power partitions are now enabled early, releasing
reset is what causes the CPUs to start executing code, and RAM repair must
complete before the CPU boots.

Note that this commit is the result of squashing a numbmer of commits
in NVIDIA's downstream L4T branch, hence the multiple signoffs below.

Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:29 -07:00
Stephen Warren
daebd48fe8 Revert "tegra: Introduce SRAM repair on tegra124"
This reverts commit 701b7b1d2c. It will
be immediately replaced by a different implementation that is more
complete and runs are more targetted times.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:29 -07:00
Tom Rini
a57d45db90 Merge branch 'master' of git://git.denx.de/u-boot-net 2018-07-26 15:55:42 -04:00
Joe Hershberger
9cce566321 arm: Prevent redefinition error in fsl-layerscape
The include/phy.h will start including dm.h, which pulls in
linux/compat.h after the attempted redefinition in
arch/arm/include/asm/armv8/mmu.h, so move this include to allow
redefinition.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:21 -05:00
Joe Hershberger
f40a31e695 sandbox: eth-raw: Add a SIMPLE_BUS to enumerate host interfaces
Ask the OS for each of its interfaces and for each one, bind a U-Boot
device and then probe it. This will allocate the priv data structure
that is then populated.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:19 -05:00
Joe Hershberger
c9e2caff85 sandbox: eth-raw: Allow interface to be specified by index
With systemd stable interface names, eth0 will almost never exist.
Instead of using that name in the sandbox.dts, use an index.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
ac13270b49 sandbox: eth-raw: Add a function to ask the host about localhost
Instead of doing a simple string compare against "lo", look for the flag
that indicates a localhost interface.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
8c7988b6db net: sandbox-raw: Convert raw eth driver to livetree
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
50ed0ef832 sandbox: eth-raw: Make sure descriptors are always initialized
If we let descriptors equal 0, we can end up closing STDIN. Make sure
they start out as -1.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:17 -05:00
Joe Hershberger
c6fa51a499 sandbox: Fix format of fake-host-hwaddr in test.dts
test.dts specified the fake MAC address as a u32 array. Instead it
should be a u8 array.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:17 -05:00
Joe Hershberger
97367df109 sandbox: eth-raw: Correct valid socket test in send/recv
In open, the socket is correctly checked to be -1 in the error case.
In send and recv, we checked for 0, but that is a valid socket number.

Correct this by checking for -1 as a bad socket everywhere.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:17 -05:00
York Sun
038b965c2b armv8: ls1046ardb: Add falcon mode for for QSPI boot
A new defconfig is introduced to support SPL boot from QSPI NOR
flash. This is to support falcon mode for faster booting into
Linux.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 11:51:23 -07:00
York Sun
9960609275 armv8: layerscape: spl: Initialize QSPI AHB for QSPI boot
To get full access of QSPI space, initialize AHB interface.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Yuantian Tang
86bff2bb09 armv8: dts: fsl-ls1012a: add sata node support
One ls1012a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Yuantian Tang
ed167eb1c7 armv8: fsl: remove sata support
Remove the old implementation in order to enable DM for sata.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
York Sun
61ab8aac60 armv8: layerscape: Enabled I-cache for SPL boot
Enable I-cache for SPL boot to boost performance. Earlier MMU was
enabled only for LS2080A and has since been dropped by commit
f539c8a4a7 ("armv8: ls2080a: Drop early MMU for SPL build").

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Tom Rini
ff6bef4852 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-07-26 11:43:26 -04:00
Tom Rini
de4b4ef36f Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-07-26 11:43:23 -04:00
Alexander Graf
42a3d42688 x86: Add efi_loader bits to x86_64 linker script
The x86_64 linker script was missing efi runtime information. Add it.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:44 +02:00
Alexander Graf
7e21fbca26 efi_loader: Rename sections to allow for implicit data
Some times gcc may generate data that is then used within code that may
be part of an efi runtime section. That data could be jump tables,
constants or strings.

In order to make sure we catch these, we need to ensure that gcc emits
them into a section that we can relocate together with all the other
efi runtime bits. This only works if the -ffunction-sections and
-fdata-sections flags are passed and the efi runtime functions are
in a section that starts with ".text".

Up to now we had all efi runtime bits in sections that did not
interfere with the normal section naming scheme, but this forces
us to do so. Hence we need to move the efi_loader text/data/rodata
sections before the global *(.text*) catch-all section.

With this patch in place, we should hopefully have an easier time
to extend the efi runtime functionality in the future.

Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: Fix x86_64 breakage]
2018-07-25 14:57:44 +02:00
Alexander Graf
dae73c4cdc elf: Move x86 reloc defines to common elf.h
We need to know about x86 relocation definitions even in cases where
we don't officially build against the x86 target, such as with sandbox.

So let's move the x86 definitions into the common elf header, where all
other architectures already have them.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Mark Kettenis
d32e86bde8 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
ARMV7_LPAE is required in order to enable the MMU in HYP mode.
And we really want to enable the MMU in HYP mode such that we can
enable the the caches.  Otherwise U-Boot code (such as the EFI
implementation) that runs in HYP mode will run at a snils pace.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Mark Kettenis
907ee2945e ARM: HYP/non-sec: migrate stack
The current code that switches into HYP mode doesn't bother to set
up a stack for HYP mode.  This doesn't work for EFI applications
as they expect a usable stack.  Fix this by migrating the stack
pointer from SP_svc to SP_hyp while in Monitor mode.
This restores the stack pointer when we drop into HYP mode.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Masahiro Yamada
7ef5b1e7ed ARM: uniphier: enable distro boot
Switch to the distro boot for UniPhier platform.

 - Remove the environment vairalbes used to load images from raw
   block devices.

 - Keep the command to download images via tftp.  This will be
   useful to boot the kernel when no valid kernel image is ready
   yet in the file system.

 - Use root.cpio.gz instead of root.cpio.uboot because we always know
   the file size of the init ramdisk; it is loaded via either a file
   system or network.

 - Rename fit_addr_r to kernel_addr_r, which the distro command
   checks to get the load address of FIT image.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:53 +09:00
Masahiro Yamada
bb04d2ec4d ARM: uniphier: support fdt_fixup_mtdparts
Propagate the "mtdparts" environment variable to the DT passed
in to OS.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:53 +09:00
Masahiro Yamada
65fce76301 ARM: uniphier: split ft_board_setup() out to a separate file
Prepare to add more fdt fixup code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:53 +09:00
Masahiro Yamada
e968715302 ARM: uniphier: clean-up ft_board_setup()
The 'bd' is passed in ft_board_setup() as the second argument.
Replace 'gd->bd' with 'bd'.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:53 +09:00
Marek Vasut
a6759e3dfc ARM: rmobile: gen2: Enable ACTLR[0] (Enable invalidates of BTB) to facilitate CVE_2017-5715 WA in OS
Enable CVE_2017_5715 mitigation on CPU0 on R-Car H2, M2W, M2N, V2H,
which all contain Cortex-A15 cores. R-Car E2 contains only Cortex-A7
cores and is not affected. Without this enabled, Linux kernel reports:

  CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable

With this enabled, Linux kernel reports:

  CPU0: Spectre v2: using ICIALLU workaround

NOTE: This by itself does not enable the workaround for other CPUs
      than CPU0 and may require additional kernel patches for the
      other CPUs in SMP configurations.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-07-25 00:14:19 +02:00
Marek Vasut
64eeb15854 ARM: dts: socfpga: Adjust NAND register layout on Arria10
Adjust the NAND register size on Arria10 to reflect reality.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-25 00:13:32 +02:00
Marek Vasut
42f4b83b52 ARM: socfpga: Init missing security policies on A10
The Arria10 requires proper configuration of the NOC firewall, otherwise
the access to certain areas of the LWHPS bridge fails in Linux. Add the
missing setup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-25 00:13:32 +02:00
Marek Vasut
937db7188e ARM: socfpga: Assure correct CPACR configuration
Make sure the ARM CPACR register is zeroed out, this is mandatory
on Arria10.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-25 00:13:32 +02:00
Ley Foon Tan
00057eea66 arm: socfpga: Fixes: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET
Commit bfc6bae8fa

This commit rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET. Update
with new CONFIG name and enable CONFIG_SPL_DM_RESET when CONFIG_DM_RESET is enabled.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
2018-07-25 00:13:32 +02:00
Adam Ford
d7cc15bb53 ARM: DTS: am3517-evm-u-boot: Mark MMC1 with cd-inverted
In order to use the device tree for MMC, the card-detect pin
needs to be inverted.  This patch places this into the
am3517-evm-u-boot.dtsi file to keep the main DTS and DTSI files
clean and in-sync with Linux

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
972edd4930 ARM: dts: am3517-evm-uboot: Add reg-shift for UART
With the resync of the omap3.dtsi file, the reg-shift was removed
so it breaks the UART.  Adding the reg-shift into the
am3517-evm-u-boot.dtsi keeps the reg-shift for U-Boot, but keeps
the dts/dtsi files clean from Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
5448ff33f2 ARM: DTS: Resync Logic PD SOM-LV 37xx devkit with Linux 4.18-RC4
There have been some significant changes to the DM37 SOM-LV device
tree.  This patch re-syncs it with Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
e6ea2390cd ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit with Linux 4.18-RC4
There have been some refactoring of the DTS files for the Logic PD
DM37 Torpedo.  This patch re-sync's the DTS files with Linux

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
66dae3bbca ARM: dts: Resync OMAP3 and omap36xx with Linux 4.18-RC4
There have been several minor changes to the OMAP3.dtsi, so this
patch re-syncs it with Linux.  An addition include/dt-binding was
also brought with it.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
b8dbec5fb6 ARM: DTS: Resync am3517-evm.dts with Linux 4.18-rc4
Several changes have been made to the AM3517-evm and the underlying
am3517.dtsi file.  This patch re-sync's the DTS and DTSI files with
Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Tom Rini
b740074ac4 m68k: m5253evbe: Remove this board
The m5253evbe board has been marked as orphan since June of 2014 and
should have been dropped a while ago.  Do so now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-23 14:33:21 -04:00
Martin Kaiser
0d38a5fd44 mx25: fix the offset between the USB ports' registers
The USBOH module on imx25 chips contains two USB controllers which are
called USB OTG Controller and USB Host Controller. Each one has its EHCI
root hub. The OTG Controller's EHCI registers start at offset 0, the Host
Controller's registers start at offset 0x400.

We set CONFIG_MXC_USB_PORT=0 to select the OTG Controller and 1 for the
Host Controller. Therefore, IMX_USB_PORT_OFFSET must be 0x400. Using
this setting, the Host Controller starts working on my imx25 board.

Please note that the imx25 reference manual claims that the Host
Controller's registers start at 0x200. This is not correct. The Linux
Kernel uses the correct offset 0x400 in imx25.dtsi.

Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-07-23 11:05:04 +02:00
Adam Ford
bbbb50f9fd imx: i.mx6q: imx6q_logic: Migrate to SPL and enable SDP
Since the vast majority of i.MX6 boards are migrating to SPL,
this patch converts im6q_logic to SPL and enables the SDP for
loading SPL and u-boot.img over USB.  The Falcon mode only
supports NAND flash as of now due to limited space/RAM, but
all i.MX6D/Q SOM's from Logic PD have internal NAND from which
to boot.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 11:03:20 +02:00
Fabio Estevam
d5b7177f91 pico-imx7d: Add SPL support
Convert pico-imx7d to SPL support.

There are two variants of pico-imx7d SOMs:
- One with 512MB of RAM
- One with 1GB of RAM

The 512MB module contains two Hynix H5TC2G63GFR-PBA.
The 1GB module contains two Hynix H5TC4G63GFR-PBA.

The RAM size is determined in runtime by reading GPIO1_12.

While at it, also add USB Serial Download mode support as it
is very helpful for loading SPL and u-boot.img via imx_usb_loader.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2018-07-23 10:59:48 +02:00
Mark Jonas
9ea7519383 arm, imx6: add alternative PAD_CTL_DSE constants
Not all i.MX6 pads use the same drive strength table. So far only the
240 Ohm to 34 Ohm table was available. Because the constants used have
speaking names it can be confusing to use e.g. PAD_CTL_DSE_48ohm when
according to the reference manual 52 Ohm is the correct value. This
patch adds the 260 Ohm to 37 Ohm table.

For example, the IOMUXC_SW_PAD_CTL_PAD_SD2_CLK register (SD-card clock)
uses the added table.

Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-07-23 10:57:39 +02:00
Stefan Agner
f97df68898 imx: mx7: psci: implement MIGRATE_INFO_TYPE
Implement MIGRATE_INFO_TYPE. This informs Linux that no migration
for the trusted operating system is necessary:
  [    0.000000] psci: Trusted OS migration not required

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:54:32 +02:00
Stefan Agner
28a5af11f8 imx: mx7: psci: support CPU0 on/off
So far psci_cpu_(on|off) only worked for CPU1. Allow to control
CPU0 too. This allows to run the Linux PSCI checker successfully:
  [    2.213447] psci_checker: PSCI checker started using 2 CPUs
  [    2.219107] psci_checker: Starting hotplug tests
  [    2.223859] psci_checker: Trying to turn off and on again all CPUs
  [    2.267191] IRQ21 no longer affine to CPU0
  [    2.293266] Retrying again to check for CPU kill
  [    2.302269] CPU0 killed.
  [    2.311648] psci_checker: Trying to turn off and on again group 0 (CPUs 0-1)
  [    2.354354] IRQ21 no longer affine to CPU0
  [    2.383222] Retrying again to check for CPU kill
  [    2.392148] CPU0 killed.
  [    2.398063] psci_checker: Hotplug tests passed OK
  [    2.402910] psci_checker: Starting suspend tests (10 cycles per state)
  [    2.410019] psci_checker: cpuidle not available on CPU 0, ignoring
  [    2.416452] psci_checker: cpuidle not available on CPU 1, ignoring
  [    2.422757] psci_checker: Could not start suspend tests on any CPU
  [    2.429370] psci_checker: PSCI checker completed

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:54:23 +02:00
Stefan Agner
a89eb89b38 imx: mx7: psci: provide complete PSCI 1.0 implementation
PSCI 1.0 require PSCI_VERSION, PSCI_FEATURES, AFFINITY_INFO and
CPU_SUSPEND to be implemented. Commit 0ec3d98f76 ("mx7_common:
use psci 1.0 instead of 0.1") marked the i.MX 7 implementation to
be PSCI 1.0 compliant but failed to implement those functions.
Especially the missing PSCI version callback was noticeable when
booting Linux:

  [    0.000000] psci: probing for conduit method from DT.
  [    0.000000] psci: PSCIv65535.65535 detected in firmware.
  [    0.000000] psci: Using standard PSCI v0.2 function IDs
  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.
  [    0.000000] psci: SMC Calling Convention v1.0

This patch provides a minimal implementation thereof. With this
patch applied Linux detects PSCI 1.0:

  [    0.000000] psci: probing for conduit method from DT.
  [    0.000000] psci: PSCIv1.0 detected in firmware.
  [    0.000000] psci: Using standard PSCI v0.2 function IDs
  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.
  [    0.000000] psci: SMC Calling Convention v1.0

Fixes: 0ec3d98f76 ("mx7_common: use psci 1.0 instead of 0.1")
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:54:01 +02:00
Stefan Agner
cff38c5504 imx: mx7: psci: use C code exclusively
There is no need for assembly in the platform specific part of
the PSCI implementation.

Note that this does not make it a complete PSCI 1.0 implementation
yet but aids to do so in upcoming patches.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:53:42 +02:00
Stefan Agner
77fcc2cc90 ARM: PSCI: initialize stack pointer on secondary CPUs
A proper stack is required to safely use C code in psci_arch_cpu_entry.

Fixes: 486daaa618 ("arm: psci: add a weak function psci_arch_cpu_entry")
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Patrick DELAUNAY <Patrick.delaunay@st.com>
Tested-by: Patrick DELAUNAY <Patrick.delaunay@st.com>
2018-07-23 10:53:12 +02:00
Michael Trimarchi
4a72abcb71 imx: imx6: Add comment to gpr_init function
This function can be used only for some of the nxp SoC. Make
it explicit in the comment. This adjust a bit commit
3aa4b703b4 ("imx: imx6: Move gpr_init() function to soc.c")

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-23 10:50:53 +02:00
Fabio Estevam
2756d31fae mx7: Remove BMODE support
i.MX7 does not support BMODE due to the erratum e10574 ("Watchdog:
A watchdog timeout or software trigger will not reset the SOC"), so
remove its support.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-07-23 10:50:00 +02:00
Michael Trimarchi
9236269de5 imx: mx6: Fix implementantion reset_misc
lcdif_power_down should not be included in spl build to avoid build
failure introduced by commit eb111bb31d

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-07-23 10:31:52 +02:00
Stefan Agner
31b1e17f44 board: toradex: add Colibri iMX6ULL support
Add support for the Colibri iMX6ULL module which comes with
on-board raw NAND.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:12:00 +02:00
Stefan Agner
55f34f3a9e ARM: dts: imx6ull: use same compatible string as Linux is using
The GPMI NAND IP seems to be the same as used in i.MX 6Quad. Use
the fsl,imx6q-gpmi-nand compatible string like Linux devices trees
are.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:12:00 +02:00
Stefan Agner
23eaf4180f imx: add macro to detect whether USB has been initialized
This macro allows to detect whether the boot ROM initialized USB
already (serial downloader). This is helpful to reliably detect
if the system has been recovered via USB serial downloader.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-07-23 10:12:00 +02:00
Tom Rini
83853366e3 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2018-07-20 22:35:49 -04:00
Carlo Caione
315ded9730 rockchip: veyron: Set vcc33_sd regulator value
On the veyron board the vcc33_sd regulator is used as vmmc-supply for
the SD card. This regulator is powered in the MMC core during power on
but its value is never actually set.

In the veyron platform the reset value for the LDO output is 1.8V while
the standard (min and max) value for this regulator defined in the DTS
is 3.3V. When the MMC core enable the regulator without setting its
value, the output is automatically set to 1.8V instead of 3.3V.

With this patch we preemptively set the value to 3.3V.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Carlo Caione
389167c3c4 rk3288: Disable JTAG function from sdmmc0 IO
The GRF_SOC_CON0.grf_force_jtag bit is automatically set at boot and it
is preventing the SDMMC to work correctly. Disable the JTAG function on
the assumption that a working SD has higher priority over JTAG.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Carlo Caione
0d4d5fd73c rk3288: veyron: Init boot-on regulators
Use regulators_enable_boot_on() to init all the regulators with
regulator-boot-on property.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Heinrich Schuchardt
9125947687 rockchip: rk3399: spl: add missing \n to output
Without the patch SPL (in case of an error) creates an output like:

	U-Boot SPL board initMissing DTB

The patch adds the missing line feed. So now we get:

	U-Boot SPL board init
	Missing DTB

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:26 +02:00
Philipp Tomsich
e5f2ecc750 rockchip: rk3399: inject 'u-boot, spl-boot-device' for next-stage
This implements the new 'spl_perform_fixups' hook for RK3399-based
boards and injects the /chosen/u-boot,spl-boot-device with an ofpath
corresponding to the boot device used.

The intended usage is for the full U-Boot stage to evaluate this in
scripts and then adapt its boot-order when using distro-boot.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-07-21 01:55:26 +02:00
Alexander Kochetkov
706afa46c7 rockchip: rk3188: add rk_board_late_init() hook
All other rockchip boards have rk_board_late_init() hook,
so add it to rk3188 boards also.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:25 +02:00
Tom Rini
e0ed8332fa Merge git://git.denx.de/u-boot-x86 2018-07-20 19:31:30 -04:00
Loic Devulder
77dd09211b ARM64: meson: Sync DT with Linux 4.17.5
Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.17.5
(Linux commit 54fb3c180d05e9dfda892a93413514e99f0cbb19).

This will enable HDMI_5V for USB Amlogic Meson GXL P212 based boards.

Signed-off-by: Loic Devulder <ldevulder@suse.de>
2018-07-20 15:55:09 -04:00
Patrick Delaunay
8a07d5bfe1 stm32mp1: clock tree update
Configure clock tree for all the devices.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20 15:55:06 -04:00
Patrick Delaunay
5f16f655cc stm32mp1: add support for stm32mp157c-ev1 board
Add support of stm32mp157c-ev1, the evaluation board with pmic stpmu1
(ev1 = mother board + daughter ed1) with device tree.
EV1 is the selected board by default in basic defconfig.

PS: CONFIG_PINCTRL_FULL activation avoid to increase
    SYS_MALLOC_F_LEN (Early malloc usage: 2034)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20 15:55:05 -04:00